]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/mfd/sm501.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'kvm-ppc-fixes-4.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / sm501.c
CommitLineData
b6d6454f
BD		 1/* linux/drivers/mfd/sm501.c
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * SM501 MFD driver
12*/
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/list.h>
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/pci.h>
42cd2366 22#include <linux/i2c-gpio.h>
b2e63555 23#include <linux/gpio/machine.h>
5a0e3ad6 24#include <linux/slab.h>
b6d6454f
BD		 25
26#include <linux/sm501.h>
27#include <linux/sm501-regs.h>
61711f8f 28#include <linux/serial_8250.h>
b6d6454f 29
f77401d4 30#include <linux/io.h>
b6d6454f
BD		 31
32struct sm501_device {
33 struct list_head list;
34 struct platform_device pdev;
35};
36
f61be273
BD		 37struct sm501_gpio;
38
f2999209
BD		 39#ifdef CONFIG_MFD_SM501_GPIO
40#include <linux/gpio.h>
41
f61be273
BD		 42struct sm501_gpio_chip {
43 struct gpio_chip gpio;
44 struct sm501_gpio *ourgpio; /* to get back to parent. */
45 void __iomem *regbase;
98325f8f 46 void __iomem *control; /* address of control reg. */
f61be273
BD		 47};
48
49struct sm501_gpio {
50 struct sm501_gpio_chip low;
51 struct sm501_gpio_chip high;
52 spinlock_t lock;
53
54 unsigned int registered : 1;
55 void __iomem *regs;
56 struct resource *regs_res;
57};
f2999209
BD		 58#else
59struct sm501_gpio {
60 /* no gpio support, empty definition for sm501_devdata. */
61};
62#endif
f61be273 63
b6d6454f
BD		 64struct sm501_devdata {
65 spinlock_t reg_lock;
66 struct mutex clock_lock;
67 struct list_head devices;
f61be273 68 struct sm501_gpio gpio;
b6d6454f
BD		 69
70 struct device *dev;
71 struct resource *io_res;
72 struct resource *mem_res;
73 struct resource *regs_claim;
74 struct sm501_platdata *platdata;
75
f61be273 76
331d7475
BD		 77 unsigned int in_suspend;
78 unsigned long pm_misc;
79
b6d6454f
BD		 80 int unit_power[20];
81 unsigned int pdev_id;
82 unsigned int irq;
83 void __iomem *regs;
3149be50 84 unsigned int rev;
b6d6454f
BD		 85};
86
f61be273 87
b6d6454f
BD		 88#define MHZ (1000 * 1000)
89
90#ifdef DEBUG
245904a4 91static const unsigned int div_tab[] = {
b6d6454f
BD		 92 [0] = 1,
93 [1] = 2,
94 [2] = 4,
95 [3] = 8,
96 [4] = 16,
97 [5] = 32,
98 [6] = 64,
99 [7] = 128,
100 [8] = 3,
101 [9] = 6,
102 [10] = 12,
103 [11] = 24,
104 [12] = 48,
105 [13] = 96,
106 [14] = 192,
107 [15] = 384,
108 [16] = 5,
109 [17] = 10,
110 [18] = 20,
111 [19] = 40,
112 [20] = 80,
113 [21] = 160,
114 [22] = 320,
115 [23] = 604,
116};
117
118static unsigned long decode_div(unsigned long pll2, unsigned long val,
119 unsigned int lshft, unsigned int selbit,
245904a4 120 unsigned long mask)
b6d6454f
BD		 121{
122 if (val & selbit)
123 pll2 = 288 * MHZ;
124
245904a4 125 return pll2 / div_tab[(val >> lshft) & mask];
b6d6454f
BD		 126}
127
128#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
129
130/* sm501_dump_clk
131 *
132 * Print out the current clock configuration for the device
133*/
134
135static void sm501_dump_clk(struct sm501_devdata *sm)
136{
bf5f0019
HS		 137 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);
138 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
139 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
140 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
b6d6454f
BD		 141 unsigned long sdclk0, sdclk1;
142 unsigned long pll2 = 0;
143
144 switch (misct & 0x30) {
145 case 0x00:
146 pll2 = 336 * MHZ;
147 break;
148 case 0x10:
149 pll2 = 288 * MHZ;
150 break;
151 case 0x20:
152 pll2 = 240 * MHZ;
153 break;
154 case 0x30:
155 pll2 = 192 * MHZ;
156 break;
157 }
158
159 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
245904a4 160 sdclk0 /= div_tab[((misct >> 8) & 0xf)];
b6d6454f
BD		 161
162 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
245904a4 163 sdclk1 /= div_tab[((misct >> 16) & 0xf)];
b6d6454f
BD		 164
165 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
166 misct, pm0, pm1);
167
168 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
169 fmt_freq(pll2), sdclk0, sdclk1);
170
171 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
172
173 dev_dbg(sm->dev, "PM0[%c]: "
174 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
48986f06 175 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
b6d6454f 176 (pmc & 3 ) == 0 ? '*' : '-',
245904a4
VS		 177 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
178 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
179 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),
180 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));
b6d6454f
BD		 181
182 dev_dbg(sm->dev, "PM1[%c]: "
183 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
184 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
185 (pmc & 3 ) == 1 ? '*' : '-',
245904a4
VS		 186 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
187 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
188 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),
189 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));
b6d6454f 190}
331d7475
BD		 191
192static void sm501_dump_regs(struct sm501_devdata *sm)
193{
194 void __iomem *regs = sm->regs;
195
196 dev_info(sm->dev, "System Control %08x\n",
bf5f0019 197 smc501_readl(regs + SM501_SYSTEM_CONTROL));
331d7475 198 dev_info(sm->dev, "Misc Control %08x\n",
bf5f0019 199 smc501_readl(regs + SM501_MISC_CONTROL));
331d7475 200 dev_info(sm->dev, "GPIO Control Low %08x\n",
bf5f0019 201 smc501_readl(regs + SM501_GPIO31_0_CONTROL));
331d7475 202 dev_info(sm->dev, "GPIO Control Hi %08x\n",
bf5f0019 203 smc501_readl(regs + SM501_GPIO63_32_CONTROL));
331d7475 204 dev_info(sm->dev, "DRAM Control %08x\n",
bf5f0019 205 smc501_readl(regs + SM501_DRAM_CONTROL));
331d7475 206 dev_info(sm->dev, "Arbitration Ctrl %08x\n",
bf5f0019 207 smc501_readl(regs + SM501_ARBTRTN_CONTROL));
331d7475 208 dev_info(sm->dev, "Misc Timing %08x\n",
bf5f0019 209 smc501_readl(regs + SM501_MISC_TIMING));
331d7475
BD		 210}
211
212static void sm501_dump_gate(struct sm501_devdata *sm)
b6d6454f 213{
331d7475 214 dev_info(sm->dev, "CurrentGate %08x\n",
bf5f0019 215 smc501_readl(sm->regs + SM501_CURRENT_GATE));
331d7475 216 dev_info(sm->dev, "CurrentClock %08x\n",
bf5f0019 217 smc501_readl(sm->regs + SM501_CURRENT_CLOCK));
331d7475 218 dev_info(sm->dev, "PowerModeControl %08x\n",
bf5f0019 219 smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));
b6d6454f 220}
331d7475
BD		 221
222#else
223static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
224static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
225static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
b6d6454f
BD		 226#endif
227
228/* sm501_sync_regs
229 *
230 * ensure the
231*/
232
233static void sm501_sync_regs(struct sm501_devdata *sm)
234{
bf5f0019 235 smc501_readl(sm->regs);
b6d6454f
BD		 236}
237
331d7475
BD		 238static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
239{
240 /* during suspend/resume, we are currently not allowed to sleep,
241 * so change to using mdelay() instead of msleep() if we
242 * are in one of these paths */
243
244 if (sm->in_suspend)
245 mdelay(delay);
246 else
247 msleep(delay);
248}
249
b6d6454f
BD		 250/* sm501_misc_control
251 *
331d7475 252 * alters the miscellaneous control parameters
b6d6454f
BD		 253*/
254
255int sm501_misc_control(struct device *dev,
256 unsigned long set, unsigned long clear)
257{
258 struct sm501_devdata *sm = dev_get_drvdata(dev);
259 unsigned long misc;
260 unsigned long save;
261 unsigned long to;
262
263 spin_lock_irqsave(&sm->reg_lock, save);
264
bf5f0019 265 misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
b6d6454f
BD		 266 to = (misc & ~clear) | set;
267
268 if (to != misc) {
bf5f0019 269 smc501_writel(to, sm->regs + SM501_MISC_CONTROL);
b6d6454f
BD		 270 sm501_sync_regs(sm);
271
272 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
273 }
274
275 spin_unlock_irqrestore(&sm->reg_lock, save);
276 return to;
277}
278
279EXPORT_SYMBOL_GPL(sm501_misc_control);
280
281/* sm501_modify_reg
282 *
283 * Modify a register in the SM501 which may be shared with other
284 * drivers.
285*/
286
287unsigned long sm501_modify_reg(struct device *dev,
288 unsigned long reg,
289 unsigned long set,
290 unsigned long clear)
291{
292 struct sm501_devdata *sm = dev_get_drvdata(dev);
293 unsigned long data;
294 unsigned long save;
295
296 spin_lock_irqsave(&sm->reg_lock, save);
297
bf5f0019 298 data = smc501_readl(sm->regs + reg);
b6d6454f
BD		 299 data |= set;
300 data &= ~clear;
301
bf5f0019 302 smc501_writel(data, sm->regs + reg);
b6d6454f
BD		 303 sm501_sync_regs(sm);
304
305 spin_unlock_irqrestore(&sm->reg_lock, save);
306
307 return data;
308}
309
310EXPORT_SYMBOL_GPL(sm501_modify_reg);
311
b6d6454f
BD		 312/* sm501_unit_power
313 *
314 * alters the power active gate to set specific units on or off
315 */
316
317int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
318{
319 struct sm501_devdata *sm = dev_get_drvdata(dev);
320 unsigned long mode;
321 unsigned long gate;
322 unsigned long clock;
323
324 mutex_lock(&sm->clock_lock);
325
bf5f0019
HS		 326 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
327 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
328 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
b6d6454f
BD		 329
330 mode &= 3; /* get current power mode */
331
bf703c3f 332 if (unit >= ARRAY_SIZE(sm->unit_power)) {
145980a0 333 dev_err(dev, "%s: bad unit %d\n", __func__, unit);
b6d6454f
BD		 334 goto already;
335 }
336
145980a0 337 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
b6d6454f
BD		 338 sm->unit_power[unit], to);
339
340 if (to == 0 && sm->unit_power[unit] == 0) {
341 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
342 goto already;
343 }
344
345 sm->unit_power[unit] += to ? 1 : -1;
346 to = sm->unit_power[unit] ? 1 : 0;
347
348 if (to) {
349 if (gate & (1 << unit))
350 goto already;
351 gate |= (1 << unit);
352 } else {
353 if (!(gate & (1 << unit)))
354 goto already;
355 gate &= ~(1 << unit);
356 }
357
358 switch (mode) {
359 case 1:
bf5f0019
HS		 360 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
361 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
b6d6454f
BD		 362 mode = 0;
363 break;
364 case 2:
365 case 0:
bf5f0019
HS		 366 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
367 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
b6d6454f
BD		 368 mode = 1;
369 break;
370
371 default:
992bb253
JS		 372 gate = -1;
373 goto already;
b6d6454f
BD		 374 }
375
bf5f0019 376 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
b6d6454f
BD		 377 sm501_sync_regs(sm);
378
379 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
380 gate, clock, mode);
381
331d7475 382 sm501_mdelay(sm, 16);
b6d6454f
BD		 383
384 already:
385 mutex_unlock(&sm->clock_lock);
386 return gate;
387}
388
389EXPORT_SYMBOL_GPL(sm501_unit_power);
390
b6d6454f
BD		 391/* clock value structure. */
392struct sm501_clock {
393 unsigned long mclk;
394 int divider;
395 int shift;
3149be50 396 unsigned int m, n, k;
b6d6454f
BD		 397};
398
3149be50
VS		 399/* sm501_calc_clock
400 *
401 * Calculates the nearest discrete clock frequency that
402 * can be achieved with the specified input clock.
403 * the maximum divisor is 3 or 5
404 */
405
406static int sm501_calc_clock(unsigned long freq,
407 struct sm501_clock *clock,
408 int max_div,
409 unsigned long mclk,
410 long *best_diff)
411{
412 int ret = 0;
413 int divider;
414 int shift;
415 long diff;
416
417 /* try dividers 1 and 3 for CRT and for panel,
418 try divider 5 for panel only.*/
419
420 for (divider = 1; divider <= max_div; divider += 2) {
421 /* try all 8 shift values.*/
422 for (shift = 0; shift < 8; shift++) {
423 /* Calculate difference to requested clock */
829ecbcb 424 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
3149be50
VS		 425 if (diff < 0)
426 diff = -diff;
427
428 /* If it is less than the current, use it */
429 if (diff < *best_diff) {
430 *best_diff = diff;
431
432 clock->mclk = mclk;
433 clock->divider = divider;
434 clock->shift = shift;
435 ret = 1;
436 }
437 }
438 }
439
440 return ret;
441}
442
443/* sm501_calc_pll
444 *
445 * Calculates the nearest discrete clock frequency that can be
446 * achieved using the programmable PLL.
447 * the maximum divisor is 3 or 5
448 */
449
450static unsigned long sm501_calc_pll(unsigned long freq,
451 struct sm501_clock *clock,
452 int max_div)
453{
454 unsigned long mclk;
455 unsigned int m, n, k;
456 long best_diff = 999999999;
457
458 /*
459 * The SM502 datasheet doesn't specify the min/max values for M and N.
460 * N = 1 at least doesn't work in practice.
461 */
462 for (m = 2; m <= 255; m++) {
463 for (n = 2; n <= 127; n++) {
464 for (k = 0; k <= 1; k++) {
465 mclk = (24000000UL * m / n) >> k;
466
467 if (sm501_calc_clock(freq, clock, max_div,
468 mclk, &best_diff)) {
469 clock->m = m;
470 clock->n = n;
471 clock->k = k;
472 }
473 }
474 }
475 }
476
477 /* Return best clock. */
478 return clock->mclk / (clock->divider << clock->shift);
479}
480
b6d6454f
BD		 481/* sm501_select_clock
482 *
3149be50
VS		 483 * Calculates the nearest discrete clock frequency that can be
484 * achieved using the 288MHz and 336MHz PLLs.
b6d6454f
BD		 485 * the maximum divisor is 3 or 5
486 */
3149be50 487
b6d6454f
BD		 488static unsigned long sm501_select_clock(unsigned long freq,
489 struct sm501_clock *clock,
490 int max_div)
491{
492 unsigned long mclk;
b6d6454f
BD		 493 long best_diff = 999999999;
494
495 /* Try 288MHz and 336MHz clocks. */
496 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
3149be50 497 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
b6d6454f
BD		 498 }
499
500 /* Return best clock. */
501 return clock->mclk / (clock->divider << clock->shift);
502}
503
504/* sm501_set_clock
505 *
506 * set one of the four clock sources to the closest available frequency to
507 * the one specified
508*/
509
510unsigned long sm501_set_clock(struct device *dev,
511 int clksrc,
512 unsigned long req_freq)
513{
514 struct sm501_devdata *sm = dev_get_drvdata(dev);
bf5f0019
HS		 515 unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
516 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
517 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
3149be50 518 unsigned int pll_reg = 0;
3ad2f3fb 519 unsigned long sm501_freq; /* the actual frequency achieved */
5f114ebc 520 u64 reg;
b6d6454f
BD		 521
522 struct sm501_clock to;
523
524 /* find achivable discrete frequency and setup register value
525 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
526 * has an extra bit for the divider */
527
528 switch (clksrc) {
529 case SM501_CLOCK_P2XCLK:
3ad2f3fb 530 /* This clock is divided in half so to achieve the
b6d6454f
BD		 531 * requested frequency the value must be multiplied by
532 * 2. This clock also has an additional pre divisor */
533
3149be50
VS		 534 if (sm->rev >= 0xC0) {
535 /* SM502 -> use the programmable PLL */
536 sm501_freq = (sm501_calc_pll(2 * req_freq,
537 &to, 5) / 2);
538 reg = to.shift & 0x07;/* bottom 3 bits are shift */
539 if (to.divider == 3)
540 reg |= 0x08; /* /3 divider required */
541 else if (to.divider == 5)
542 reg |= 0x10; /* /5 divider required */
543 reg |= 0x40; /* select the programmable PLL */
544 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
545 } else {
546 sm501_freq = (sm501_select_clock(2 * req_freq,
547 &to, 5) / 2);
548 reg = to.shift & 0x07;/* bottom 3 bits are shift */
549 if (to.divider == 3)
550 reg |= 0x08; /* /3 divider required */
551 else if (to.divider == 5)
552 reg |= 0x10; /* /5 divider required */
553 if (to.mclk != 288000000)
554 reg |= 0x20; /* which mclk pll is source */
555 }
b6d6454f
BD		 556 break;
557
558 case SM501_CLOCK_V2XCLK:
3ad2f3fb 559 /* This clock is divided in half so to achieve the
b6d6454f
BD		 560 * requested frequency the value must be multiplied by 2. */
561
562 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
563 reg=to.shift & 0x07; /* bottom 3 bits are shift */
564 if (to.divider == 3)
565 reg |= 0x08; /* /3 divider required */
566 if (to.mclk != 288000000)
567 reg |= 0x10; /* which mclk pll is source */
568 break;
569
570 case SM501_CLOCK_MCLK:
571 case SM501_CLOCK_M1XCLK:
572 /* These clocks are the same and not further divided */
573
574 sm501_freq = sm501_select_clock( req_freq, &to, 3);
575 reg=to.shift & 0x07; /* bottom 3 bits are shift */
576 if (to.divider == 3)
577 reg |= 0x08; /* /3 divider required */
578 if (to.mclk != 288000000)
579 reg |= 0x10; /* which mclk pll is source */
580 break;
581
582 default:
583 return 0; /* this is bad */
584 }
585
586 mutex_lock(&sm->clock_lock);
587
bf5f0019
HS		 588 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
589 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
590 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
b6d6454f
BD		 591
592 clock = clock & ~(0xFF << clksrc);
593 clock |= reg<<clksrc;
594
595 mode &= 3; /* find current mode */
596
597 switch (mode) {
598 case 1:
bf5f0019
HS		 599 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
600 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
b6d6454f
BD		 601 mode = 0;
602 break;
603 case 2:
604 case 0:
bf5f0019
HS		 605 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
606 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
b6d6454f
BD		 607 mode = 1;
608 break;
609
610 default:
611 mutex_unlock(&sm->clock_lock);
612 return -1;
613 }
614
bf5f0019 615 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
3149be50
VS		 616
617 if (pll_reg)
bf5f0019
HS		 618 smc501_writel(pll_reg,
619 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
3149be50 620
b6d6454f
BD		 621 sm501_sync_regs(sm);
622
80e74a80
BD		 623 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
624 gate, clock, mode);
b6d6454f 625
331d7475 626 sm501_mdelay(sm, 16);
b6d6454f
BD		 627 mutex_unlock(&sm->clock_lock);
628
629 sm501_dump_clk(sm);
630
631 return sm501_freq;
632}
633
634EXPORT_SYMBOL_GPL(sm501_set_clock);
635
636/* sm501_find_clock
637 *
638 * finds the closest available frequency for a given clock
639*/
640
3149be50
VS		 641unsigned long sm501_find_clock(struct device *dev,
642 int clksrc,
b6d6454f
BD		 643 unsigned long req_freq)
644{
3149be50 645 struct sm501_devdata *sm = dev_get_drvdata(dev);
3ad2f3fb 646 unsigned long sm501_freq; /* the frequency achieveable by the 501 */
b6d6454f
BD		 647 struct sm501_clock to;
648
649 switch (clksrc) {
650 case SM501_CLOCK_P2XCLK:
3149be50
VS		 651 if (sm->rev >= 0xC0) {
652 /* SM502 -> use the programmable PLL */
653 sm501_freq = (sm501_calc_pll(2 * req_freq,
654 &to, 5) / 2);
655 } else {
656 sm501_freq = (sm501_select_clock(2 * req_freq,
657 &to, 5) / 2);
658 }
b6d6454f
BD		 659 break;
660
661 case SM501_CLOCK_V2XCLK:
662 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
663 break;
664
665 case SM501_CLOCK_MCLK:
666 case SM501_CLOCK_M1XCLK:
667 sm501_freq = sm501_select_clock(req_freq, &to, 3);
668 break;
669
670 default:
671 sm501_freq = 0; /* error */
672 }
673
674 return sm501_freq;
675}
676
677EXPORT_SYMBOL_GPL(sm501_find_clock);
678
679static struct sm501_device *to_sm_device(struct platform_device *pdev)
680{
681 return container_of(pdev, struct sm501_device, pdev);
682}
683
684/* sm501_device_release
685 *
686 * A release function for the platform devices we create to allow us to
687 * free any items we allocated
688*/
689
690static void sm501_device_release(struct device *dev)
691{
692 kfree(to_sm_device(to_platform_device(dev)));
693}
694
695/* sm501_create_subdev
696 *
697 * Create a skeleton platform device with resources for passing to a
698 * sub-driver
699*/
700
701static struct platform_device *
61711f8f
MD		 702sm501_create_subdev(struct sm501_devdata *sm, char *name,
703 unsigned int res_count, unsigned int platform_data_size)
b6d6454f
BD		 704{
705 struct sm501_device *smdev;
706
707 smdev = kzalloc(sizeof(struct sm501_device) +
61711f8f
MD		 708 (sizeof(struct resource) * res_count) +
709 platform_data_size, GFP_KERNEL);
b6d6454f
BD		 710 if (!smdev)
711 return NULL;
712
713 smdev->pdev.dev.release = sm501_device_release;
714
715 smdev->pdev.name = name;
716 smdev->pdev.id = sm->pdev_id;
b6d6454f
BD		 717 smdev->pdev.dev.parent = sm->dev;
718
61711f8f
MD		 719 if (res_count) {
720 smdev->pdev.resource = (struct resource *)(smdev+1);
721 smdev->pdev.num_resources = res_count;
722 }
723 if (platform_data_size)
724 smdev->pdev.dev.platform_data = (void *)(smdev+1);
725
b6d6454f
BD		 726 return &smdev->pdev;
727}
728
729/* sm501_register_device
730 *
731 * Register a platform device created with sm501_create_subdev()
732*/
733
734static int sm501_register_device(struct sm501_devdata *sm,
735 struct platform_device *pdev)
736{
737 struct sm501_device *smdev = to_sm_device(pdev);
738 int ptr;
739 int ret;
740
741 for (ptr = 0; ptr < pdev->num_resources; ptr++) {
3f3d4310
JP		 742 printk(KERN_DEBUG "%s[%d] %pR\n",
743 pdev->name, ptr, &pdev->resource[ptr]);
b6d6454f
BD		 744 }
745
746 ret = platform_device_register(pdev);
747
748 if (ret >= 0) {
749 dev_dbg(sm->dev, "registered %s\n", pdev->name);
750 list_add_tail(&smdev->list, &sm->devices);
751 } else
752 dev_err(sm->dev, "error registering %s (%d)\n",
753 pdev->name, ret);
754
755 return ret;
756}
757
758/* sm501_create_subio
759 *
760 * Fill in an IO resource for a sub device
761*/
762
763static void sm501_create_subio(struct sm501_devdata *sm,
764 struct resource *res,
765 resource_size_t offs,
766 resource_size_t size)
767{
768 res->flags = IORESOURCE_MEM;
769 res->parent = sm->io_res;
770 res->start = sm->io_res->start + offs;
771 res->end = res->start + size - 1;
772}
773
774/* sm501_create_mem
775 *
776 * Fill in an MEM resource for a sub device
777*/
778
779static void sm501_create_mem(struct sm501_devdata *sm,
780 struct resource *res,
781 resource_size_t *offs,
782 resource_size_t size)
783{
784 *offs -= size; /* adjust memory size */
785
786 res->flags = IORESOURCE_MEM;
787 res->parent = sm->mem_res;
788 res->start = sm->mem_res->start + *offs;
789 res->end = res->start + size - 1;
790}
791
792/* sm501_create_irq
793 *
794 * Fill in an IRQ resource for a sub device
795*/
796
797static void sm501_create_irq(struct sm501_devdata *sm,
798 struct resource *res)
799{
800 res->flags = IORESOURCE_IRQ;
801 res->parent = NULL;
802 res->start = res->end = sm->irq;
803}
804
805static int sm501_register_usbhost(struct sm501_devdata *sm,
806 resource_size_t *mem_avail)
807{
808 struct platform_device *pdev;
809
61711f8f 810 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
b6d6454f
BD		 811 if (!pdev)
812 return -ENOMEM;
813
814 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
815 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
816 sm501_create_irq(sm, &pdev->resource[2]);
817
818 return sm501_register_device(sm, pdev);
819}
820
61711f8f
MD		 821static void sm501_setup_uart_data(struct sm501_devdata *sm,
822 struct plat_serial8250_port *uart_data,
823 unsigned int offset)
824{
825 uart_data->membase = sm->regs + offset;
826 uart_data->mapbase = sm->io_res->start + offset;
827 uart_data->iotype = UPIO_MEM;
828 uart_data->irq = sm->irq;
829 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
830 uart_data->regshift = 2;
831 uart_data->uartclk = (9600 * 16);
832}
833
834static int sm501_register_uart(struct sm501_devdata *sm, int devices)
835{
836 struct platform_device *pdev;
837 struct plat_serial8250_port *uart_data;
838
839 pdev = sm501_create_subdev(sm, "serial8250", 0,
840 sizeof(struct plat_serial8250_port) * 3);
841 if (!pdev)
842 return -ENOMEM;
843
334a41ce 844 uart_data = dev_get_platdata(&pdev->dev);
61711f8f
MD		 845
846 if (devices & SM501_USE_UART0) {
847 sm501_setup_uart_data(sm, uart_data++, 0x30000);
848 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
849 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
850 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
851 }
852 if (devices & SM501_USE_UART1) {
853 sm501_setup_uart_data(sm, uart_data++, 0x30020);
854 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
855 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
856 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
857 }
858
859 pdev->id = PLAT8250_DEV_SM501;
860
861 return sm501_register_device(sm, pdev);
862}
863
b6d6454f
BD		 864static int sm501_register_display(struct sm501_devdata *sm,
865 resource_size_t *mem_avail)
866{
867 struct platform_device *pdev;
868
61711f8f 869 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
b6d6454f
BD		 870 if (!pdev)
871 return -ENOMEM;
872
873 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
874 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
875 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
876 sm501_create_irq(sm, &pdev->resource[3]);
877
878 return sm501_register_device(sm, pdev);
879}
880
f61be273
BD		 881#ifdef CONFIG_MFD_SM501_GPIO
882
f61be273
BD		 883static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
884{
885 return container_of(gpio, struct sm501_devdata, gpio);
886}
887
888static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
889
890{
3a504105 891 struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip);
f61be273
BD		 892 unsigned long result;
893
bf5f0019 894 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
f61be273
BD		 895 result >>= offset;
896
897 return result & 1UL;
898}
899
98325f8f
BD		 900static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
901 unsigned long bit)
902{
903 unsigned long ctrl;
904
905 /* check and modify if this pin is not set as gpio. */
906
bf5f0019 907 if (smc501_readl(smchip->control) & bit) {
98325f8f
BD		 908 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
909 "changing mode of gpio, bit %08lx\n", bit);
910
bf5f0019 911 ctrl = smc501_readl(smchip->control);
98325f8f 912 ctrl &= ~bit;
bf5f0019 913 smc501_writel(ctrl, smchip->control);
98325f8f
BD		 914
915 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
916 }
917}
918
f61be273
BD		 919static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
920
921{
3a504105 922 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
f61be273
BD		 923 struct sm501_gpio *smgpio = smchip->ourgpio;
924 unsigned long bit = 1 << offset;
925 void __iomem *regs = smchip->regbase;
926 unsigned long save;
927 unsigned long val;
928
929 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
930 __func__, chip, offset);
931
932 spin_lock_irqsave(&smgpio->lock, save);
933
bf5f0019 934 val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
f61be273
BD		 935 if (value)
936 val |= bit;
bf5f0019 937 smc501_writel(val, regs);
f61be273
BD		 938
939 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
98325f8f
BD		 940 sm501_gpio_ensure_gpio(smchip, bit);
941
f61be273
BD		 942 spin_unlock_irqrestore(&smgpio->lock, save);
943}
944
945static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
946{
3a504105 947 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
f61be273
BD		 948 struct sm501_gpio *smgpio = smchip->ourgpio;
949 void __iomem *regs = smchip->regbase;
950 unsigned long bit = 1 << offset;
951 unsigned long save;
952 unsigned long ddr;
953
98325f8f
BD		 954 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
955 __func__, chip, offset);
f61be273
BD		 956
957 spin_lock_irqsave(&smgpio->lock, save);
958
bf5f0019
HS		 959 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
960 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
f61be273
BD		 961
962 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
98325f8f
BD		 963 sm501_gpio_ensure_gpio(smchip, bit);
964
f61be273
BD		 965 spin_unlock_irqrestore(&smgpio->lock, save);
966
967 return 0;
968}
969
970static int sm501_gpio_output(struct gpio_chip *chip,
971 unsigned offset, int value)
972{
3a504105 973 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
f61be273
BD		 974 struct sm501_gpio *smgpio = smchip->ourgpio;
975 unsigned long bit = 1 << offset;
976 void __iomem *regs = smchip->regbase;
977 unsigned long save;
978 unsigned long val;
979 unsigned long ddr;
980
981 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
982 __func__, chip, offset, value);
983
984 spin_lock_irqsave(&smgpio->lock, save);
985
bf5f0019 986 val = smc501_readl(regs + SM501_GPIO_DATA_LOW);
f61be273
BD		 987 if (value)
988 val |= bit;
989 else
990 val &= ~bit;
bf5f0019 991 smc501_writel(val, regs);
f61be273 992
bf5f0019
HS		 993 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
994 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
f61be273
BD		 995
996 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
bf5f0019 997 smc501_writel(val, regs + SM501_GPIO_DATA_LOW);
f61be273
BD		 998
999 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1000 spin_unlock_irqrestore(&smgpio->lock, save);
1001
1002 return 0;
1003}
1004
7e94e515 1005static const struct gpio_chip gpio_chip_template = {
f61be273
BD		 1006 .ngpio = 32,
1007 .direction_input = sm501_gpio_input,
1008 .direction_output = sm501_gpio_output,
1009 .set = sm501_gpio_set,
1010 .get = sm501_gpio_get,
1011};
1012
f791be49 1013static int sm501_gpio_register_chip(struct sm501_devdata *sm,
f61be273
BD		 1014 struct sm501_gpio *gpio,
1015 struct sm501_gpio_chip *chip)
1016{
1017 struct sm501_platdata *pdata = sm->platdata;
1018 struct gpio_chip *gchip = &chip->gpio;
60e540d6 1019 int base = pdata->gpio_base;
f61be273 1020
28130bea 1021 chip->gpio = gpio_chip_template;
f61be273
BD		 1022
1023 if (chip == &gpio->high) {
60e540d6
AP		 1024 if (base > 0)
1025 base += 32;
f61be273 1026 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
98325f8f 1027 chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
f61be273
BD		 1028 gchip->label = "SM501-HIGH";
1029 } else {
1030 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
98325f8f 1031 chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
f61be273
BD		 1032 gchip->label = "SM501-LOW";
1033 }
1034
1035 gchip->base = base;
1036 chip->ourgpio = gpio;
1037
3a504105 1038 return gpiochip_add_data(gchip, chip);
f61be273
BD		 1039}
1040
f791be49 1041static int sm501_register_gpio(struct sm501_devdata *sm)
f61be273
BD		 1042{
1043 struct sm501_gpio *gpio = &sm->gpio;
1044 resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1045 int ret;
f61be273
BD		 1046
1047 dev_dbg(sm->dev, "registering gpio block %08llx\n",
1048 (unsigned long long)iobase);
1049
1050 spin_lock_init(&gpio->lock);
1051
1052 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1053 if (gpio->regs_res == NULL) {
1054 dev_err(sm->dev, "gpio: failed to request region\n");
1055 return -ENXIO;
1056 }
1057
1058 gpio->regs = ioremap(iobase, 0x20);
1059 if (gpio->regs == NULL) {
1060 dev_err(sm->dev, "gpio: failed to remap registers\n");
1061 ret = -ENXIO;
28130bea 1062 goto err_claimed;
f61be273
BD		 1063 }
1064
1065 /* Register both our chips. */
1066
1067 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1068 if (ret) {
1069 dev_err(sm->dev, "failed to add low chip\n");
1070 goto err_mapped;
1071 }
1072
1073 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1074 if (ret) {
1075 dev_err(sm->dev, "failed to add high chip\n");
1076 goto err_low_chip;
1077 }
1078
1079 gpio->registered = 1;
1080
1081 return 0;
1082
1083 err_low_chip:
88d5e520 1084 gpiochip_remove(&gpio->low.gpio);
f61be273
BD		 1085
1086 err_mapped:
28130bea
BD		 1087 iounmap(gpio->regs);
1088
1089 err_claimed:
f61be273
BD		 1090 release_resource(gpio->regs_res);
1091 kfree(gpio->regs_res);
1092
1093 return ret;
1094}
1095
1096static void sm501_gpio_remove(struct sm501_devdata *sm)
1097{
28130bea 1098 struct sm501_gpio *gpio = &sm->gpio;
f61be273 1099
f2999209
BD		 1100 if (!sm->gpio.registered)
1101 return;
1102
88d5e520 1103 gpiochip_remove(&gpio->low.gpio);
1104 gpiochip_remove(&gpio->high.gpio);
28130bea
BD		 1105
1106 iounmap(gpio->regs);
1107 release_resource(gpio->regs_res);
1108 kfree(gpio->regs_res);
f61be273
BD		 1109}
1110
f2999209
BD		 1111static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1112{
1113 return sm->gpio.registered;
1114}
f61be273 1115#else
28130bea 1116static inline int sm501_register_gpio(struct sm501_devdata *sm)
f61be273
BD		 1117{
1118 return 0;
1119}
1120
28130bea 1121static inline void sm501_gpio_remove(struct sm501_devdata *sm)
f61be273
BD		 1122{
1123}
42cd2366 1124
f2999209
BD		 1125static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1126{
1127 return 0;
1128}
f61be273
BD		 1129#endif
1130
42cd2366
BD		 1131static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1132 struct sm501_platdata_gpio_i2c *iic)
1133{
1134 struct i2c_gpio_platform_data *icd;
1135 struct platform_device *pdev;
b2e63555 1136 struct gpiod_lookup_table *lookup;
42cd2366
BD		 1137
1138 pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1139 sizeof(struct i2c_gpio_platform_data));
1140 if (!pdev)
1141 return -ENOMEM;
1142
b2e63555
LW		 1143 /* Create a gpiod lookup using gpiochip-local offsets */
1144 lookup = devm_kzalloc(&pdev->dev,
1145 sizeof(*lookup) + 3 * sizeof(struct gpiod_lookup),
1146 GFP_KERNEL);
1147 lookup->dev_id = "i2c-gpio";
1148 if (iic->pin_sda < 32)
1149 lookup->table[0].chip_label = "SM501-LOW";
1150 else
1151 lookup->table[0].chip_label = "SM501-HIGH";
1152 lookup->table[0].chip_hwnum = iic->pin_sda % 32;
1153 lookup->table[0].con_id = NULL;
1154 lookup->table[0].idx = 0;
4d0ce62c 1155 lookup->table[0].flags = GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN;
b2e63555
LW		 1156 if (iic->pin_scl < 32)
1157 lookup->table[1].chip_label = "SM501-LOW";
1158 else
1159 lookup->table[1].chip_label = "SM501-HIGH";
1160 lookup->table[1].chip_hwnum = iic->pin_scl % 32;
1161 lookup->table[1].con_id = NULL;
1162 lookup->table[1].idx = 1;
4d0ce62c 1163 lookup->table[1].flags = GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN;
b2e63555 1164 gpiod_add_lookup_table(lookup);
42cd2366 1165
b2e63555 1166 icd = dev_get_platdata(&pdev->dev);
42cd2366
BD		 1167 icd->timeout = iic->timeout;
1168 icd->udelay = iic->udelay;
1169
1170 /* note, we can't use either of the pin numbers, as the i2c-gpio
1171 * driver uses the platform.id field to generate the bus number
1172 * to register with the i2c core; The i2c core doesn't have enough
1173 * entries to deal with anything we currently use.
1174 */
1175
1176 pdev->id = iic->bus_num;
1177
b2e63555 1178 dev_info(sm->dev, "registering i2c-%d: sda=%d, scl=%d\n",
42cd2366 1179 iic->bus_num,
b2e63555 1180 iic->pin_sda, iic->pin_scl);
42cd2366
BD		 1181
1182 return sm501_register_device(sm, pdev);
1183}
1184
1185static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1186 struct sm501_platdata *pdata)
1187{
1188 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1189 int index;
1190 int ret;
1191
1192 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1193 ret = sm501_register_gpio_i2c_instance(sm, iic);
1194 if (ret < 0)
1195 return ret;
1196 }
1197
1198 return 0;
1199}
1200
b6d6454f
BD		 1201/* sm501_dbg_regs
1202 *
1203 * Debug attribute to attach to parent device to show core registers
1204*/
1205
1206static ssize_t sm501_dbg_regs(struct device *dev,
1207 struct device_attribute *attr, char *buff)
1208{
1209 struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1210 unsigned int reg;
1211 char *ptr = buff;
1212 int ret;
1213
1214 for (reg = 0x00; reg < 0x70; reg += 4) {
1215 ret = sprintf(ptr, "%08x = %08x\n",
bf5f0019 1216 reg, smc501_readl(sm->regs + reg));
b6d6454f
BD		 1217 ptr += ret;
1218 }
1219
1220 return ptr - buff;
1221}
1222
1223
8a8320c2 1224static DEVICE_ATTR(dbg_regs, 0444, sm501_dbg_regs, NULL);
b6d6454f
BD		 1225
1226/* sm501_init_reg
1227 *
1228 * Helper function for the init code to setup a register
5136237b
BD		 1229 *
1230 * clear the bits which are set in r->mask, and then set
1231 * the bits set in r->set.
b6d6454f
BD		 1232*/
1233
1234static inline void sm501_init_reg(struct sm501_devdata *sm,
1235 unsigned long reg,
1236 struct sm501_reg_init *r)
1237{
1238 unsigned long tmp;
1239
bf5f0019 1240 tmp = smc501_readl(sm->regs + reg);
b6d6454f 1241 tmp &= ~r->mask;
5136237b 1242 tmp |= r->set;
bf5f0019 1243 smc501_writel(tmp, sm->regs + reg);
b6d6454f
BD		 1244}
1245
1246/* sm501_init_regs
1247 *
1248 * Setup core register values
1249*/
1250
1251static void sm501_init_regs(struct sm501_devdata *sm,
1252 struct sm501_initdata *init)
1253{
1254 sm501_misc_control(sm->dev,
1255 init->misc_control.set,
1256 init->misc_control.mask);
1257
1258 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1259 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1260 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1261
b6d6454f
BD		 1262 if (init->m1xclk) {
1263 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1264 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1265 }
b5913bbd
BD		 1266
1267 if (init->mclk) {
1268 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1269 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1270 }
81906221
BD		 1271
1272}
1273
1274/* Check the PLL sources for the M1CLK and M1XCLK
1275 *
1276 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1277 * there is a risk (see errata AB-5) that the SM501 will cease proper
1278 * function. If this happens, then it is likely the SM501 will
1279 * hang the system.
1280*/
1281
1282static int sm501_check_clocks(struct sm501_devdata *sm)
1283{
bf5f0019 1284 unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
81906221
BD		 1285 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1286 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1287
1288 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
b6d6454f
BD		 1289}
1290
1291static unsigned int sm501_mem_local[] = {
1292 [0] = 4*1024*1024,
1293 [1] = 8*1024*1024,
1294 [2] = 16*1024*1024,
1295 [3] = 32*1024*1024,
1296 [4] = 64*1024*1024,
1297 [5] = 2*1024*1024,
1298};
1299
1300/* sm501_init_dev
1301 *
1302 * Common init code for an SM501
1303*/
1304
f791be49 1305static int sm501_init_dev(struct sm501_devdata *sm)
b6d6454f 1306{
61711f8f 1307 struct sm501_initdata *idata;
42cd2366 1308 struct sm501_platdata *pdata;
b6d6454f
BD		 1309 resource_size_t mem_avail;
1310 unsigned long dramctrl;
1e27dbe7 1311 unsigned long devid;
b6d6454f
BD		 1312 int ret;
1313
1314 mutex_init(&sm->clock_lock);
1315 spin_lock_init(&sm->reg_lock);
1316
1317 INIT_LIST_HEAD(&sm->devices);
1318
bf5f0019 1319 devid = smc501_readl(sm->regs + SM501_DEVICEID);
b6d6454f 1320
1e27dbe7
BD		 1321 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1322 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1323 return -EINVAL;
1324 }
1325
61711f8f 1326 /* disable irqs */
bf5f0019 1327 smc501_writel(0, sm->regs + SM501_IRQ_MASK);
61711f8f 1328
bf5f0019 1329 dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);
b6d6454f
BD		 1330 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1331
1e27dbe7
BD		 1332 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1333 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
b6d6454f 1334
3149be50
VS		 1335 sm->rev = devid & SM501_DEVICEID_REVMASK;
1336
331d7475 1337 sm501_dump_gate(sm);
b6d6454f
BD		 1338
1339 ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1340 if (ret)
1341 dev_err(sm->dev, "failed to create debug regs file\n");
1342
1343 sm501_dump_clk(sm);
1344
1345 /* check to see if we have some device initialisation */
1346
42cd2366
BD		 1347 pdata = sm->platdata;
1348 idata = pdata ? pdata->init : NULL;
1349
61711f8f
MD		 1350 if (idata) {
1351 sm501_init_regs(sm, idata);
b6d6454f 1352
61711f8f
MD		 1353 if (idata->devices & SM501_USE_USB_HOST)
1354 sm501_register_usbhost(sm, &mem_avail);
1355 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1356 sm501_register_uart(sm, idata->devices);
f61be273
BD		 1357 if (idata->devices & SM501_USE_GPIO)
1358 sm501_register_gpio(sm);
b6d6454f
BD		 1359 }
1360
4295f9bf 1361 if (pdata && pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) {
f2999209
BD		 1362 if (!sm501_gpio_isregistered(sm))
1363 dev_err(sm->dev, "no gpio available for i2c gpio.\n");
42cd2366
BD		 1364 else
1365 sm501_register_gpio_i2c(sm, pdata);
1366 }
1367
81906221
BD		 1368 ret = sm501_check_clocks(sm);
1369 if (ret) {
1370 dev_err(sm->dev, "M1X and M clocks sourced from different "
1371 "PLLs\n");
1372 return -EINVAL;
1373 }
1374
b6d6454f
BD		 1375 /* always create a framebuffer */
1376 sm501_register_display(sm, &mem_avail);
1377
1378 return 0;
1379}
1380
f791be49 1381static int sm501_plat_probe(struct platform_device *dev)
b6d6454f
BD		 1382{
1383 struct sm501_devdata *sm;
7cf5244c 1384 int ret;
b6d6454f
BD		 1385
1386 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1387 if (sm == NULL) {
1388 dev_err(&dev->dev, "no memory for device data\n");
7cf5244c 1389 ret = -ENOMEM;
b6d6454f
BD		 1390 goto err1;
1391 }
1392
1393 sm->dev = &dev->dev;
1394 sm->pdev_id = dev->id;
334a41ce 1395 sm->platdata = dev_get_platdata(&dev->dev);
b6d6454f 1396
7cf5244c
RK		 1397 ret = platform_get_irq(dev, 0);
1398 if (ret < 0) {
b6d6454f 1399 dev_err(&dev->dev, "failed to get irq resource\n");
b6d6454f
BD		 1400 goto err_res;
1401 }
7cf5244c 1402 sm->irq = ret;
b6d6454f 1403
7cf5244c
RK		 1404 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1405 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
4295f9bf 1406
b6d6454f
BD		 1407 if (sm->io_res == NULL || sm->mem_res == NULL) {
1408 dev_err(&dev->dev, "failed to get IO resource\n");
7cf5244c 1409 ret = -ENOENT;
b6d6454f
BD		 1410 goto err_res;
1411 }
1412
1413 sm->regs_claim = request_mem_region(sm->io_res->start,
a5300dcb 1414 0x100, "sm501");
b6d6454f
BD		 1415
1416 if (sm->regs_claim == NULL) {
1417 dev_err(&dev->dev, "cannot claim registers\n");
7cf5244c 1418 ret = -EBUSY;
b6d6454f
BD		 1419 goto err_res;
1420 }
1421
1422 platform_set_drvdata(dev, sm);
1423
311e54c0 1424 sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
b6d6454f
BD		 1425
1426 if (sm->regs == NULL) {
1427 dev_err(&dev->dev, "cannot remap registers\n");
7cf5244c 1428 ret = -EIO;
b6d6454f
BD		 1429 goto err_claim;
1430 }
1431
1432 return sm501_init_dev(sm);
1433
1434 err_claim:
1435 release_resource(sm->regs_claim);
1436 kfree(sm->regs_claim);
1437 err_res:
1438 kfree(sm);
1439 err1:
7cf5244c 1440 return ret;
b6d6454f
BD		 1441
1442}
1443
331d7475 1444#ifdef CONFIG_PM
472dba7d 1445
331d7475
BD		 1446/* power management support */
1447
472dba7d
BD		 1448static void sm501_set_power(struct sm501_devdata *sm, int on)
1449{
1450 struct sm501_platdata *pd = sm->platdata;
1451
1452 if (pd == NULL)
1453 return;
1454
1455 if (pd->get_power) {
1456 if (pd->get_power(sm->dev) == on) {
1457 dev_dbg(sm->dev, "is already %d\n", on);
1458 return;
1459 }
1460 }
1461
1462 if (pd->set_power) {
1463 dev_dbg(sm->dev, "setting power to %d\n", on);
1464
1465 pd->set_power(sm->dev, on);
1466 sm501_mdelay(sm, 10);
1467 }
1468}
1469
331d7475
BD		 1470static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1471{
1472 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1473
1474 sm->in_suspend = 1;
bf5f0019 1475 sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
331d7475
BD		 1476
1477 sm501_dump_regs(sm);
472dba7d
BD		 1478
1479 if (sm->platdata) {
1480 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1481 sm501_set_power(sm, 0);
1482 }
1483
331d7475
BD		 1484 return 0;
1485}
1486
1487static int sm501_plat_resume(struct platform_device *pdev)
1488{
1489 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1490
472dba7d
BD		 1491 sm501_set_power(sm, 1);
1492
331d7475
BD		 1493 sm501_dump_regs(sm);
1494 sm501_dump_gate(sm);
1495 sm501_dump_clk(sm);
1496
1497 /* check to see if we are in the same state as when suspended */
1498
bf5f0019 1499 if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
331d7475 1500 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
bf5f0019 1501 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
331d7475
BD		 1502
1503 /* our suspend causes the controller state to change,
1504 * either by something attempting setup, power loss,
1505 * or an external reset event on power change */
1506
1507 if (sm->platdata && sm->platdata->init) {
1508 sm501_init_regs(sm, sm->platdata->init);
1509 }
1510 }
1511
1512 /* dump our state from resume */
1513
1514 sm501_dump_regs(sm);
1515 sm501_dump_clk(sm);
1516
1517 sm->in_suspend = 0;
1518
1519 return 0;
1520}
1521#else
1522#define sm501_plat_suspend NULL
1523#define sm501_plat_resume NULL
1524#endif
1525
b6d6454f
BD		 1526/* Initialisation data for PCI devices */
1527
1528static struct sm501_initdata sm501_pci_initdata = {
1529 .gpio_high = {
1530 .set = 0x3F000000, /* 24bit panel */
1531 .mask = 0x0,
1532 },
1533 .misc_timing = {
1534 .set = 0x010100, /* SDRAM timing */
1535 .mask = 0x1F1F00,
1536 },
1537 .misc_control = {
1538 .set = SM501_MISC_PNL_24BIT,
1539 .mask = 0,
1540 },
1541
1542 .devices = SM501_USE_ALL,
81906221
BD		 1543
1544 /* Errata AB-3 says that 72MHz is the fastest available
1545 * for 33MHZ PCI with proper bus-mastering operation */
1546
1547 .mclk = 72 * MHZ,
1548 .m1xclk = 144 * MHZ,
b6d6454f
BD		 1549};
1550
1551static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1552 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1553 SM501FB_FLAG_USE_HWCURSOR |
1554 SM501FB_FLAG_USE_HWACCEL |
1555 SM501FB_FLAG_DISABLE_AT_EXIT),
1556};
1557
1558static struct sm501_platdata_fb sm501_fb_pdata = {
1559 .fb_route = SM501_FB_OWN,
1560 .fb_crt = &sm501_pdata_fbsub,
1561 .fb_pnl = &sm501_pdata_fbsub,
1562};
1563
1564static struct sm501_platdata sm501_pci_platdata = {
1565 .init = &sm501_pci_initdata,
1566 .fb = &sm501_fb_pdata,
60e540d6 1567 .gpio_base = -1,
b6d6454f
BD		 1568};
1569
f791be49 1570static int sm501_pci_probe(struct pci_dev *dev,
158abca5 1571 const struct pci_device_id *id)
b6d6454f
BD		 1572{
1573 struct sm501_devdata *sm;
1574 int err;
1575
1576 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1577 if (sm == NULL) {
1578 dev_err(&dev->dev, "no memory for device data\n");
1579 err = -ENOMEM;
1580 goto err1;
1581 }
1582
1583 /* set a default set of platform data */
1584 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1585
1586 /* set a hopefully unique id for our child platform devices */
1587 sm->pdev_id = 32 + dev->devfn;
1588
1589 pci_set_drvdata(dev, sm);
1590
1591 err = pci_enable_device(dev);
1592 if (err) {
1593 dev_err(&dev->dev, "cannot enable device\n");
1594 goto err2;
1595 }
1596
1597 sm->dev = &dev->dev;
1598 sm->irq = dev->irq;
1599
1600#ifdef __BIG_ENDIAN
1601 /* if the system is big-endian, we most probably have a
1602 * translation in the IO layer making the PCI bus little endian
1603 * so make the framebuffer swapped pixels */
1604
1605 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1606#endif
1607
1608 /* check our resources */
1609
1610 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1611 dev_err(&dev->dev, "region #0 is not memory?\n");
1612 err = -EINVAL;
1613 goto err3;
1614 }
1615
1616 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1617 dev_err(&dev->dev, "region #1 is not memory?\n");
1618 err = -EINVAL;
1619 goto err3;
1620 }
1621
1622 /* make our resources ready for sharing */
1623
1624 sm->io_res = &dev->resource[1];
1625 sm->mem_res = &dev->resource[0];
1626
1627 sm->regs_claim = request_mem_region(sm->io_res->start,
a5300dcb 1628 0x100, "sm501");
b6d6454f
BD		 1629 if (sm->regs_claim == NULL) {
1630 dev_err(&dev->dev, "cannot claim registers\n");
1631 err= -EBUSY;
1632 goto err3;
1633 }
1634
7ab18995 1635 sm->regs = pci_ioremap_bar(dev, 1);
b6d6454f
BD		 1636
1637 if (sm->regs == NULL) {
1638 dev_err(&dev->dev, "cannot remap registers\n");
1639 err = -EIO;
1640 goto err4;
1641 }
1642
1643 sm501_init_dev(sm);
1644 return 0;
1645
1646 err4:
1647 release_resource(sm->regs_claim);
1648 kfree(sm->regs_claim);
1649 err3:
1650 pci_disable_device(dev);
1651 err2:
b6d6454f
BD		 1652 kfree(sm);
1653 err1:
1654 return err;
1655}
1656
1657static void sm501_remove_sub(struct sm501_devdata *sm,
1658 struct sm501_device *smdev)
1659{
1660 list_del(&smdev->list);
1661 platform_device_unregister(&smdev->pdev);
1662}
1663
1664static void sm501_dev_remove(struct sm501_devdata *sm)
1665{
1666 struct sm501_device *smdev, *tmp;
1667
1668 list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1669 sm501_remove_sub(sm, smdev);
1670
1671 device_remove_file(sm->dev, &dev_attr_dbg_regs);
f61be273 1672
f2999209 1673 sm501_gpio_remove(sm);
b6d6454f
BD		 1674}
1675
4740f73f 1676static void sm501_pci_remove(struct pci_dev *dev)
b6d6454f
BD		 1677{
1678 struct sm501_devdata *sm = pci_get_drvdata(dev);
1679
1680 sm501_dev_remove(sm);
1681 iounmap(sm->regs);
1682
1683 release_resource(sm->regs_claim);
1684 kfree(sm->regs_claim);
1685
b6d6454f
BD		 1686 pci_disable_device(dev);
1687}
1688
1689static int sm501_plat_remove(struct platform_device *dev)
1690{
1691 struct sm501_devdata *sm = platform_get_drvdata(dev);
1692
1693 sm501_dev_remove(sm);
1694 iounmap(sm->regs);
1695
1696 release_resource(sm->regs_claim);
1697 kfree(sm->regs_claim);
1698
1699 return 0;
1700}
1701
36fcd06c 1702static const struct pci_device_id sm501_pci_tbl[] = {
b6d6454f
BD		 1703 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1704 { 0, },
1705};
1706
1707MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1708
158abca5 1709static struct pci_driver sm501_pci_driver = {
b6d6454f
BD		 1710 .name = "sm501",
1711 .id_table = sm501_pci_tbl,
1712 .probe = sm501_pci_probe,
84449216 1713 .remove = sm501_pci_remove,
b6d6454f
BD		 1714};
1715
4f46d6e7
KS		 1716MODULE_ALIAS("platform:sm501");
1717
ae6eee3c 1718static const struct of_device_id of_sm501_match_tbl[] = {
4295f9bf
HS		 1719 { .compatible = "smi,sm501", },
1720 { /* end */ }
1721};
327cc18e 1722MODULE_DEVICE_TABLE(of, of_sm501_match_tbl);
4295f9bf 1723
158abca5 1724static struct platform_driver sm501_plat_driver = {
b6d6454f
BD		 1725 .driver = {
1726 .name = "sm501",
4295f9bf 1727 .of_match_table = of_sm501_match_tbl,
b6d6454f
BD		 1728 },
1729 .probe = sm501_plat_probe,
1730 .remove = sm501_plat_remove,
331d7475
BD		 1731 .suspend = sm501_plat_suspend,
1732 .resume = sm501_plat_resume,
b6d6454f
BD		 1733};
1734
1735static int __init sm501_base_init(void)
1736{
158abca5
AD		 1737 platform_driver_register(&sm501_plat_driver);
1738 return pci_register_driver(&sm501_pci_driver);
b6d6454f
BD		 1739}
1740
1741static void __exit sm501_base_exit(void)
1742{
158abca5
AD		 1743 platform_driver_unregister(&sm501_plat_driver);
1744 pci_unregister_driver(&sm501_pci_driver);
b6d6454f
BD		 1745}
1746
1747module_init(sm501_base_init);
1748module_exit(sm501_base_exit);
1749
1750MODULE_DESCRIPTION("SM501 Core Driver");
1751MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1752MODULE_LICENSE("GPL v2");
ubuntu-bionic-kernel mirror