[mirror_ubuntu-jammy-kernel.git] / drivers / mfd / ssbi.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
 * Copyright (c) 2010, Google Inc.
 *
 * Original authors: Code Aurora Forum
 *
 * Author: Dima Zavin <dima@android.com>
 *  - Largely rewritten from original to not be an i2c driver.
 */

#define pr_fmt(fmt) "%s: " fmt, __func__

#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/ssbi.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>

/* SSBI 2.0 controller registers */
#define SSBI2_CMD			0x0008
#define SSBI2_RD			0x0010
#define SSBI2_STATUS			0x0014
#define SSBI2_MODE2			0x001C

/* SSBI_CMD fields */
#define SSBI_CMD_RDWRN			(1 << 24)

/* SSBI_STATUS fields */
#define SSBI_STATUS_RD_READY		(1 << 2)
#define SSBI_STATUS_READY		(1 << 1)
#define SSBI_STATUS_MCHN_BUSY		(1 << 0)

/* SSBI_MODE2 fields */
#define SSBI_MODE2_REG_ADDR_15_8_SHFT	0x04
#define SSBI_MODE2_REG_ADDR_15_8_MASK	(0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT)

#define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \
	(((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \
	SSBI_MODE2_REG_ADDR_15_8_MASK))

/* SSBI PMIC Arbiter command registers */
#define SSBI_PA_CMD			0x0000
#define SSBI_PA_RD_STATUS		0x0004

/* SSBI_PA_CMD fields */
#define SSBI_PA_CMD_RDWRN		(1 << 24)
#define SSBI_PA_CMD_ADDR_MASK		0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/

/* SSBI_PA_RD_STATUS fields */
#define SSBI_PA_RD_STATUS_TRANS_DONE	(1 << 27)
#define SSBI_PA_RD_STATUS_TRANS_DENIED	(1 << 26)

#define SSBI_TIMEOUT_US			100

enum ssbi_controller_type {
	MSM_SBI_CTRL_SSBI = 0,
	MSM_SBI_CTRL_SSBI2,
	MSM_SBI_CTRL_PMIC_ARBITER,
};

struct ssbi {
	struct device		*slave;
	void __iomem		*base;
	spinlock_t		lock;
	enum ssbi_controller_type controller_type;
	int (*read)(struct ssbi *, u16 addr, u8 *buf, int len);
	int (*write)(struct ssbi *, u16 addr, const u8 *buf, int len);
};

static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg)
{
	return readl(ssbi->base + reg);
}

static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg)
{
	writel(val, ssbi->base + reg);
}

/*
 * Via private exchange with one of the original authors, the hardware
 * should generally finish a transaction in about 5us.  The worst
 * case, is when using the arbiter and both other CPUs have just
 * started trying to use the SSBI bus will result in a time of about
 * 20us.  It should never take longer than this.
 *
 * As such, this wait merely spins, with a udelay.
 */
static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask)
{
	u32 timeout = SSBI_TIMEOUT_US;
	u32 val;

	while (timeout--) {
		val = ssbi_readl(ssbi, SSBI2_STATUS);
		if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0))
			return 0;
		udelay(1);
	}

	return -ETIMEDOUT;
}

static int
ssbi_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
{
	u32 cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16);
	int ret = 0;

	if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
		u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
		mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
		ssbi_writel(ssbi, mode2, SSBI2_MODE2);
	}

	while (len) {
		ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
		if (ret)
			goto err;

		ssbi_writel(ssbi, cmd, SSBI2_CMD);
		ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0);
		if (ret)
			goto err;
		*buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff;
		len--;
	}

err:
	return ret;
}

static int
ssbi_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
{
	int ret = 0;

	if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
		u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
		mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
		ssbi_writel(ssbi, mode2, SSBI2_MODE2);
	}

	while (len) {
		ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
		if (ret)
			goto err;

		ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD);
		ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY);
		if (ret)
			goto err;
		buf++;
		len--;
	}

err:
	return ret;
}

/*
 * See ssbi_wait_mask for an explanation of the time and the
 * busywait.
 */
static inline int
ssbi_pa_transfer(struct ssbi *ssbi, u32 cmd, u8 *data)
{
	u32 timeout = SSBI_TIMEOUT_US;
	u32 rd_status = 0;

	ssbi_writel(ssbi, cmd, SSBI_PA_CMD);

	while (timeout--) {
		rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS);

		if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED)
			return -EPERM;

		if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) {
			if (data)
				*data = rd_status & 0xff;
			return 0;
		}
		udelay(1);
	}

	return -ETIMEDOUT;
}

static int
ssbi_pa_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
{
	u32 cmd;
	int ret = 0;

	cmd = SSBI_PA_CMD_RDWRN | (addr & SSBI_PA_CMD_ADDR_MASK) << 8;

	while (len) {
		ret = ssbi_pa_transfer(ssbi, cmd, buf);
		if (ret)
			goto err;
		buf++;
		len--;
	}

err:
	return ret;
}

static int
ssbi_pa_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
{
	u32 cmd;
	int ret = 0;

	while (len) {
		cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 | *buf;
		ret = ssbi_pa_transfer(ssbi, cmd, NULL);
		if (ret)
			goto err;
		buf++;
		len--;
	}

err:
	return ret;
}

int ssbi_read(struct device *dev, u16 addr, u8 *buf, int len)
{
	struct ssbi *ssbi = dev_get_drvdata(dev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&ssbi->lock, flags);
	ret = ssbi->read(ssbi, addr, buf, len);
	spin_unlock_irqrestore(&ssbi->lock, flags);

	return ret;
}
EXPORT_SYMBOL_GPL(ssbi_read);

int ssbi_write(struct device *dev, u16 addr, const u8 *buf, int len)
{
	struct ssbi *ssbi = dev_get_drvdata(dev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&ssbi->lock, flags);
	ret = ssbi->write(ssbi, addr, buf, len);
	spin_unlock_irqrestore(&ssbi->lock, flags);

	return ret;
}
EXPORT_SYMBOL_GPL(ssbi_write);

static int ssbi_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct resource *mem_res;
	struct ssbi *ssbi;
	const char *type;

	ssbi = devm_kzalloc(&pdev->dev, sizeof(*ssbi), GFP_KERNEL);
	if (!ssbi)
		return -ENOMEM;

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ssbi->base = devm_ioremap_resource(&pdev->dev, mem_res);
	if (IS_ERR(ssbi->base))
		return PTR_ERR(ssbi->base);

	platform_set_drvdata(pdev, ssbi);

	type = of_get_property(np, "qcom,controller-type", NULL);
	if (type == NULL) {
		dev_err(&pdev->dev, "Missing qcom,controller-type property\n");
		return -EINVAL;
	}
	dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type);
	if (strcmp(type, "ssbi") == 0)
		ssbi->controller_type = MSM_SBI_CTRL_SSBI;
	else if (strcmp(type, "ssbi2") == 0)
		ssbi->controller_type = MSM_SBI_CTRL_SSBI2;
	else if (strcmp(type, "pmic-arbiter") == 0)
		ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER;
	else {
		dev_err(&pdev->dev, "Unknown qcom,controller-type\n");
		return -EINVAL;
	}

	if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) {
		ssbi->read = ssbi_pa_read_bytes;
		ssbi->write = ssbi_pa_write_bytes;
	} else {
		ssbi->read = ssbi_read_bytes;
		ssbi->write = ssbi_write_bytes;
	}

	spin_lock_init(&ssbi->lock);

	return devm_of_platform_populate(&pdev->dev);
}

static const struct of_device_id ssbi_match_table[] = {
	{ .compatible = "qcom,ssbi" },
	{}
};
MODULE_DEVICE_TABLE(of, ssbi_match_table);

static struct platform_driver ssbi_driver = {
	.probe		= ssbi_probe,
	.driver		= {
		.name	= "ssbi",
		.of_match_table = ssbi_match_table,
	},
};
module_platform_driver(ssbi_driver);

MODULE_LICENSE("GPL v2");
MODULE_VERSION("1.0");
MODULE_ALIAS("platform:ssbi");
MODULE_AUTHOR("Dima Zavin <dima@android.com>");
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
ce44bf5b	2	/* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
e44b0cee KH	3	* Copyright (c) 2010, Google Inc.
	4	*
	5	* Original authors: Code Aurora Forum
	6	*
	7	* Author: Dima Zavin <dima@android.com>
	8	* - Largely rewritten from original to not be an i2c driver.
e44b0cee KH	9	*/
	10
	11	#define pr_fmt(fmt) "%s: " fmt, __func__
	12
	13	#include <linux/delay.h>
	14	#include <linux/err.h>
	15	#include <linux/io.h>
	16	#include <linux/kernel.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/slab.h>
ce44bf5b	19	#include <linux/ssbi.h>
e44b0cee	20	#include <linux/module.h>
97f00f71 DB	21	#include <linux/of.h>
97f00f71 DB	22	#include <linux/of_device.h>
e44b0cee KH	23
	24	/* SSBI 2.0 controller registers */
	25	#define SSBI2_CMD 0x0008
	26	#define SSBI2_RD 0x0010
	27	#define SSBI2_STATUS 0x0014
	28	#define SSBI2_MODE2 0x001C
	29
	30	/* SSBI_CMD fields */
	31	#define SSBI_CMD_RDWRN (1 << 24)
	32
	33	/* SSBI_STATUS fields */
	34	#define SSBI_STATUS_RD_READY (1 << 2)
	35	#define SSBI_STATUS_READY (1 << 1)
	36	#define SSBI_STATUS_MCHN_BUSY (1 << 0)
	37
	38	/* SSBI_MODE2 fields */
	39	#define SSBI_MODE2_REG_ADDR_15_8_SHFT 0x04
	40	#define SSBI_MODE2_REG_ADDR_15_8_MASK (0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT)
	41
	42	#define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \
	43	(((MD) & 0x0F) \| ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \
	44	SSBI_MODE2_REG_ADDR_15_8_MASK))
	45
	46	/* SSBI PMIC Arbiter command registers */
	47	#define SSBI_PA_CMD 0x0000
	48	#define SSBI_PA_RD_STATUS 0x0004
	49
	50	/* SSBI_PA_CMD fields */
	51	#define SSBI_PA_CMD_RDWRN (1 << 24)
	52	#define SSBI_PA_CMD_ADDR_MASK 0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/
	53
	54	/* SSBI_PA_RD_STATUS fields */
	55	#define SSBI_PA_RD_STATUS_TRANS_DONE (1 << 27)
	56	#define SSBI_PA_RD_STATUS_TRANS_DENIED (1 << 26)
	57
	58	#define SSBI_TIMEOUT_US 100
	59
bae911a0 SB	60	enum ssbi_controller_type {
	61	MSM_SBI_CTRL_SSBI = 0,
	62	MSM_SBI_CTRL_SSBI2,
	63	MSM_SBI_CTRL_PMIC_ARBITER,
	64	};
	65
ce44bf5b	66	struct ssbi {
e44b0cee KH	67	struct device *slave;
	68	void __iomem *base;
	69	spinlock_t lock;
ce44bf5b DB	70	enum ssbi_controller_type controller_type;
ce44bf5b DB	71	int (read)(struct ssbi , u16 addr, u8 *buf, int len);
5eec14cc	72	int (write)(struct ssbi , u16 addr, const u8 *buf, int len);
e44b0cee KH	73	};
e44b0cee KH	74
ce44bf5b	75	static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg)
e44b0cee KH	76	{
	77	return readl(ssbi->base + reg);
	78	}
	79
ce44bf5b	80	static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg)
e44b0cee KH	81	{
	82	writel(val, ssbi->base + reg);
	83	}
	84
3f7a73b5 DB	85	/*
	86	* Via private exchange with one of the original authors, the hardware
	87	* should generally finish a transaction in about 5us. The worst
	88	* case, is when using the arbiter and both other CPUs have just
	89	* started trying to use the SSBI bus will result in a time of about
	90	* 20us. It should never take longer than this.
	91	*
	92	* As such, this wait merely spins, with a udelay.
	93	*/
ce44bf5b	94	static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask)
e44b0cee KH	95	{
	96	u32 timeout = SSBI_TIMEOUT_US;
	97	u32 val;
	98
	99	while (timeout--) {
	100	val = ssbi_readl(ssbi, SSBI2_STATUS);
	101	if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0))
	102	return 0;
	103	udelay(1);
	104	}
	105
e44b0cee KH	106	return -ETIMEDOUT;
	107	}
	108
	109	static int
ce44bf5b	110	ssbi_read_bytes(struct ssbi ssbi, u16 addr, u8 buf, int len)
e44b0cee KH	111	{
	112	u32 cmd = SSBI_CMD_RDWRN \| ((addr & 0xff) << 16);
	113	int ret = 0;
	114
	115	if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
	116	u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
	117	mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
	118	ssbi_writel(ssbi, mode2, SSBI2_MODE2);
	119	}
	120
	121	while (len) {
	122	ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
	123	if (ret)
	124	goto err;
	125
	126	ssbi_writel(ssbi, cmd, SSBI2_CMD);
	127	ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0);
	128	if (ret)
	129	goto err;
	130	*buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff;
	131	len--;
	132	}
	133
	134	err:
	135	return ret;
	136	}
	137
	138	static int
5eec14cc	139	ssbi_write_bytes(struct ssbi ssbi, u16 addr, const u8 buf, int len)
e44b0cee KH	140	{
	141	int ret = 0;
	142
	143	if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
	144	u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
	145	mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
	146	ssbi_writel(ssbi, mode2, SSBI2_MODE2);
	147	}
	148
	149	while (len) {
	150	ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
	151	if (ret)
	152	goto err;
	153
	154	ssbi_writel(ssbi, ((addr & 0xff) << 16) \| *buf, SSBI2_CMD);
	155	ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY);
	156	if (ret)
	157	goto err;
	158	buf++;
	159	len--;
	160	}
	161
	162	err:
	163	return ret;
	164	}
	165
3f7a73b5 DB	166	/*
	167	* See ssbi_wait_mask for an explanation of the time and the
	168	* busywait.
	169	*/
e44b0cee	170	static inline int
ce44bf5b	171	ssbi_pa_transfer(struct ssbi ssbi, u32 cmd, u8 data)
e44b0cee KH	172	{
	173	u32 timeout = SSBI_TIMEOUT_US;
	174	u32 rd_status = 0;
	175
	176	ssbi_writel(ssbi, cmd, SSBI_PA_CMD);
	177
	178	while (timeout--) {
	179	rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS);
	180
37799ef4	181	if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED)
e44b0cee	182	return -EPERM;
e44b0cee KH	183
	184	if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) {
	185	if (data)
	186	*data = rd_status & 0xff;
	187	return 0;
	188	}
	189	udelay(1);
	190	}
	191
e44b0cee KH	192	return -ETIMEDOUT;
	193	}
	194
	195	static int
ce44bf5b	196	ssbi_pa_read_bytes(struct ssbi ssbi, u16 addr, u8 buf, int len)
e44b0cee KH	197	{
	198	u32 cmd;
	199	int ret = 0;
	200
	201	cmd = SSBI_PA_CMD_RDWRN \| (addr & SSBI_PA_CMD_ADDR_MASK) << 8;
	202
	203	while (len) {
ce44bf5b	204	ret = ssbi_pa_transfer(ssbi, cmd, buf);
e44b0cee KH	205	if (ret)
	206	goto err;
	207	buf++;
	208	len--;
	209	}
	210
	211	err:
	212	return ret;
	213	}
	214
	215	static int
5eec14cc	216	ssbi_pa_write_bytes(struct ssbi ssbi, u16 addr, const u8 buf, int len)
e44b0cee KH	217	{
	218	u32 cmd;
	219	int ret = 0;
	220
	221	while (len) {
	222	cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 \| *buf;
ce44bf5b	223	ret = ssbi_pa_transfer(ssbi, cmd, NULL);
e44b0cee KH	224	if (ret)
	225	goto err;
	226	buf++;
	227	len--;
	228	}
	229
	230	err:
	231	return ret;
	232	}
	233
ce44bf5b	234	int ssbi_read(struct device dev, u16 addr, u8 buf, int len)
e44b0cee	235	{
ed835136	236	struct ssbi *ssbi = dev_get_drvdata(dev);
e44b0cee KH	237	unsigned long flags;
	238	int ret;
	239
e44b0cee KH	240	spin_lock_irqsave(&ssbi->lock, flags);
	241	ret = ssbi->read(ssbi, addr, buf, len);
	242	spin_unlock_irqrestore(&ssbi->lock, flags);
	243
	244	return ret;
	245	}
ce44bf5b	246	EXPORT_SYMBOL_GPL(ssbi_read);
e44b0cee	247
5eec14cc	248	int ssbi_write(struct device dev, u16 addr, const u8 buf, int len)
e44b0cee	249	{
ed835136	250	struct ssbi *ssbi = dev_get_drvdata(dev);
e44b0cee KH	251	unsigned long flags;
	252	int ret;
	253
e44b0cee KH	254	spin_lock_irqsave(&ssbi->lock, flags);
	255	ret = ssbi->write(ssbi, addr, buf, len);
	256	spin_unlock_irqrestore(&ssbi->lock, flags);
	257
	258	return ret;
	259	}
ce44bf5b	260	EXPORT_SYMBOL_GPL(ssbi_write);
e44b0cee	261
ce44bf5b	262	static int ssbi_probe(struct platform_device *pdev)
e44b0cee	263	{
97f00f71	264	struct device_node *np = pdev->dev.of_node;
e44b0cee	265	struct resource *mem_res;
ce44bf5b	266	struct ssbi *ssbi;
97f00f71	267	const char *type;
e44b0cee	268
e5784388 SB	269	ssbi = devm_kzalloc(&pdev->dev, sizeof(*ssbi), GFP_KERNEL);
e5784388 SB	270	if (!ssbi)
e44b0cee	271	return -ENOMEM;
e44b0cee KH	272
e44b0cee KH	273	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
e5784388 SB	274	ssbi->base = devm_ioremap_resource(&pdev->dev, mem_res);
	275	if (IS_ERR(ssbi->base))
	276	return PTR_ERR(ssbi->base);
e44b0cee	277
e44b0cee KH	278	platform_set_drvdata(pdev, ssbi);
e44b0cee KH	279
97f00f71 DB	280	type = of_get_property(np, "qcom,controller-type", NULL);
97f00f71 DB	281	if (type == NULL) {
e5784388 SB	282	dev_err(&pdev->dev, "Missing qcom,controller-type property\n");
e5784388 SB	283	return -EINVAL;
97f00f71 DB	284	}
	285	dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type);
	286	if (strcmp(type, "ssbi") == 0)
	287	ssbi->controller_type = MSM_SBI_CTRL_SSBI;
	288	else if (strcmp(type, "ssbi2") == 0)
	289	ssbi->controller_type = MSM_SBI_CTRL_SSBI2;
	290	else if (strcmp(type, "pmic-arbiter") == 0)
	291	ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER;
	292	else {
e5784388 SB	293	dev_err(&pdev->dev, "Unknown qcom,controller-type\n");
e5784388 SB	294	return -EINVAL;
97f00f71 DB	295	}
97f00f71 DB	296
e44b0cee	297	if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) {
ce44bf5b DB	298	ssbi->read = ssbi_pa_read_bytes;
ce44bf5b DB	299	ssbi->write = ssbi_pa_write_bytes;
e44b0cee	300	} else {
ce44bf5b DB	301	ssbi->read = ssbi_read_bytes;
ce44bf5b DB	302	ssbi->write = ssbi_write_bytes;
e44b0cee KH	303	}
	304
	305	spin_lock_init(&ssbi->lock);
	306
f38aa351	307	return devm_of_platform_populate(&pdev->dev);
e44b0cee KH	308	}
e44b0cee KH	309
12eda2a2	310	static const struct of_device_id ssbi_match_table[] = {
97f00f71 DB	311	{ .compatible = "qcom,ssbi" },
	312	{}
	313	};
6378c1e5	314	MODULE_DEVICE_TABLE(of, ssbi_match_table);
97f00f71	315
ce44bf5b DB	316	static struct platform_driver ssbi_driver = {
ce44bf5b DB	317	.probe = ssbi_probe,
e44b0cee	318	.driver = {
ce44bf5b	319	.name = "ssbi",
97f00f71	320	.of_match_table = ssbi_match_table,
e44b0cee KH	321	},
e44b0cee KH	322	};
e5784388	323	module_platform_driver(ssbi_driver);
e44b0cee KH	324
	325	MODULE_LICENSE("GPL v2");
	326	MODULE_VERSION("1.0");
ce44bf5b	327	MODULE_ALIAS("platform:ssbi");
e44b0cee	328	MODULE_AUTHOR("Dima Zavin <dima@android.com>");