[mirror_ubuntu-jammy-kernel.git] / drivers / mfd / ssbi.c

/* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
 * Copyright (c) 2010, Google Inc.
 *
 * Original authors: Code Aurora Forum
 *
 * Author: Dima Zavin <dima@android.com>
 *  - Largely rewritten from original to not be an i2c driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#define pr_fmt(fmt) "%s: " fmt, __func__

#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/ssbi.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>

/* SSBI 2.0 controller registers */
#define SSBI2_CMD			0x0008
#define SSBI2_RD			0x0010
#define SSBI2_STATUS			0x0014
#define SSBI2_MODE2			0x001C

/* SSBI_CMD fields */
#define SSBI_CMD_RDWRN			(1 << 24)

/* SSBI_STATUS fields */
#define SSBI_STATUS_RD_READY		(1 << 2)
#define SSBI_STATUS_READY		(1 << 1)
#define SSBI_STATUS_MCHN_BUSY		(1 << 0)

/* SSBI_MODE2 fields */
#define SSBI_MODE2_REG_ADDR_15_8_SHFT	0x04
#define SSBI_MODE2_REG_ADDR_15_8_MASK	(0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT)

#define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \
	(((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \
	SSBI_MODE2_REG_ADDR_15_8_MASK))

/* SSBI PMIC Arbiter command registers */
#define SSBI_PA_CMD			0x0000
#define SSBI_PA_RD_STATUS		0x0004

/* SSBI_PA_CMD fields */
#define SSBI_PA_CMD_RDWRN		(1 << 24)
#define SSBI_PA_CMD_ADDR_MASK		0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/

/* SSBI_PA_RD_STATUS fields */
#define SSBI_PA_RD_STATUS_TRANS_DONE	(1 << 27)
#define SSBI_PA_RD_STATUS_TRANS_DENIED	(1 << 26)

#define SSBI_TIMEOUT_US			100

enum ssbi_controller_type {
	MSM_SBI_CTRL_SSBI = 0,
	MSM_SBI_CTRL_SSBI2,
	MSM_SBI_CTRL_PMIC_ARBITER,
};

struct ssbi {
	struct device		*slave;
	void __iomem		*base;
	spinlock_t		lock;
	enum ssbi_controller_type controller_type;
	int (*read)(struct ssbi *, u16 addr, u8 *buf, int len);
	int (*write)(struct ssbi *, u16 addr, const u8 *buf, int len);
};

static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg)
{
	return readl(ssbi->base + reg);
}

static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg)
{
	writel(val, ssbi->base + reg);
}

/*
 * Via private exchange with one of the original authors, the hardware
 * should generally finish a transaction in about 5us.  The worst
 * case, is when using the arbiter and both other CPUs have just
 * started trying to use the SSBI bus will result in a time of about
 * 20us.  It should never take longer than this.
 *
 * As such, this wait merely spins, with a udelay.
 */
static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask)
{
	u32 timeout = SSBI_TIMEOUT_US;
	u32 val;

	while (timeout--) {
		val = ssbi_readl(ssbi, SSBI2_STATUS);
		if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0))
			return 0;
		udelay(1);
	}

	return -ETIMEDOUT;
}

static int
ssbi_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
{
	u32 cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16);
	int ret = 0;

	if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
		u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
		mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
		ssbi_writel(ssbi, mode2, SSBI2_MODE2);
	}

	while (len) {
		ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
		if (ret)
			goto err;

		ssbi_writel(ssbi, cmd, SSBI2_CMD);
		ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0);
		if (ret)
			goto err;
		*buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff;
		len--;
	}

err:
	return ret;
}

static int
ssbi_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
{
	int ret = 0;

	if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
		u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
		mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
		ssbi_writel(ssbi, mode2, SSBI2_MODE2);
	}

	while (len) {
		ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
		if (ret)
			goto err;

		ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD);
		ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY);
		if (ret)
			goto err;
		buf++;
		len--;
	}

err:
	return ret;
}

/*
 * See ssbi_wait_mask for an explanation of the time and the
 * busywait.
 */
static inline int
ssbi_pa_transfer(struct ssbi *ssbi, u32 cmd, u8 *data)
{
	u32 timeout = SSBI_TIMEOUT_US;
	u32 rd_status = 0;

	ssbi_writel(ssbi, cmd, SSBI_PA_CMD);

	while (timeout--) {
		rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS);

		if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED)
			return -EPERM;

		if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) {
			if (data)
				*data = rd_status & 0xff;
			return 0;
		}
		udelay(1);
	}

	return -ETIMEDOUT;
}

static int
ssbi_pa_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
{
	u32 cmd;
	int ret = 0;

	cmd = SSBI_PA_CMD_RDWRN | (addr & SSBI_PA_CMD_ADDR_MASK) << 8;

	while (len) {
		ret = ssbi_pa_transfer(ssbi, cmd, buf);
		if (ret)
			goto err;
		buf++;
		len--;
	}

err:
	return ret;
}

static int
ssbi_pa_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
{
	u32 cmd;
	int ret = 0;

	while (len) {
		cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 | *buf;
		ret = ssbi_pa_transfer(ssbi, cmd, NULL);
		if (ret)
			goto err;
		buf++;
		len--;
	}

err:
	return ret;
}

int ssbi_read(struct device *dev, u16 addr, u8 *buf, int len)
{
	struct ssbi *ssbi = dev_get_drvdata(dev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&ssbi->lock, flags);
	ret = ssbi->read(ssbi, addr, buf, len);
	spin_unlock_irqrestore(&ssbi->lock, flags);

	return ret;
}
EXPORT_SYMBOL_GPL(ssbi_read);

int ssbi_write(struct device *dev, u16 addr, const u8 *buf, int len)
{
	struct ssbi *ssbi = dev_get_drvdata(dev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&ssbi->lock, flags);
	ret = ssbi->write(ssbi, addr, buf, len);
	spin_unlock_irqrestore(&ssbi->lock, flags);

	return ret;
}
EXPORT_SYMBOL_GPL(ssbi_write);

static int ssbi_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct resource *mem_res;
	struct ssbi *ssbi;
	const char *type;

	ssbi = devm_kzalloc(&pdev->dev, sizeof(*ssbi), GFP_KERNEL);
	if (!ssbi)
		return -ENOMEM;

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ssbi->base = devm_ioremap_resource(&pdev->dev, mem_res);
	if (IS_ERR(ssbi->base))
		return PTR_ERR(ssbi->base);

	platform_set_drvdata(pdev, ssbi);

	type = of_get_property(np, "qcom,controller-type", NULL);
	if (type == NULL) {
		dev_err(&pdev->dev, "Missing qcom,controller-type property\n");
		return -EINVAL;
	}
	dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type);
	if (strcmp(type, "ssbi") == 0)
		ssbi->controller_type = MSM_SBI_CTRL_SSBI;
	else if (strcmp(type, "ssbi2") == 0)
		ssbi->controller_type = MSM_SBI_CTRL_SSBI2;
	else if (strcmp(type, "pmic-arbiter") == 0)
		ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER;
	else {
		dev_err(&pdev->dev, "Unknown qcom,controller-type\n");
		return -EINVAL;
	}

	if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) {
		ssbi->read = ssbi_pa_read_bytes;
		ssbi->write = ssbi_pa_write_bytes;
	} else {
		ssbi->read = ssbi_read_bytes;
		ssbi->write = ssbi_write_bytes;
	}

	spin_lock_init(&ssbi->lock);

	return devm_of_platform_populate(&pdev->dev);
}

static const struct of_device_id ssbi_match_table[] = {
	{ .compatible = "qcom,ssbi" },
	{}
};
MODULE_DEVICE_TABLE(of, ssbi_match_table);

static struct platform_driver ssbi_driver = {
	.probe		= ssbi_probe,
	.driver		= {
		.name	= "ssbi",
		.of_match_table = ssbi_match_table,
	},
};
module_platform_driver(ssbi_driver);

MODULE_LICENSE("GPL v2");
MODULE_VERSION("1.0");
MODULE_ALIAS("platform:ssbi");
MODULE_AUTHOR("Dima Zavin <dima@android.com>");
Commit	Line	Data
ce44bf5b	1	/* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
e44b0cee KH	2	* Copyright (c) 2010, Google Inc.
	3	*
	4	* Original authors: Code Aurora Forum
	5	*
	6	* Author: Dima Zavin <dima@android.com>
	7	* - Largely rewritten from original to not be an i2c driver.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 and
	11	* only version 2 as published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
	19	#define pr_fmt(fmt) "%s: " fmt, __func__
	20
	21	#include <linux/delay.h>
	22	#include <linux/err.h>
	23	#include <linux/io.h>
	24	#include <linux/kernel.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/slab.h>
ce44bf5b	27	#include <linux/ssbi.h>
e44b0cee	28	#include <linux/module.h>
97f00f71 DB	29	#include <linux/of.h>
97f00f71 DB	30	#include <linux/of_device.h>
e44b0cee KH	31
	32	/* SSBI 2.0 controller registers */
	33	#define SSBI2_CMD 0x0008
	34	#define SSBI2_RD 0x0010
	35	#define SSBI2_STATUS 0x0014
	36	#define SSBI2_MODE2 0x001C
	37
	38	/* SSBI_CMD fields */
	39	#define SSBI_CMD_RDWRN (1 << 24)
	40
	41	/* SSBI_STATUS fields */
	42	#define SSBI_STATUS_RD_READY (1 << 2)
	43	#define SSBI_STATUS_READY (1 << 1)
	44	#define SSBI_STATUS_MCHN_BUSY (1 << 0)
	45
	46	/* SSBI_MODE2 fields */
	47	#define SSBI_MODE2_REG_ADDR_15_8_SHFT 0x04
	48	#define SSBI_MODE2_REG_ADDR_15_8_MASK (0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT)
	49
	50	#define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \
	51	(((MD) & 0x0F) \| ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \
	52	SSBI_MODE2_REG_ADDR_15_8_MASK))
	53
	54	/* SSBI PMIC Arbiter command registers */
	55	#define SSBI_PA_CMD 0x0000
	56	#define SSBI_PA_RD_STATUS 0x0004
	57
	58	/* SSBI_PA_CMD fields */
	59	#define SSBI_PA_CMD_RDWRN (1 << 24)
	60	#define SSBI_PA_CMD_ADDR_MASK 0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/
	61
	62	/* SSBI_PA_RD_STATUS fields */
	63	#define SSBI_PA_RD_STATUS_TRANS_DONE (1 << 27)
	64	#define SSBI_PA_RD_STATUS_TRANS_DENIED (1 << 26)
	65
	66	#define SSBI_TIMEOUT_US 100
	67
bae911a0 SB	68	enum ssbi_controller_type {
	69	MSM_SBI_CTRL_SSBI = 0,
	70	MSM_SBI_CTRL_SSBI2,
	71	MSM_SBI_CTRL_PMIC_ARBITER,
	72	};
	73
ce44bf5b	74	struct ssbi {
e44b0cee KH	75	struct device *slave;
	76	void __iomem *base;
	77	spinlock_t lock;
ce44bf5b DB	78	enum ssbi_controller_type controller_type;
ce44bf5b DB	79	int (read)(struct ssbi , u16 addr, u8 *buf, int len);
5eec14cc	80	int (write)(struct ssbi , u16 addr, const u8 *buf, int len);
e44b0cee KH	81	};
e44b0cee KH	82
ce44bf5b	83	static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg)
e44b0cee KH	84	{
	85	return readl(ssbi->base + reg);
	86	}
	87
ce44bf5b	88	static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg)
e44b0cee KH	89	{
	90	writel(val, ssbi->base + reg);
	91	}
	92
3f7a73b5 DB	93	/*
	94	* Via private exchange with one of the original authors, the hardware
	95	* should generally finish a transaction in about 5us. The worst
	96	* case, is when using the arbiter and both other CPUs have just
	97	* started trying to use the SSBI bus will result in a time of about
	98	* 20us. It should never take longer than this.
	99	*
	100	* As such, this wait merely spins, with a udelay.
	101	*/
ce44bf5b	102	static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask)
e44b0cee KH	103	{
	104	u32 timeout = SSBI_TIMEOUT_US;
	105	u32 val;
	106
	107	while (timeout--) {
	108	val = ssbi_readl(ssbi, SSBI2_STATUS);
	109	if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0))
	110	return 0;
	111	udelay(1);
	112	}
	113
e44b0cee KH	114	return -ETIMEDOUT;
	115	}
	116
	117	static int
ce44bf5b	118	ssbi_read_bytes(struct ssbi ssbi, u16 addr, u8 buf, int len)
e44b0cee KH	119	{
	120	u32 cmd = SSBI_CMD_RDWRN \| ((addr & 0xff) << 16);
	121	int ret = 0;
	122
	123	if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
	124	u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
	125	mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
	126	ssbi_writel(ssbi, mode2, SSBI2_MODE2);
	127	}
	128
	129	while (len) {
	130	ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
	131	if (ret)
	132	goto err;
	133
	134	ssbi_writel(ssbi, cmd, SSBI2_CMD);
	135	ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0);
	136	if (ret)
	137	goto err;
	138	*buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff;
	139	len--;
	140	}
	141
	142	err:
	143	return ret;
	144	}
	145
	146	static int
5eec14cc	147	ssbi_write_bytes(struct ssbi ssbi, u16 addr, const u8 buf, int len)
e44b0cee KH	148	{
	149	int ret = 0;
	150
	151	if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
	152	u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
	153	mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
	154	ssbi_writel(ssbi, mode2, SSBI2_MODE2);
	155	}
	156
	157	while (len) {
	158	ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
	159	if (ret)
	160	goto err;
	161
	162	ssbi_writel(ssbi, ((addr & 0xff) << 16) \| *buf, SSBI2_CMD);
	163	ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY);
	164	if (ret)
	165	goto err;
	166	buf++;
	167	len--;
	168	}
	169
	170	err:
	171	return ret;
	172	}
	173
3f7a73b5 DB	174	/*
	175	* See ssbi_wait_mask for an explanation of the time and the
	176	* busywait.
	177	*/
e44b0cee	178	static inline int
ce44bf5b	179	ssbi_pa_transfer(struct ssbi ssbi, u32 cmd, u8 data)
e44b0cee KH	180	{
	181	u32 timeout = SSBI_TIMEOUT_US;
	182	u32 rd_status = 0;
	183
	184	ssbi_writel(ssbi, cmd, SSBI_PA_CMD);
	185
	186	while (timeout--) {
	187	rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS);
	188
37799ef4	189	if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED)
e44b0cee	190	return -EPERM;
e44b0cee KH	191
	192	if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) {
	193	if (data)
	194	*data = rd_status & 0xff;
	195	return 0;
	196	}
	197	udelay(1);
	198	}
	199
e44b0cee KH	200	return -ETIMEDOUT;
	201	}
	202
	203	static int
ce44bf5b	204	ssbi_pa_read_bytes(struct ssbi ssbi, u16 addr, u8 buf, int len)
e44b0cee KH	205	{
	206	u32 cmd;
	207	int ret = 0;
	208
	209	cmd = SSBI_PA_CMD_RDWRN \| (addr & SSBI_PA_CMD_ADDR_MASK) << 8;
	210
	211	while (len) {
ce44bf5b	212	ret = ssbi_pa_transfer(ssbi, cmd, buf);
e44b0cee KH	213	if (ret)
	214	goto err;
	215	buf++;
	216	len--;
	217	}
	218
	219	err:
	220	return ret;
	221	}
	222
	223	static int
5eec14cc	224	ssbi_pa_write_bytes(struct ssbi ssbi, u16 addr, const u8 buf, int len)
e44b0cee KH	225	{
	226	u32 cmd;
	227	int ret = 0;
	228
	229	while (len) {
	230	cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 \| *buf;
ce44bf5b	231	ret = ssbi_pa_transfer(ssbi, cmd, NULL);
e44b0cee KH	232	if (ret)
	233	goto err;
	234	buf++;
	235	len--;
	236	}
	237
	238	err:
	239	return ret;
	240	}
	241
ce44bf5b	242	int ssbi_read(struct device dev, u16 addr, u8 buf, int len)
e44b0cee	243	{
ed835136	244	struct ssbi *ssbi = dev_get_drvdata(dev);
e44b0cee KH	245	unsigned long flags;
	246	int ret;
	247
e44b0cee KH	248	spin_lock_irqsave(&ssbi->lock, flags);
	249	ret = ssbi->read(ssbi, addr, buf, len);
	250	spin_unlock_irqrestore(&ssbi->lock, flags);
	251
	252	return ret;
	253	}
ce44bf5b	254	EXPORT_SYMBOL_GPL(ssbi_read);
e44b0cee	255
5eec14cc	256	int ssbi_write(struct device dev, u16 addr, const u8 buf, int len)
e44b0cee	257	{
ed835136	258	struct ssbi *ssbi = dev_get_drvdata(dev);
e44b0cee KH	259	unsigned long flags;
	260	int ret;
	261
e44b0cee KH	262	spin_lock_irqsave(&ssbi->lock, flags);
	263	ret = ssbi->write(ssbi, addr, buf, len);
	264	spin_unlock_irqrestore(&ssbi->lock, flags);
	265
	266	return ret;
	267	}
ce44bf5b	268	EXPORT_SYMBOL_GPL(ssbi_write);
e44b0cee	269
ce44bf5b	270	static int ssbi_probe(struct platform_device *pdev)
e44b0cee	271	{
97f00f71	272	struct device_node *np = pdev->dev.of_node;
e44b0cee	273	struct resource *mem_res;
ce44bf5b	274	struct ssbi *ssbi;
97f00f71	275	const char *type;
e44b0cee	276
e5784388 SB	277	ssbi = devm_kzalloc(&pdev->dev, sizeof(*ssbi), GFP_KERNEL);
e5784388 SB	278	if (!ssbi)
e44b0cee	279	return -ENOMEM;
e44b0cee KH	280
e44b0cee KH	281	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
e5784388 SB	282	ssbi->base = devm_ioremap_resource(&pdev->dev, mem_res);
	283	if (IS_ERR(ssbi->base))
	284	return PTR_ERR(ssbi->base);
e44b0cee	285
e44b0cee KH	286	platform_set_drvdata(pdev, ssbi);
e44b0cee KH	287
97f00f71 DB	288	type = of_get_property(np, "qcom,controller-type", NULL);
97f00f71 DB	289	if (type == NULL) {
e5784388 SB	290	dev_err(&pdev->dev, "Missing qcom,controller-type property\n");
e5784388 SB	291	return -EINVAL;
97f00f71 DB	292	}
	293	dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type);
	294	if (strcmp(type, "ssbi") == 0)
	295	ssbi->controller_type = MSM_SBI_CTRL_SSBI;
	296	else if (strcmp(type, "ssbi2") == 0)
	297	ssbi->controller_type = MSM_SBI_CTRL_SSBI2;
	298	else if (strcmp(type, "pmic-arbiter") == 0)
	299	ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER;
	300	else {
e5784388 SB	301	dev_err(&pdev->dev, "Unknown qcom,controller-type\n");
e5784388 SB	302	return -EINVAL;
97f00f71 DB	303	}
97f00f71 DB	304
e44b0cee	305	if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) {
ce44bf5b DB	306	ssbi->read = ssbi_pa_read_bytes;
ce44bf5b DB	307	ssbi->write = ssbi_pa_write_bytes;
e44b0cee	308	} else {
ce44bf5b DB	309	ssbi->read = ssbi_read_bytes;
ce44bf5b DB	310	ssbi->write = ssbi_write_bytes;
e44b0cee KH	311	}
	312
	313	spin_lock_init(&ssbi->lock);
	314
f38aa351	315	return devm_of_platform_populate(&pdev->dev);
e44b0cee KH	316	}
e44b0cee KH	317
12eda2a2	318	static const struct of_device_id ssbi_match_table[] = {
97f00f71 DB	319	{ .compatible = "qcom,ssbi" },
	320	{}
	321	};
6378c1e5	322	MODULE_DEVICE_TABLE(of, ssbi_match_table);
97f00f71	323
ce44bf5b DB	324	static struct platform_driver ssbi_driver = {
ce44bf5b DB	325	.probe = ssbi_probe,
e44b0cee	326	.driver = {
ce44bf5b	327	.name = "ssbi",
97f00f71	328	.of_match_table = ssbi_match_table,
e44b0cee KH	329	},
e44b0cee KH	330	};
e5784388	331	module_platform_driver(ssbi_driver);
e44b0cee KH	332
	333	MODULE_LICENSE("GPL v2");
	334	MODULE_VERSION("1.0");
ce44bf5b	335	MODULE_ALIAS("platform:ssbi");
e44b0cee	336	MODULE_AUTHOR("Dima Zavin <dima@android.com>");