[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / t7l66xb.c

/*
 *
 * Toshiba T7L66XB core mfd support
 *
 * Copyright (c) 2005, 2007, 2008 Ian Molton
 * Copyright (c) 2008 Dmitry Baryshkov
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * T7L66 features:
 *
 * Supported in this driver:
 * SD/MMC
 * SM/NAND flash controller
 *
 * As yet not supported
 * GPIO interface (on NAND pins)
 * Serial interface
 * TFT 'interface converter'
 * PCMCIA interface logic
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tmio.h>
#include <linux/mfd/t7l66xb.h>

enum {
	T7L66XB_CELL_NAND,
	T7L66XB_CELL_MMC,
};

static const struct resource t7l66xb_mmc_resources[] = {
	{
		.start = 0x800,
		.end	= 0x9ff,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_T7L66XB_MMC,
		.end	= IRQ_T7L66XB_MMC,
		.flags = IORESOURCE_IRQ,
	},
};

#define SCR_REVID	0x08		/* b Revision ID	*/
#define SCR_IMR		0x42		/* b Interrupt Mask	*/
#define SCR_DEV_CTL	0xe0		/* b Device control	*/
#define SCR_ISR		0xe1		/* b Interrupt Status	*/
#define SCR_GPO_OC	0xf0		/* b GPO output control	*/
#define SCR_GPO_OS	0xf1		/* b GPO output enable	*/
#define SCR_GPI_S	0xf2		/* w GPI status		*/
#define SCR_APDC	0xf8		/* b Active pullup down ctrl */

#define SCR_DEV_CTL_USB		BIT(0)	/* USB enable		*/
#define SCR_DEV_CTL_MMC		BIT(1)	/* MMC enable		*/

/*--------------------------------------------------------------------------*/

struct t7l66xb {
	void __iomem		*scr;
	/* Lock to protect registers requiring read/modify/write ops. */
	raw_spinlock_t		lock;

	struct resource		rscr;
	struct clk		*clk48m;
	struct clk		*clk32k;
	int			irq;
	int			irq_base;
};

/*--------------------------------------------------------------------------*/

static int t7l66xb_mmc_enable(struct platform_device *mmc)
{
	struct platform_device *dev = to_platform_device(mmc->dev.parent);
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	unsigned long flags;
	u8 dev_ctl;
	int ret;

	ret = clk_prepare_enable(t7l66xb->clk32k);
	if (ret)
		return ret;

	raw_spin_lock_irqsave(&t7l66xb->lock, flags);

	dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
	dev_ctl |= SCR_DEV_CTL_MMC;
	tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);

	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);

	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
		t7l66xb_mmc_resources[0].start & 0xfffe);

	return 0;
}

static int t7l66xb_mmc_disable(struct platform_device *mmc)
{
	struct platform_device *dev = to_platform_device(mmc->dev.parent);
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	unsigned long flags;
	u8 dev_ctl;

	raw_spin_lock_irqsave(&t7l66xb->lock, flags);

	dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
	dev_ctl &= ~SCR_DEV_CTL_MMC;
	tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);

	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);

	clk_disable_unprepare(t7l66xb->clk32k);

	return 0;
}

static void t7l66xb_mmc_pwr(struct platform_device *mmc, int state)
{
	struct platform_device *dev = to_platform_device(mmc->dev.parent);
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);

	tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state);
}

static void t7l66xb_mmc_clk_div(struct platform_device *mmc, int state)
{
	struct platform_device *dev = to_platform_device(mmc->dev.parent);
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);

	tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state);
}

/*--------------------------------------------------------------------------*/

static struct tmio_mmc_data t7166xb_mmc_data = {
	.hclk = 24000000,
	.set_pwr = t7l66xb_mmc_pwr,
	.set_clk_div = t7l66xb_mmc_clk_div,
};

static const struct resource t7l66xb_nand_resources[] = {
	{
		.start	= 0xc00,
		.end	= 0xc07,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= 0x0100,
		.end	= 0x01ff,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_T7L66XB_NAND,
		.end	= IRQ_T7L66XB_NAND,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mfd_cell t7l66xb_cells[] = {
	[T7L66XB_CELL_MMC] = {
		.name = "tmio-mmc",
		.enable = t7l66xb_mmc_enable,
		.disable = t7l66xb_mmc_disable,
		.platform_data = &t7166xb_mmc_data,
		.pdata_size    = sizeof(t7166xb_mmc_data),
		.num_resources = ARRAY_SIZE(t7l66xb_mmc_resources),
		.resources = t7l66xb_mmc_resources,
	},
	[T7L66XB_CELL_NAND] = {
		.name = "tmio-nand",
		.num_resources = ARRAY_SIZE(t7l66xb_nand_resources),
		.resources = t7l66xb_nand_resources,
	},
};

/*--------------------------------------------------------------------------*/

/* Handle the T7L66XB interrupt mux */
static void t7l66xb_irq(struct irq_desc *desc)
{
	struct t7l66xb *t7l66xb = irq_desc_get_handler_data(desc);
	unsigned int isr;
	unsigned int i, irq_base;

	irq_base = t7l66xb->irq_base;

	while ((isr = tmio_ioread8(t7l66xb->scr + SCR_ISR) &
				~tmio_ioread8(t7l66xb->scr + SCR_IMR)))
		for (i = 0; i < T7L66XB_NR_IRQS; i++)
			if (isr & (1 << i))
				generic_handle_irq(irq_base + i);
}

static void t7l66xb_irq_mask(struct irq_data *data)
{
	struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
	unsigned long			flags;
	u8 imr;

	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
	imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
	imr |= 1 << (data->irq - t7l66xb->irq_base);
	tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
}

static void t7l66xb_irq_unmask(struct irq_data *data)
{
	struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
	unsigned long flags;
	u8 imr;

	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
	imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
	imr &= ~(1 << (data->irq - t7l66xb->irq_base));
	tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
}

static struct irq_chip t7l66xb_chip = {
	.name		= "t7l66xb",
	.irq_ack	= t7l66xb_irq_mask,
	.irq_mask	= t7l66xb_irq_mask,
	.irq_unmask	= t7l66xb_irq_unmask,
};

/*--------------------------------------------------------------------------*/

/* Install the IRQ handler */
static void t7l66xb_attach_irq(struct platform_device *dev)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	unsigned int irq, irq_base;

	irq_base = t7l66xb->irq_base;

	for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
		irq_set_chip_and_handler(irq, &t7l66xb_chip, handle_level_irq);
		irq_set_chip_data(irq, t7l66xb);
	}

	irq_set_irq_type(t7l66xb->irq, IRQ_TYPE_EDGE_FALLING);
	irq_set_chained_handler_and_data(t7l66xb->irq, t7l66xb_irq, t7l66xb);
}

static void t7l66xb_detach_irq(struct platform_device *dev)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	unsigned int irq, irq_base;

	irq_base = t7l66xb->irq_base;

	irq_set_chained_handler_and_data(t7l66xb->irq, NULL, NULL);

	for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
		irq_set_chip(irq, NULL);
		irq_set_chip_data(irq, NULL);
	}
}

/*--------------------------------------------------------------------------*/

#ifdef CONFIG_PM
static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);

	if (pdata && pdata->suspend)
		pdata->suspend(dev);
	clk_disable_unprepare(t7l66xb->clk48m);

	return 0;
}

static int t7l66xb_resume(struct platform_device *dev)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
	int ret;

	ret = clk_prepare_enable(t7l66xb->clk48m);
	if (ret)
		return ret;

	if (pdata && pdata->resume)
		pdata->resume(dev);

	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
		t7l66xb_mmc_resources[0].start & 0xfffe);

	return 0;
}
#else
#define t7l66xb_suspend NULL
#define t7l66xb_resume	NULL
#endif

/*--------------------------------------------------------------------------*/

static int t7l66xb_probe(struct platform_device *dev)
{
	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
	struct t7l66xb *t7l66xb;
	struct resource *iomem, *rscr;
	int ret;

	if (!pdata)
		return -EINVAL;

	iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!iomem)
		return -EINVAL;

	t7l66xb = kzalloc(sizeof *t7l66xb, GFP_KERNEL);
	if (!t7l66xb)
		return -ENOMEM;

	raw_spin_lock_init(&t7l66xb->lock);

	platform_set_drvdata(dev, t7l66xb);

	ret = platform_get_irq(dev, 0);
	if (ret >= 0)
		t7l66xb->irq = ret;
	else
		goto err_noirq;

	t7l66xb->irq_base = pdata->irq_base;

	t7l66xb->clk32k = clk_get(&dev->dev, "CLK_CK32K");
	if (IS_ERR(t7l66xb->clk32k)) {
		ret = PTR_ERR(t7l66xb->clk32k);
		goto err_clk32k_get;
	}

	t7l66xb->clk48m = clk_get(&dev->dev, "CLK_CK48M");
	if (IS_ERR(t7l66xb->clk48m)) {
		ret = PTR_ERR(t7l66xb->clk48m);
		goto err_clk48m_get;
	}

	rscr = &t7l66xb->rscr;
	rscr->name = "t7l66xb-core";
	rscr->start = iomem->start;
	rscr->end = iomem->start + 0xff;
	rscr->flags = IORESOURCE_MEM;

	ret = request_resource(iomem, rscr);
	if (ret)
		goto err_request_scr;

	t7l66xb->scr = ioremap(rscr->start, resource_size(rscr));
	if (!t7l66xb->scr) {
		ret = -ENOMEM;
		goto err_ioremap;
	}

	ret = clk_prepare_enable(t7l66xb->clk48m);
	if (ret)
		goto err_clk_enable;

	if (pdata->enable)
		pdata->enable(dev);

	/* Mask all interrupts */
	tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR);

	printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n",
		dev->name, tmio_ioread8(t7l66xb->scr + SCR_REVID),
		(unsigned long)iomem->start, t7l66xb->irq);

	t7l66xb_attach_irq(dev);

	t7l66xb_cells[T7L66XB_CELL_NAND].platform_data = pdata->nand_data;
	t7l66xb_cells[T7L66XB_CELL_NAND].pdata_size = sizeof(*pdata->nand_data);

	ret = mfd_add_devices(&dev->dev, dev->id,
			      t7l66xb_cells, ARRAY_SIZE(t7l66xb_cells),
			      iomem, t7l66xb->irq_base, NULL);

	if (!ret)
		return 0;

	t7l66xb_detach_irq(dev);
	clk_disable_unprepare(t7l66xb->clk48m);
err_clk_enable:
	iounmap(t7l66xb->scr);
err_ioremap:
	release_resource(&t7l66xb->rscr);
err_request_scr:
	clk_put(t7l66xb->clk48m);
err_clk48m_get:
	clk_put(t7l66xb->clk32k);
err_clk32k_get:
err_noirq:
	kfree(t7l66xb);
	return ret;
}

static int t7l66xb_remove(struct platform_device *dev)
{
	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	int ret;

	ret = pdata->disable(dev);
	clk_disable_unprepare(t7l66xb->clk48m);
	clk_put(t7l66xb->clk48m);
	clk_disable_unprepare(t7l66xb->clk32k);
	clk_put(t7l66xb->clk32k);
	t7l66xb_detach_irq(dev);
	iounmap(t7l66xb->scr);
	release_resource(&t7l66xb->rscr);
	mfd_remove_devices(&dev->dev);
	kfree(t7l66xb);

	return ret;

}

static struct platform_driver t7l66xb_platform_driver = {
	.driver = {
		.name	= "t7l66xb",
	},
	.suspend	= t7l66xb_suspend,
	.resume		= t7l66xb_resume,
	.probe		= t7l66xb_probe,
	.remove		= t7l66xb_remove,
};

/*--------------------------------------------------------------------------*/

module_platform_driver(t7l66xb_platform_driver);

MODULE_DESCRIPTION("Toshiba T7L66XB core driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Ian Molton");
MODULE_ALIAS("platform:t7l66xb");
Commit	Line	Data
1f192015 IM	1	/*
	2	*
	3	* Toshiba T7L66XB core mfd support
	4	*
	5	* Copyright (c) 2005, 2007, 2008 Ian Molton
	6	* Copyright (c) 2008 Dmitry Baryshkov
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* T7L66 features:
	13	*
	14	* Supported in this driver:
	15	* SD/MMC
	16	* SM/NAND flash controller
	17	*
	18	* As yet not supported
	19	* GPIO interface (on NAND pins)
	20	* Serial interface
	21	* TFT 'interface converter'
	22	* PCMCIA interface logic
	23	*/
	24
	25	#include <linux/kernel.h>
	26	#include <linux/module.h>
7acb706c	27	#include <linux/err.h>
1f192015	28	#include <linux/io.h>
5a0e3ad6	29	#include <linux/slab.h>
1f192015	30	#include <linux/irq.h>
7acb706c	31	#include <linux/clk.h>
1f192015 IM	32	#include <linux/platform_device.h>
	33	#include <linux/mfd/core.h>
	34	#include <linux/mfd/tmio.h>
	35	#include <linux/mfd/t7l66xb.h>
	36
	37	enum {
	38	T7L66XB_CELL_NAND,
	39	T7L66XB_CELL_MMC,
	40	};
	41
64e8867b IM	42	static const struct resource t7l66xb_mmc_resources[] = {
	43	{
	44	.start = 0x800,
	45	.end = 0x9ff,
	46	.flags = IORESOURCE_MEM,
	47	},
	48	{
	49	.start = IRQ_T7L66XB_MMC,
	50	.end = IRQ_T7L66XB_MMC,
	51	.flags = IORESOURCE_IRQ,
	52	},
	53	};
	54
1f192015 IM	55	#define SCR_REVID 0x08 /* b Revision ID */
	56	#define SCR_IMR 0x42 /* b Interrupt Mask */
	57	#define SCR_DEV_CTL 0xe0 /* b Device control */
	58	#define SCR_ISR 0xe1 /* b Interrupt Status */
	59	#define SCR_GPO_OC 0xf0 /* b GPO output control */
	60	#define SCR_GPO_OS 0xf1 /* b GPO output enable */
	61	#define SCR_GPI_S 0xf2 /* w GPI status */
	62	#define SCR_APDC 0xf8 /* b Active pullup down ctrl */
	63
	64	#define SCR_DEV_CTL_USB BIT(0) /* USB enable */
	65	#define SCR_DEV_CTL_MMC BIT(1) /* MMC enable */
	66
	67	/--------------------------------------------------------------------------/
	68
	69	struct t7l66xb {
	70	void __iomem *scr;
	71	/* Lock to protect registers requiring read/modify/write ops. */
9fe8c2df	72	raw_spinlock_t lock;
1f192015 IM	73
1f192015 IM	74	struct resource rscr;
7acb706c IM	75	struct clk *clk48m;
7acb706c IM	76	struct clk *clk32k;
1f192015 IM	77	int irq;
	78	int irq_base;
	79	};
	80
	81	/--------------------------------------------------------------------------/
	82
	83	static int t7l66xb_mmc_enable(struct platform_device *mmc)
	84	{
	85	struct platform_device *dev = to_platform_device(mmc->dev.parent);
1f192015 IM	86	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	87	unsigned long flags;
	88	u8 dev_ctl;
b62d8dbe	89	int ret;
1f192015	90
b62d8dbe AY	91	ret = clk_prepare_enable(t7l66xb->clk32k);
	92	if (ret)
	93	return ret;
1f192015	94
9fe8c2df	95	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
1f192015 IM	96
	97	dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
	98	dev_ctl \|= SCR_DEV_CTL_MMC;
	99	tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
	100
9fe8c2df	101	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
1f192015	102
64e8867b IM	103	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
	104	t7l66xb_mmc_resources[0].start & 0xfffe);
	105
1f192015 IM	106	return 0;
	107	}
	108
	109	static int t7l66xb_mmc_disable(struct platform_device *mmc)
	110	{
	111	struct platform_device *dev = to_platform_device(mmc->dev.parent);
1f192015 IM	112	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	113	unsigned long flags;
	114	u8 dev_ctl;
	115
9fe8c2df	116	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
1f192015 IM	117
	118	dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
	119	dev_ctl &= ~SCR_DEV_CTL_MMC;
	120	tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
	121
9fe8c2df	122	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
1f192015	123
71d679b8	124	clk_disable_unprepare(t7l66xb->clk32k);
1f192015 IM	125
	126	return 0;
	127	}
	128
64e8867b IM	129	static void t7l66xb_mmc_pwr(struct platform_device *mmc, int state)
	130	{
	131	struct platform_device *dev = to_platform_device(mmc->dev.parent);
	132	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	133
	134	tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state);
	135	}
	136
	137	static void t7l66xb_mmc_clk_div(struct platform_device *mmc, int state)
	138	{
	139	struct platform_device *dev = to_platform_device(mmc->dev.parent);
	140	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	141
	142	tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state);
	143	}
	144
1f192015 IM	145	/--------------------------------------------------------------------------/
1f192015 IM	146
4d3792e0	147	static struct tmio_mmc_data t7166xb_mmc_data = {
f0e46cc4	148	.hclk = 24000000,
64e8867b IM	149	.set_pwr = t7l66xb_mmc_pwr,
64e8867b IM	150	.set_clk_div = t7l66xb_mmc_clk_div,
1f192015 IM	151	};
1f192015 IM	152
3446d4bb	153	static const struct resource t7l66xb_nand_resources[] = {
1f192015 IM	154	{
	155	.start = 0xc00,
	156	.end = 0xc07,
	157	.flags = IORESOURCE_MEM,
	158	},
	159	{
	160	.start = 0x0100,
	161	.end = 0x01ff,
	162	.flags = IORESOURCE_MEM,
	163	},
	164	{
	165	.start = IRQ_T7L66XB_NAND,
	166	.end = IRQ_T7L66XB_NAND,
	167	.flags = IORESOURCE_IRQ,
	168	},
	169	};
	170
	171	static struct mfd_cell t7l66xb_cells[] = {
	172	[T7L66XB_CELL_MMC] = {
	173	.name = "tmio-mmc",
	174	.enable = t7l66xb_mmc_enable,
	175	.disable = t7l66xb_mmc_disable,
ec71974f SO	176	.platform_data = &t7166xb_mmc_data,
ec71974f SO	177	.pdata_size = sizeof(t7166xb_mmc_data),
1f192015 IM	178	.num_resources = ARRAY_SIZE(t7l66xb_mmc_resources),
	179	.resources = t7l66xb_mmc_resources,
	180	},
	181	[T7L66XB_CELL_NAND] = {
	182	.name = "tmio-nand",
	183	.num_resources = ARRAY_SIZE(t7l66xb_nand_resources),
	184	.resources = t7l66xb_nand_resources,
	185	},
	186	};
	187
	188	/--------------------------------------------------------------------------/
	189
	190	/* Handle the T7L66XB interrupt mux */
bd0b9ac4	191	static void t7l66xb_irq(struct irq_desc *desc)
1f192015	192	{
1e84aa44	193	struct t7l66xb *t7l66xb = irq_desc_get_handler_data(desc);
1f192015 IM	194	unsigned int isr;
	195	unsigned int i, irq_base;
	196
	197	irq_base = t7l66xb->irq_base;
	198
	199	while ((isr = tmio_ioread8(t7l66xb->scr + SCR_ISR) &
	200	~tmio_ioread8(t7l66xb->scr + SCR_IMR)))
	201	for (i = 0; i < T7L66XB_NR_IRQS; i++)
	202	if (isr & (1 << i))
	203	generic_handle_irq(irq_base + i);
	204	}
	205
a4e7fead	206	static void t7l66xb_irq_mask(struct irq_data *data)
1f192015	207	{
a4e7fead	208	struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
1f192015 IM	209	unsigned long flags;
	210	u8 imr;
	211
9fe8c2df	212	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
1f192015	213	imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
a4e7fead	214	imr \|= 1 << (data->irq - t7l66xb->irq_base);
1f192015	215	tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
9fe8c2df	216	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
1f192015 IM	217	}
1f192015 IM	218
a4e7fead	219	static void t7l66xb_irq_unmask(struct irq_data *data)
1f192015	220	{
a4e7fead	221	struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
1f192015 IM	222	unsigned long flags;
	223	u8 imr;
	224
9fe8c2df	225	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
1f192015	226	imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
a4e7fead	227	imr &= ~(1 << (data->irq - t7l66xb->irq_base));
1f192015	228	tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
9fe8c2df	229	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
1f192015 IM	230	}
	231
	232	static struct irq_chip t7l66xb_chip = {
a4e7fead MB	233	.name = "t7l66xb",
	234	.irq_ack = t7l66xb_irq_mask,
	235	.irq_mask = t7l66xb_irq_mask,
	236	.irq_unmask = t7l66xb_irq_unmask,
1f192015 IM	237	};
	238
	239	/--------------------------------------------------------------------------/
	240
	241	/* Install the IRQ handler */
	242	static void t7l66xb_attach_irq(struct platform_device *dev)
	243	{
	244	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	245	unsigned int irq, irq_base;
	246
	247	irq_base = t7l66xb->irq_base;
	248
	249	for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
d6f7ce9f	250	irq_set_chip_and_handler(irq, &t7l66xb_chip, handle_level_irq);
d5bb1221	251	irq_set_chip_data(irq, t7l66xb);
1f192015 IM	252	}
1f192015 IM	253
d5bb1221	254	irq_set_irq_type(t7l66xb->irq, IRQ_TYPE_EDGE_FALLING);
de7c9e0d	255	irq_set_chained_handler_and_data(t7l66xb->irq, t7l66xb_irq, t7l66xb);
1f192015 IM	256	}
	257
	258	static void t7l66xb_detach_irq(struct platform_device *dev)
	259	{
	260	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	261	unsigned int irq, irq_base;
	262
	263	irq_base = t7l66xb->irq_base;
	264
de7c9e0d	265	irq_set_chained_handler_and_data(t7l66xb->irq, NULL, NULL);
1f192015 IM	266
1f192015 IM	267	for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
d5bb1221 TG	268	irq_set_chip(irq, NULL);
d5bb1221 TG	269	irq_set_chip_data(irq, NULL);
1f192015 IM	270	}
	271	}
	272
	273	/--------------------------------------------------------------------------/
	274
	275	#ifdef CONFIG_PM
	276	static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state)
	277	{
7acb706c	278	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
334a41ce	279	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
1f192015 IM	280
	281	if (pdata && pdata->suspend)
	282	pdata->suspend(dev);
71d679b8	283	clk_disable_unprepare(t7l66xb->clk48m);
1f192015 IM	284
	285	return 0;
	286	}
	287
	288	static int t7l66xb_resume(struct platform_device *dev)
	289	{
7acb706c	290	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
334a41ce	291	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
b62d8dbe AY	292	int ret;
	293
	294	ret = clk_prepare_enable(t7l66xb->clk48m);
	295	if (ret)
	296	return ret;
1f192015 IM	297
	298	if (pdata && pdata->resume)
	299	pdata->resume(dev);
	300
64e8867b IM	301	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
	302	t7l66xb_mmc_resources[0].start & 0xfffe);
	303
1f192015 IM	304	return 0;
	305	}
	306	#else
	307	#define t7l66xb_suspend NULL
	308	#define t7l66xb_resume NULL
	309	#endif
	310
	311	/--------------------------------------------------------------------------/
	312
	313	static int t7l66xb_probe(struct platform_device *dev)
	314	{
334a41ce	315	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
1f192015 IM	316	struct t7l66xb *t7l66xb;
	317	struct resource iomem, rscr;
	318	int ret;
	319
78b7d84c	320	if (!pdata)
9ad285d6 SO	321	return -EINVAL;
9ad285d6 SO	322
1f192015 IM	323	iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
	324	if (!iomem)
	325	return -EINVAL;
	326
	327	t7l66xb = kzalloc(sizeof *t7l66xb, GFP_KERNEL);
	328	if (!t7l66xb)
	329	return -ENOMEM;
	330
9fe8c2df	331	raw_spin_lock_init(&t7l66xb->lock);
1f192015 IM	332
	333	platform_set_drvdata(dev, t7l66xb);
	334
	335	ret = platform_get_irq(dev, 0);
	336	if (ret >= 0)
	337	t7l66xb->irq = ret;
	338	else
	339	goto err_noirq;
	340
	341	t7l66xb->irq_base = pdata->irq_base;
	342
7acb706c IM	343	t7l66xb->clk32k = clk_get(&dev->dev, "CLK_CK32K");
	344	if (IS_ERR(t7l66xb->clk32k)) {
	345	ret = PTR_ERR(t7l66xb->clk32k);
	346	goto err_clk32k_get;
	347	}
	348
	349	t7l66xb->clk48m = clk_get(&dev->dev, "CLK_CK48M");
	350	if (IS_ERR(t7l66xb->clk48m)) {
	351	ret = PTR_ERR(t7l66xb->clk48m);
7acb706c IM	352	goto err_clk48m_get;
	353	}
	354
1f192015 IM	355	rscr = &t7l66xb->rscr;
	356	rscr->name = "t7l66xb-core";
	357	rscr->start = iomem->start;
	358	rscr->end = iomem->start + 0xff;
	359	rscr->flags = IORESOURCE_MEM;
	360
	361	ret = request_resource(iomem, rscr);
	362	if (ret)
	363	goto err_request_scr;
	364
c02e6a5f	365	t7l66xb->scr = ioremap(rscr->start, resource_size(rscr));
1f192015 IM	366	if (!t7l66xb->scr) {
	367	ret = -ENOMEM;
	368	goto err_ioremap;
	369	}
	370
b62d8dbe AY	371	ret = clk_prepare_enable(t7l66xb->clk48m);
	372	if (ret)
	373	goto err_clk_enable;
7acb706c	374
78b7d84c	375	if (pdata->enable)
1f192015 IM	376	pdata->enable(dev);
	377
	378	/* Mask all interrupts */
	379	tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR);
	380
	381	printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n",
	382	dev->name, tmio_ioread8(t7l66xb->scr + SCR_REVID),
	383	(unsigned long)iomem->start, t7l66xb->irq);
	384
	385	t7l66xb_attach_irq(dev);
	386
7dc00a0d SO	387	t7l66xb_cells[T7L66XB_CELL_NAND].platform_data = pdata->nand_data;
7dc00a0d SO	388	t7l66xb_cells[T7L66XB_CELL_NAND].pdata_size = sizeof(*pdata->nand_data);
8a4fbe01	389
56bf2bda SO	390	ret = mfd_add_devices(&dev->dev, dev->id,
56bf2bda SO	391	t7l66xb_cells, ARRAY_SIZE(t7l66xb_cells),
0848c94f	392	iomem, t7l66xb->irq_base, NULL);
1f192015 IM	393
	394	if (!ret)
	395	return 0;
	396
	397	t7l66xb_detach_irq(dev);
b62d8dbe AY	398	clk_disable_unprepare(t7l66xb->clk48m);
b62d8dbe AY	399	err_clk_enable:
1f192015 IM	400	iounmap(t7l66xb->scr);
	401	err_ioremap:
	402	release_resource(&t7l66xb->rscr);
1f192015	403	err_request_scr:
7acb706c IM	404	clk_put(t7l66xb->clk48m);
	405	err_clk48m_get:
	406	clk_put(t7l66xb->clk32k);
	407	err_clk32k_get:
	408	err_noirq:
0e820ab6	409	kfree(t7l66xb);
1f192015 IM	410	return ret;
	411	}
	412
	413	static int t7l66xb_remove(struct platform_device *dev)
	414	{
334a41ce	415	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
1f192015 IM	416	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	417	int ret;
	418
	419	ret = pdata->disable(dev);
71d679b8	420	clk_disable_unprepare(t7l66xb->clk48m);
7acb706c	421	clk_put(t7l66xb->clk48m);
71d679b8	422	clk_disable_unprepare(t7l66xb->clk32k);
d2d272a9	423	clk_put(t7l66xb->clk32k);
1f192015 IM	424	t7l66xb_detach_irq(dev);
	425	iounmap(t7l66xb->scr);
	426	release_resource(&t7l66xb->rscr);
56bf2bda	427	mfd_remove_devices(&dev->dev);
1f192015 IM	428	kfree(t7l66xb);
	429
	430	return ret;
	431
	432	}
	433
	434	static struct platform_driver t7l66xb_platform_driver = {
	435	.driver = {
	436	.name = "t7l66xb",
1f192015 IM	437	},
	438	.suspend = t7l66xb_suspend,
	439	.resume = t7l66xb_resume,
	440	.probe = t7l66xb_probe,
	441	.remove = t7l66xb_remove,
	442	};
	443
	444	/--------------------------------------------------------------------------/
	445
65349d60	446	module_platform_driver(t7l66xb_platform_driver);
1f192015 IM	447
	448	MODULE_DESCRIPTION("Toshiba T7L66XB core driver");
	449	MODULE_LICENSE("GPL v2");
	450	MODULE_AUTHOR("Ian Molton");
	451	MODULE_ALIAS("platform:t7l66xb");