[mirror_ubuntu-hirsute-kernel.git] / drivers / mfd / t7l66xb.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *
 * Toshiba T7L66XB core mfd support
 *
 * Copyright (c) 2005, 2007, 2008 Ian Molton
 * Copyright (c) 2008 Dmitry Baryshkov
 *
 * T7L66 features:
 *
 * Supported in this driver:
 * SD/MMC
 * SM/NAND flash controller
 *
 * As yet not supported
 * GPIO interface (on NAND pins)
 * Serial interface
 * TFT 'interface converter'
 * PCMCIA interface logic
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tmio.h>
#include <linux/mfd/t7l66xb.h>

enum {
	T7L66XB_CELL_NAND,
	T7L66XB_CELL_MMC,
};

static const struct resource t7l66xb_mmc_resources[] = {
	{
		.start = 0x800,
		.end	= 0x9ff,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_T7L66XB_MMC,
		.end	= IRQ_T7L66XB_MMC,
		.flags = IORESOURCE_IRQ,
	},
};

#define SCR_REVID	0x08		/* b Revision ID	*/
#define SCR_IMR		0x42		/* b Interrupt Mask	*/
#define SCR_DEV_CTL	0xe0		/* b Device control	*/
#define SCR_ISR		0xe1		/* b Interrupt Status	*/
#define SCR_GPO_OC	0xf0		/* b GPO output control	*/
#define SCR_GPO_OS	0xf1		/* b GPO output enable	*/
#define SCR_GPI_S	0xf2		/* w GPI status		*/
#define SCR_APDC	0xf8		/* b Active pullup down ctrl */

#define SCR_DEV_CTL_USB		BIT(0)	/* USB enable		*/
#define SCR_DEV_CTL_MMC		BIT(1)	/* MMC enable		*/

/*--------------------------------------------------------------------------*/

struct t7l66xb {
	void __iomem		*scr;
	/* Lock to protect registers requiring read/modify/write ops. */
	raw_spinlock_t		lock;

	struct resource		rscr;
	struct clk		*clk48m;
	struct clk		*clk32k;
	int			irq;
	int			irq_base;
};

/*--------------------------------------------------------------------------*/

static int t7l66xb_mmc_enable(struct platform_device *mmc)
{
	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
	unsigned long flags;
	u8 dev_ctl;
	int ret;

	ret = clk_prepare_enable(t7l66xb->clk32k);
	if (ret)
		return ret;

	raw_spin_lock_irqsave(&t7l66xb->lock, flags);

	dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
	dev_ctl |= SCR_DEV_CTL_MMC;
	tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);

	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);

	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
		t7l66xb_mmc_resources[0].start & 0xfffe);

	return 0;
}

static int t7l66xb_mmc_disable(struct platform_device *mmc)
{
	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
	unsigned long flags;
	u8 dev_ctl;

	raw_spin_lock_irqsave(&t7l66xb->lock, flags);

	dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
	dev_ctl &= ~SCR_DEV_CTL_MMC;
	tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);

	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);

	clk_disable_unprepare(t7l66xb->clk32k);

	return 0;
}

static void t7l66xb_mmc_pwr(struct platform_device *mmc, int state)
{
	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);

	tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state);
}

static void t7l66xb_mmc_clk_div(struct platform_device *mmc, int state)
{
	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);

	tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state);
}

/*--------------------------------------------------------------------------*/

static struct tmio_mmc_data t7166xb_mmc_data = {
	.hclk = 24000000,
	.set_pwr = t7l66xb_mmc_pwr,
	.set_clk_div = t7l66xb_mmc_clk_div,
};

static const struct resource t7l66xb_nand_resources[] = {
	{
		.start	= 0xc00,
		.end	= 0xc07,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= 0x0100,
		.end	= 0x01ff,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_T7L66XB_NAND,
		.end	= IRQ_T7L66XB_NAND,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mfd_cell t7l66xb_cells[] = {
	[T7L66XB_CELL_MMC] = {
		.name = "tmio-mmc",
		.enable = t7l66xb_mmc_enable,
		.disable = t7l66xb_mmc_disable,
		.platform_data = &t7166xb_mmc_data,
		.pdata_size    = sizeof(t7166xb_mmc_data),
		.num_resources = ARRAY_SIZE(t7l66xb_mmc_resources),
		.resources = t7l66xb_mmc_resources,
	},
	[T7L66XB_CELL_NAND] = {
		.name = "tmio-nand",
		.num_resources = ARRAY_SIZE(t7l66xb_nand_resources),
		.resources = t7l66xb_nand_resources,
	},
};

/*--------------------------------------------------------------------------*/

/* Handle the T7L66XB interrupt mux */
static void t7l66xb_irq(struct irq_desc *desc)
{
	struct t7l66xb *t7l66xb = irq_desc_get_handler_data(desc);
	unsigned int isr;
	unsigned int i, irq_base;

	irq_base = t7l66xb->irq_base;

	while ((isr = tmio_ioread8(t7l66xb->scr + SCR_ISR) &
				~tmio_ioread8(t7l66xb->scr + SCR_IMR)))
		for (i = 0; i < T7L66XB_NR_IRQS; i++)
			if (isr & (1 << i))
				generic_handle_irq(irq_base + i);
}

static void t7l66xb_irq_mask(struct irq_data *data)
{
	struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
	unsigned long			flags;
	u8 imr;

	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
	imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
	imr |= 1 << (data->irq - t7l66xb->irq_base);
	tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
}

static void t7l66xb_irq_unmask(struct irq_data *data)
{
	struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
	unsigned long flags;
	u8 imr;

	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
	imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
	imr &= ~(1 << (data->irq - t7l66xb->irq_base));
	tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
}

static struct irq_chip t7l66xb_chip = {
	.name		= "t7l66xb",
	.irq_ack	= t7l66xb_irq_mask,
	.irq_mask	= t7l66xb_irq_mask,
	.irq_unmask	= t7l66xb_irq_unmask,
};

/*--------------------------------------------------------------------------*/

/* Install the IRQ handler */
static void t7l66xb_attach_irq(struct platform_device *dev)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	unsigned int irq, irq_base;

	irq_base = t7l66xb->irq_base;

	for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
		irq_set_chip_and_handler(irq, &t7l66xb_chip, handle_level_irq);
		irq_set_chip_data(irq, t7l66xb);
	}

	irq_set_irq_type(t7l66xb->irq, IRQ_TYPE_EDGE_FALLING);
	irq_set_chained_handler_and_data(t7l66xb->irq, t7l66xb_irq, t7l66xb);
}

static void t7l66xb_detach_irq(struct platform_device *dev)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	unsigned int irq, irq_base;

	irq_base = t7l66xb->irq_base;

	irq_set_chained_handler_and_data(t7l66xb->irq, NULL, NULL);

	for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
		irq_set_chip(irq, NULL);
		irq_set_chip_data(irq, NULL);
	}
}

/*--------------------------------------------------------------------------*/

#ifdef CONFIG_PM
static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);

	if (pdata && pdata->suspend)
		pdata->suspend(dev);
	clk_disable_unprepare(t7l66xb->clk48m);

	return 0;
}

static int t7l66xb_resume(struct platform_device *dev)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
	int ret;

	ret = clk_prepare_enable(t7l66xb->clk48m);
	if (ret)
		return ret;

	if (pdata && pdata->resume)
		pdata->resume(dev);

	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
		t7l66xb_mmc_resources[0].start & 0xfffe);

	return 0;
}
#else
#define t7l66xb_suspend NULL
#define t7l66xb_resume	NULL
#endif

/*--------------------------------------------------------------------------*/

static int t7l66xb_probe(struct platform_device *dev)
{
	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
	struct t7l66xb *t7l66xb;
	struct resource *iomem, *rscr;
	int ret;

	if (!pdata)
		return -EINVAL;

	iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!iomem)
		return -EINVAL;

	t7l66xb = kzalloc(sizeof *t7l66xb, GFP_KERNEL);
	if (!t7l66xb)
		return -ENOMEM;

	raw_spin_lock_init(&t7l66xb->lock);

	platform_set_drvdata(dev, t7l66xb);

	ret = platform_get_irq(dev, 0);
	if (ret >= 0)
		t7l66xb->irq = ret;
	else
		goto err_noirq;

	t7l66xb->irq_base = pdata->irq_base;

	t7l66xb->clk32k = clk_get(&dev->dev, "CLK_CK32K");
	if (IS_ERR(t7l66xb->clk32k)) {
		ret = PTR_ERR(t7l66xb->clk32k);
		goto err_clk32k_get;
	}

	t7l66xb->clk48m = clk_get(&dev->dev, "CLK_CK48M");
	if (IS_ERR(t7l66xb->clk48m)) {
		ret = PTR_ERR(t7l66xb->clk48m);
		goto err_clk48m_get;
	}

	rscr = &t7l66xb->rscr;
	rscr->name = "t7l66xb-core";
	rscr->start = iomem->start;
	rscr->end = iomem->start + 0xff;
	rscr->flags = IORESOURCE_MEM;

	ret = request_resource(iomem, rscr);
	if (ret)
		goto err_request_scr;

	t7l66xb->scr = ioremap(rscr->start, resource_size(rscr));
	if (!t7l66xb->scr) {
		ret = -ENOMEM;
		goto err_ioremap;
	}

	ret = clk_prepare_enable(t7l66xb->clk48m);
	if (ret)
		goto err_clk_enable;

	if (pdata->enable)
		pdata->enable(dev);

	/* Mask all interrupts */
	tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR);

	printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n",
		dev->name, tmio_ioread8(t7l66xb->scr + SCR_REVID),
		(unsigned long)iomem->start, t7l66xb->irq);

	t7l66xb_attach_irq(dev);

	t7l66xb_cells[T7L66XB_CELL_NAND].platform_data = pdata->nand_data;
	t7l66xb_cells[T7L66XB_CELL_NAND].pdata_size = sizeof(*pdata->nand_data);

	ret = mfd_add_devices(&dev->dev, dev->id,
			      t7l66xb_cells, ARRAY_SIZE(t7l66xb_cells),
			      iomem, t7l66xb->irq_base, NULL);

	if (!ret)
		return 0;

	t7l66xb_detach_irq(dev);
	clk_disable_unprepare(t7l66xb->clk48m);
err_clk_enable:
	iounmap(t7l66xb->scr);
err_ioremap:
	release_resource(&t7l66xb->rscr);
err_request_scr:
	clk_put(t7l66xb->clk48m);
err_clk48m_get:
	clk_put(t7l66xb->clk32k);
err_clk32k_get:
err_noirq:
	kfree(t7l66xb);
	return ret;
}

static int t7l66xb_remove(struct platform_device *dev)
{
	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	int ret;

	ret = pdata->disable(dev);
	clk_disable_unprepare(t7l66xb->clk48m);
	clk_put(t7l66xb->clk48m);
	clk_disable_unprepare(t7l66xb->clk32k);
	clk_put(t7l66xb->clk32k);
	t7l66xb_detach_irq(dev);
	iounmap(t7l66xb->scr);
	release_resource(&t7l66xb->rscr);
	mfd_remove_devices(&dev->dev);
	kfree(t7l66xb);

	return ret;

}

static struct platform_driver t7l66xb_platform_driver = {
	.driver = {
		.name	= "t7l66xb",
	},
	.suspend	= t7l66xb_suspend,
	.resume		= t7l66xb_resume,
	.probe		= t7l66xb_probe,
	.remove		= t7l66xb_remove,
};

/*--------------------------------------------------------------------------*/

module_platform_driver(t7l66xb_platform_driver);

MODULE_DESCRIPTION("Toshiba T7L66XB core driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Ian Molton");
MODULE_ALIAS("platform:t7l66xb");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1f192015 IM	2	/*
	3	*
	4	* Toshiba T7L66XB core mfd support
	5	*
	6	* Copyright (c) 2005, 2007, 2008 Ian Molton
	7	* Copyright (c) 2008 Dmitry Baryshkov
	8	*
1f192015 IM	9	* T7L66 features:
	10	*
	11	* Supported in this driver:
	12	* SD/MMC
	13	* SM/NAND flash controller
	14	*
	15	* As yet not supported
	16	* GPIO interface (on NAND pins)
	17	* Serial interface
	18	* TFT 'interface converter'
	19	* PCMCIA interface logic
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
7acb706c	24	#include <linux/err.h>
1f192015	25	#include <linux/io.h>
5a0e3ad6	26	#include <linux/slab.h>
1f192015	27	#include <linux/irq.h>
7acb706c	28	#include <linux/clk.h>
1f192015 IM	29	#include <linux/platform_device.h>
	30	#include <linux/mfd/core.h>
	31	#include <linux/mfd/tmio.h>
	32	#include <linux/mfd/t7l66xb.h>
	33
	34	enum {
	35	T7L66XB_CELL_NAND,
	36	T7L66XB_CELL_MMC,
	37	};
	38
64e8867b IM	39	static const struct resource t7l66xb_mmc_resources[] = {
	40	{
	41	.start = 0x800,
	42	.end = 0x9ff,
	43	.flags = IORESOURCE_MEM,
	44	},
	45	{
	46	.start = IRQ_T7L66XB_MMC,
	47	.end = IRQ_T7L66XB_MMC,
	48	.flags = IORESOURCE_IRQ,
	49	},
	50	};
	51
1f192015 IM	52	#define SCR_REVID 0x08 /* b Revision ID */
	53	#define SCR_IMR 0x42 /* b Interrupt Mask */
	54	#define SCR_DEV_CTL 0xe0 /* b Device control */
	55	#define SCR_ISR 0xe1 /* b Interrupt Status */
	56	#define SCR_GPO_OC 0xf0 /* b GPO output control */
	57	#define SCR_GPO_OS 0xf1 /* b GPO output enable */
	58	#define SCR_GPI_S 0xf2 /* w GPI status */
	59	#define SCR_APDC 0xf8 /* b Active pullup down ctrl */
	60
	61	#define SCR_DEV_CTL_USB BIT(0) /* USB enable */
	62	#define SCR_DEV_CTL_MMC BIT(1) /* MMC enable */
	63
	64	/--------------------------------------------------------------------------/
	65
	66	struct t7l66xb {
	67	void __iomem *scr;
	68	/* Lock to protect registers requiring read/modify/write ops. */
9fe8c2df	69	raw_spinlock_t lock;
1f192015 IM	70
1f192015 IM	71	struct resource rscr;
7acb706c IM	72	struct clk *clk48m;
7acb706c IM	73	struct clk *clk32k;
1f192015 IM	74	int irq;
	75	int irq_base;
	76	};
	77
	78	/--------------------------------------------------------------------------/
	79
	80	static int t7l66xb_mmc_enable(struct platform_device *mmc)
	81	{
ed835136	82	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
1f192015 IM	83	unsigned long flags;
1f192015 IM	84	u8 dev_ctl;
b62d8dbe	85	int ret;
1f192015	86
b62d8dbe AY	87	ret = clk_prepare_enable(t7l66xb->clk32k);
	88	if (ret)
	89	return ret;
1f192015	90
9fe8c2df	91	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
1f192015 IM	92
	93	dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
	94	dev_ctl \|= SCR_DEV_CTL_MMC;
	95	tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
	96
9fe8c2df	97	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
1f192015	98
64e8867b IM	99	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
	100	t7l66xb_mmc_resources[0].start & 0xfffe);
	101
1f192015 IM	102	return 0;
	103	}
	104
	105	static int t7l66xb_mmc_disable(struct platform_device *mmc)
	106	{
ed835136	107	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
1f192015 IM	108	unsigned long flags;
	109	u8 dev_ctl;
	110
9fe8c2df	111	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
1f192015 IM	112
	113	dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
	114	dev_ctl &= ~SCR_DEV_CTL_MMC;
	115	tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
	116
9fe8c2df	117	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
1f192015	118
71d679b8	119	clk_disable_unprepare(t7l66xb->clk32k);
1f192015 IM	120
	121	return 0;
	122	}
	123
64e8867b IM	124	static void t7l66xb_mmc_pwr(struct platform_device *mmc, int state)
64e8867b IM	125	{
ed835136	126	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
64e8867b IM	127
	128	tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state);
	129	}
	130
	131	static void t7l66xb_mmc_clk_div(struct platform_device *mmc, int state)
	132	{
ed835136	133	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
64e8867b IM	134
	135	tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state);
	136	}
	137
1f192015 IM	138	/--------------------------------------------------------------------------/
1f192015 IM	139
4d3792e0	140	static struct tmio_mmc_data t7166xb_mmc_data = {
f0e46cc4	141	.hclk = 24000000,
64e8867b IM	142	.set_pwr = t7l66xb_mmc_pwr,
64e8867b IM	143	.set_clk_div = t7l66xb_mmc_clk_div,
1f192015 IM	144	};
1f192015 IM	145
3446d4bb	146	static const struct resource t7l66xb_nand_resources[] = {
1f192015 IM	147	{
	148	.start = 0xc00,
	149	.end = 0xc07,
	150	.flags = IORESOURCE_MEM,
	151	},
	152	{
	153	.start = 0x0100,
	154	.end = 0x01ff,
	155	.flags = IORESOURCE_MEM,
	156	},
	157	{
	158	.start = IRQ_T7L66XB_NAND,
	159	.end = IRQ_T7L66XB_NAND,
	160	.flags = IORESOURCE_IRQ,
	161	},
	162	};
	163
	164	static struct mfd_cell t7l66xb_cells[] = {
	165	[T7L66XB_CELL_MMC] = {
	166	.name = "tmio-mmc",
	167	.enable = t7l66xb_mmc_enable,
	168	.disable = t7l66xb_mmc_disable,
ec71974f SO	169	.platform_data = &t7166xb_mmc_data,
ec71974f SO	170	.pdata_size = sizeof(t7166xb_mmc_data),
1f192015 IM	171	.num_resources = ARRAY_SIZE(t7l66xb_mmc_resources),
	172	.resources = t7l66xb_mmc_resources,
	173	},
	174	[T7L66XB_CELL_NAND] = {
	175	.name = "tmio-nand",
	176	.num_resources = ARRAY_SIZE(t7l66xb_nand_resources),
	177	.resources = t7l66xb_nand_resources,
	178	},
	179	};
	180
	181	/--------------------------------------------------------------------------/
	182
	183	/* Handle the T7L66XB interrupt mux */
bd0b9ac4	184	static void t7l66xb_irq(struct irq_desc *desc)
1f192015	185	{
1e84aa44	186	struct t7l66xb *t7l66xb = irq_desc_get_handler_data(desc);
1f192015 IM	187	unsigned int isr;
	188	unsigned int i, irq_base;
	189
	190	irq_base = t7l66xb->irq_base;
	191
	192	while ((isr = tmio_ioread8(t7l66xb->scr + SCR_ISR) &
	193	~tmio_ioread8(t7l66xb->scr + SCR_IMR)))
	194	for (i = 0; i < T7L66XB_NR_IRQS; i++)
	195	if (isr & (1 << i))
	196	generic_handle_irq(irq_base + i);
	197	}
	198
a4e7fead	199	static void t7l66xb_irq_mask(struct irq_data *data)
1f192015	200	{
a4e7fead	201	struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
1f192015 IM	202	unsigned long flags;
	203	u8 imr;
	204
9fe8c2df	205	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
1f192015	206	imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
a4e7fead	207	imr \|= 1 << (data->irq - t7l66xb->irq_base);
1f192015	208	tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
9fe8c2df	209	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
1f192015 IM	210	}
1f192015 IM	211
a4e7fead	212	static void t7l66xb_irq_unmask(struct irq_data *data)
1f192015	213	{
a4e7fead	214	struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
1f192015 IM	215	unsigned long flags;
	216	u8 imr;
	217
9fe8c2df	218	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
1f192015	219	imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
a4e7fead	220	imr &= ~(1 << (data->irq - t7l66xb->irq_base));
1f192015	221	tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
9fe8c2df	222	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
1f192015 IM	223	}
	224
	225	static struct irq_chip t7l66xb_chip = {
a4e7fead MB	226	.name = "t7l66xb",
	227	.irq_ack = t7l66xb_irq_mask,
	228	.irq_mask = t7l66xb_irq_mask,
	229	.irq_unmask = t7l66xb_irq_unmask,
1f192015 IM	230	};
	231
	232	/--------------------------------------------------------------------------/
	233
	234	/* Install the IRQ handler */
	235	static void t7l66xb_attach_irq(struct platform_device *dev)
	236	{
	237	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	238	unsigned int irq, irq_base;
	239
	240	irq_base = t7l66xb->irq_base;
	241
	242	for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
d6f7ce9f	243	irq_set_chip_and_handler(irq, &t7l66xb_chip, handle_level_irq);
d5bb1221	244	irq_set_chip_data(irq, t7l66xb);
1f192015 IM	245	}
1f192015 IM	246
d5bb1221	247	irq_set_irq_type(t7l66xb->irq, IRQ_TYPE_EDGE_FALLING);
de7c9e0d	248	irq_set_chained_handler_and_data(t7l66xb->irq, t7l66xb_irq, t7l66xb);
1f192015 IM	249	}
	250
	251	static void t7l66xb_detach_irq(struct platform_device *dev)
	252	{
	253	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	254	unsigned int irq, irq_base;
	255
	256	irq_base = t7l66xb->irq_base;
	257
de7c9e0d	258	irq_set_chained_handler_and_data(t7l66xb->irq, NULL, NULL);
1f192015 IM	259
1f192015 IM	260	for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
d5bb1221 TG	261	irq_set_chip(irq, NULL);
d5bb1221 TG	262	irq_set_chip_data(irq, NULL);
1f192015 IM	263	}
	264	}
	265
	266	/--------------------------------------------------------------------------/
	267
	268	#ifdef CONFIG_PM
	269	static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state)
	270	{
7acb706c	271	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
334a41ce	272	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
1f192015 IM	273
	274	if (pdata && pdata->suspend)
	275	pdata->suspend(dev);
71d679b8	276	clk_disable_unprepare(t7l66xb->clk48m);
1f192015 IM	277
	278	return 0;
	279	}
	280
	281	static int t7l66xb_resume(struct platform_device *dev)
	282	{
7acb706c	283	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
334a41ce	284	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
b62d8dbe AY	285	int ret;
	286
	287	ret = clk_prepare_enable(t7l66xb->clk48m);
	288	if (ret)
	289	return ret;
1f192015 IM	290
	291	if (pdata && pdata->resume)
	292	pdata->resume(dev);
	293
64e8867b IM	294	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
	295	t7l66xb_mmc_resources[0].start & 0xfffe);
	296
1f192015 IM	297	return 0;
	298	}
	299	#else
	300	#define t7l66xb_suspend NULL
	301	#define t7l66xb_resume NULL
	302	#endif
	303
	304	/--------------------------------------------------------------------------/
	305
	306	static int t7l66xb_probe(struct platform_device *dev)
	307	{
334a41ce	308	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
1f192015 IM	309	struct t7l66xb *t7l66xb;
	310	struct resource iomem, rscr;
	311	int ret;
	312
78b7d84c	313	if (!pdata)
9ad285d6 SO	314	return -EINVAL;
9ad285d6 SO	315
1f192015 IM	316	iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
	317	if (!iomem)
	318	return -EINVAL;
	319
	320	t7l66xb = kzalloc(sizeof *t7l66xb, GFP_KERNEL);
	321	if (!t7l66xb)
	322	return -ENOMEM;
	323
9fe8c2df	324	raw_spin_lock_init(&t7l66xb->lock);
1f192015 IM	325
	326	platform_set_drvdata(dev, t7l66xb);
	327
	328	ret = platform_get_irq(dev, 0);
	329	if (ret >= 0)
	330	t7l66xb->irq = ret;
	331	else
	332	goto err_noirq;
	333
	334	t7l66xb->irq_base = pdata->irq_base;
	335
7acb706c IM	336	t7l66xb->clk32k = clk_get(&dev->dev, "CLK_CK32K");
	337	if (IS_ERR(t7l66xb->clk32k)) {
	338	ret = PTR_ERR(t7l66xb->clk32k);
	339	goto err_clk32k_get;
	340	}
	341
	342	t7l66xb->clk48m = clk_get(&dev->dev, "CLK_CK48M");
	343	if (IS_ERR(t7l66xb->clk48m)) {
	344	ret = PTR_ERR(t7l66xb->clk48m);
7acb706c IM	345	goto err_clk48m_get;
	346	}
	347
1f192015 IM	348	rscr = &t7l66xb->rscr;
	349	rscr->name = "t7l66xb-core";
	350	rscr->start = iomem->start;
	351	rscr->end = iomem->start + 0xff;
	352	rscr->flags = IORESOURCE_MEM;
	353
	354	ret = request_resource(iomem, rscr);
	355	if (ret)
	356	goto err_request_scr;
	357
c02e6a5f	358	t7l66xb->scr = ioremap(rscr->start, resource_size(rscr));
1f192015 IM	359	if (!t7l66xb->scr) {
	360	ret = -ENOMEM;
	361	goto err_ioremap;
	362	}
	363
b62d8dbe AY	364	ret = clk_prepare_enable(t7l66xb->clk48m);
	365	if (ret)
	366	goto err_clk_enable;
7acb706c	367
78b7d84c	368	if (pdata->enable)
1f192015 IM	369	pdata->enable(dev);
	370
	371	/* Mask all interrupts */
	372	tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR);
	373
	374	printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n",
	375	dev->name, tmio_ioread8(t7l66xb->scr + SCR_REVID),
	376	(unsigned long)iomem->start, t7l66xb->irq);
	377
	378	t7l66xb_attach_irq(dev);
	379
7dc00a0d SO	380	t7l66xb_cells[T7L66XB_CELL_NAND].platform_data = pdata->nand_data;
7dc00a0d SO	381	t7l66xb_cells[T7L66XB_CELL_NAND].pdata_size = sizeof(*pdata->nand_data);
8a4fbe01	382
56bf2bda SO	383	ret = mfd_add_devices(&dev->dev, dev->id,
56bf2bda SO	384	t7l66xb_cells, ARRAY_SIZE(t7l66xb_cells),
0848c94f	385	iomem, t7l66xb->irq_base, NULL);
1f192015 IM	386
	387	if (!ret)
	388	return 0;
	389
	390	t7l66xb_detach_irq(dev);
b62d8dbe AY	391	clk_disable_unprepare(t7l66xb->clk48m);
b62d8dbe AY	392	err_clk_enable:
1f192015 IM	393	iounmap(t7l66xb->scr);
	394	err_ioremap:
	395	release_resource(&t7l66xb->rscr);
1f192015	396	err_request_scr:
7acb706c IM	397	clk_put(t7l66xb->clk48m);
	398	err_clk48m_get:
	399	clk_put(t7l66xb->clk32k);
	400	err_clk32k_get:
	401	err_noirq:
0e820ab6	402	kfree(t7l66xb);
1f192015 IM	403	return ret;
	404	}
	405
	406	static int t7l66xb_remove(struct platform_device *dev)
	407	{
334a41ce	408	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
1f192015 IM	409	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	410	int ret;
	411
	412	ret = pdata->disable(dev);
71d679b8	413	clk_disable_unprepare(t7l66xb->clk48m);
7acb706c	414	clk_put(t7l66xb->clk48m);
71d679b8	415	clk_disable_unprepare(t7l66xb->clk32k);
d2d272a9	416	clk_put(t7l66xb->clk32k);
1f192015 IM	417	t7l66xb_detach_irq(dev);
	418	iounmap(t7l66xb->scr);
	419	release_resource(&t7l66xb->rscr);
56bf2bda	420	mfd_remove_devices(&dev->dev);
1f192015 IM	421	kfree(t7l66xb);
	422
	423	return ret;
	424
	425	}
	426
	427	static struct platform_driver t7l66xb_platform_driver = {
	428	.driver = {
	429	.name = "t7l66xb",
1f192015 IM	430	},
	431	.suspend = t7l66xb_suspend,
	432	.resume = t7l66xb_resume,
	433	.probe = t7l66xb_probe,
	434	.remove = t7l66xb_remove,
	435	};
	436
	437	/--------------------------------------------------------------------------/
	438
65349d60	439	module_platform_driver(t7l66xb_platform_driver);
1f192015 IM	440
	441	MODULE_DESCRIPTION("Toshiba T7L66XB core driver");
	442	MODULE_LICENSE("GPL v2");
	443	MODULE_AUTHOR("Ian Molton");
	444	MODULE_ALIAS("platform:t7l66xb");