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Commit | Line | Data |
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1f192015 IM |
1 | /* |
2 | * | |
3 | * Toshiba T7L66XB core mfd support | |
4 | * | |
5 | * Copyright (c) 2005, 2007, 2008 Ian Molton | |
6 | * Copyright (c) 2008 Dmitry Baryshkov | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * T7L66 features: | |
13 | * | |
14 | * Supported in this driver: | |
15 | * SD/MMC | |
16 | * SM/NAND flash controller | |
17 | * | |
18 | * As yet not supported | |
19 | * GPIO interface (on NAND pins) | |
20 | * Serial interface | |
21 | * TFT 'interface converter' | |
22 | * PCMCIA interface logic | |
23 | */ | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
7acb706c | 27 | #include <linux/err.h> |
1f192015 | 28 | #include <linux/io.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
1f192015 | 30 | #include <linux/irq.h> |
7acb706c | 31 | #include <linux/clk.h> |
1f192015 IM |
32 | #include <linux/platform_device.h> |
33 | #include <linux/mfd/core.h> | |
34 | #include <linux/mfd/tmio.h> | |
35 | #include <linux/mfd/t7l66xb.h> | |
36 | ||
37 | enum { | |
38 | T7L66XB_CELL_NAND, | |
39 | T7L66XB_CELL_MMC, | |
40 | }; | |
41 | ||
64e8867b IM |
42 | static const struct resource t7l66xb_mmc_resources[] = { |
43 | { | |
44 | .start = 0x800, | |
45 | .end = 0x9ff, | |
46 | .flags = IORESOURCE_MEM, | |
47 | }, | |
48 | { | |
49 | .start = IRQ_T7L66XB_MMC, | |
50 | .end = IRQ_T7L66XB_MMC, | |
51 | .flags = IORESOURCE_IRQ, | |
52 | }, | |
53 | }; | |
54 | ||
1f192015 IM |
55 | #define SCR_REVID 0x08 /* b Revision ID */ |
56 | #define SCR_IMR 0x42 /* b Interrupt Mask */ | |
57 | #define SCR_DEV_CTL 0xe0 /* b Device control */ | |
58 | #define SCR_ISR 0xe1 /* b Interrupt Status */ | |
59 | #define SCR_GPO_OC 0xf0 /* b GPO output control */ | |
60 | #define SCR_GPO_OS 0xf1 /* b GPO output enable */ | |
61 | #define SCR_GPI_S 0xf2 /* w GPI status */ | |
62 | #define SCR_APDC 0xf8 /* b Active pullup down ctrl */ | |
63 | ||
64 | #define SCR_DEV_CTL_USB BIT(0) /* USB enable */ | |
65 | #define SCR_DEV_CTL_MMC BIT(1) /* MMC enable */ | |
66 | ||
67 | /*--------------------------------------------------------------------------*/ | |
68 | ||
69 | struct t7l66xb { | |
70 | void __iomem *scr; | |
71 | /* Lock to protect registers requiring read/modify/write ops. */ | |
72 | spinlock_t lock; | |
73 | ||
74 | struct resource rscr; | |
7acb706c IM |
75 | struct clk *clk48m; |
76 | struct clk *clk32k; | |
1f192015 IM |
77 | int irq; |
78 | int irq_base; | |
79 | }; | |
80 | ||
81 | /*--------------------------------------------------------------------------*/ | |
82 | ||
83 | static int t7l66xb_mmc_enable(struct platform_device *mmc) | |
84 | { | |
85 | struct platform_device *dev = to_platform_device(mmc->dev.parent); | |
1f192015 IM |
86 | struct t7l66xb *t7l66xb = platform_get_drvdata(dev); |
87 | unsigned long flags; | |
88 | u8 dev_ctl; | |
89 | ||
7acb706c | 90 | clk_enable(t7l66xb->clk32k); |
1f192015 IM |
91 | |
92 | spin_lock_irqsave(&t7l66xb->lock, flags); | |
93 | ||
94 | dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL); | |
95 | dev_ctl |= SCR_DEV_CTL_MMC; | |
96 | tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL); | |
97 | ||
98 | spin_unlock_irqrestore(&t7l66xb->lock, flags); | |
99 | ||
64e8867b IM |
100 | tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0, |
101 | t7l66xb_mmc_resources[0].start & 0xfffe); | |
102 | ||
1f192015 IM |
103 | return 0; |
104 | } | |
105 | ||
106 | static int t7l66xb_mmc_disable(struct platform_device *mmc) | |
107 | { | |
108 | struct platform_device *dev = to_platform_device(mmc->dev.parent); | |
1f192015 IM |
109 | struct t7l66xb *t7l66xb = platform_get_drvdata(dev); |
110 | unsigned long flags; | |
111 | u8 dev_ctl; | |
112 | ||
113 | spin_lock_irqsave(&t7l66xb->lock, flags); | |
114 | ||
115 | dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL); | |
116 | dev_ctl &= ~SCR_DEV_CTL_MMC; | |
117 | tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL); | |
118 | ||
119 | spin_unlock_irqrestore(&t7l66xb->lock, flags); | |
120 | ||
7acb706c | 121 | clk_disable(t7l66xb->clk32k); |
1f192015 IM |
122 | |
123 | return 0; | |
124 | } | |
125 | ||
64e8867b IM |
126 | static void t7l66xb_mmc_pwr(struct platform_device *mmc, int state) |
127 | { | |
128 | struct platform_device *dev = to_platform_device(mmc->dev.parent); | |
129 | struct t7l66xb *t7l66xb = platform_get_drvdata(dev); | |
130 | ||
131 | tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state); | |
132 | } | |
133 | ||
134 | static void t7l66xb_mmc_clk_div(struct platform_device *mmc, int state) | |
135 | { | |
136 | struct platform_device *dev = to_platform_device(mmc->dev.parent); | |
137 | struct t7l66xb *t7l66xb = platform_get_drvdata(dev); | |
138 | ||
139 | tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state); | |
140 | } | |
141 | ||
1f192015 IM |
142 | /*--------------------------------------------------------------------------*/ |
143 | ||
4d3792e0 | 144 | static struct tmio_mmc_data t7166xb_mmc_data = { |
f0e46cc4 | 145 | .hclk = 24000000, |
64e8867b IM |
146 | .set_pwr = t7l66xb_mmc_pwr, |
147 | .set_clk_div = t7l66xb_mmc_clk_div, | |
1f192015 IM |
148 | }; |
149 | ||
3446d4bb | 150 | static const struct resource t7l66xb_nand_resources[] = { |
1f192015 IM |
151 | { |
152 | .start = 0xc00, | |
153 | .end = 0xc07, | |
154 | .flags = IORESOURCE_MEM, | |
155 | }, | |
156 | { | |
157 | .start = 0x0100, | |
158 | .end = 0x01ff, | |
159 | .flags = IORESOURCE_MEM, | |
160 | }, | |
161 | { | |
162 | .start = IRQ_T7L66XB_NAND, | |
163 | .end = IRQ_T7L66XB_NAND, | |
164 | .flags = IORESOURCE_IRQ, | |
165 | }, | |
166 | }; | |
167 | ||
168 | static struct mfd_cell t7l66xb_cells[] = { | |
169 | [T7L66XB_CELL_MMC] = { | |
170 | .name = "tmio-mmc", | |
171 | .enable = t7l66xb_mmc_enable, | |
172 | .disable = t7l66xb_mmc_disable, | |
4f95bf40 | 173 | .mfd_data = &t7166xb_mmc_data, |
1f192015 IM |
174 | .num_resources = ARRAY_SIZE(t7l66xb_mmc_resources), |
175 | .resources = t7l66xb_mmc_resources, | |
176 | }, | |
177 | [T7L66XB_CELL_NAND] = { | |
178 | .name = "tmio-nand", | |
179 | .num_resources = ARRAY_SIZE(t7l66xb_nand_resources), | |
180 | .resources = t7l66xb_nand_resources, | |
181 | }, | |
182 | }; | |
183 | ||
184 | /*--------------------------------------------------------------------------*/ | |
185 | ||
186 | /* Handle the T7L66XB interrupt mux */ | |
187 | static void t7l66xb_irq(unsigned int irq, struct irq_desc *desc) | |
188 | { | |
d5bb1221 | 189 | struct t7l66xb *t7l66xb = irq_get_handler_data(irq); |
1f192015 IM |
190 | unsigned int isr; |
191 | unsigned int i, irq_base; | |
192 | ||
193 | irq_base = t7l66xb->irq_base; | |
194 | ||
195 | while ((isr = tmio_ioread8(t7l66xb->scr + SCR_ISR) & | |
196 | ~tmio_ioread8(t7l66xb->scr + SCR_IMR))) | |
197 | for (i = 0; i < T7L66XB_NR_IRQS; i++) | |
198 | if (isr & (1 << i)) | |
199 | generic_handle_irq(irq_base + i); | |
200 | } | |
201 | ||
a4e7fead | 202 | static void t7l66xb_irq_mask(struct irq_data *data) |
1f192015 | 203 | { |
a4e7fead | 204 | struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data); |
1f192015 IM |
205 | unsigned long flags; |
206 | u8 imr; | |
207 | ||
208 | spin_lock_irqsave(&t7l66xb->lock, flags); | |
209 | imr = tmio_ioread8(t7l66xb->scr + SCR_IMR); | |
a4e7fead | 210 | imr |= 1 << (data->irq - t7l66xb->irq_base); |
1f192015 IM |
211 | tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR); |
212 | spin_unlock_irqrestore(&t7l66xb->lock, flags); | |
213 | } | |
214 | ||
a4e7fead | 215 | static void t7l66xb_irq_unmask(struct irq_data *data) |
1f192015 | 216 | { |
a4e7fead | 217 | struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data); |
1f192015 IM |
218 | unsigned long flags; |
219 | u8 imr; | |
220 | ||
221 | spin_lock_irqsave(&t7l66xb->lock, flags); | |
222 | imr = tmio_ioread8(t7l66xb->scr + SCR_IMR); | |
a4e7fead | 223 | imr &= ~(1 << (data->irq - t7l66xb->irq_base)); |
1f192015 IM |
224 | tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR); |
225 | spin_unlock_irqrestore(&t7l66xb->lock, flags); | |
226 | } | |
227 | ||
228 | static struct irq_chip t7l66xb_chip = { | |
a4e7fead MB |
229 | .name = "t7l66xb", |
230 | .irq_ack = t7l66xb_irq_mask, | |
231 | .irq_mask = t7l66xb_irq_mask, | |
232 | .irq_unmask = t7l66xb_irq_unmask, | |
1f192015 IM |
233 | }; |
234 | ||
235 | /*--------------------------------------------------------------------------*/ | |
236 | ||
237 | /* Install the IRQ handler */ | |
238 | static void t7l66xb_attach_irq(struct platform_device *dev) | |
239 | { | |
240 | struct t7l66xb *t7l66xb = platform_get_drvdata(dev); | |
241 | unsigned int irq, irq_base; | |
242 | ||
243 | irq_base = t7l66xb->irq_base; | |
244 | ||
245 | for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) { | |
d6f7ce9f | 246 | irq_set_chip_and_handler(irq, &t7l66xb_chip, handle_level_irq); |
d5bb1221 | 247 | irq_set_chip_data(irq, t7l66xb); |
1f192015 IM |
248 | #ifdef CONFIG_ARM |
249 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
250 | #endif | |
251 | } | |
252 | ||
d5bb1221 TG |
253 | irq_set_irq_type(t7l66xb->irq, IRQ_TYPE_EDGE_FALLING); |
254 | irq_set_handler_data(t7l66xb->irq, t7l66xb); | |
255 | irq_set_chained_handler(t7l66xb->irq, t7l66xb_irq); | |
1f192015 IM |
256 | } |
257 | ||
258 | static void t7l66xb_detach_irq(struct platform_device *dev) | |
259 | { | |
260 | struct t7l66xb *t7l66xb = platform_get_drvdata(dev); | |
261 | unsigned int irq, irq_base; | |
262 | ||
263 | irq_base = t7l66xb->irq_base; | |
264 | ||
d5bb1221 TG |
265 | irq_set_chained_handler(t7l66xb->irq, NULL); |
266 | irq_set_handler_data(t7l66xb->irq, NULL); | |
1f192015 IM |
267 | |
268 | for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) { | |
269 | #ifdef CONFIG_ARM | |
270 | set_irq_flags(irq, 0); | |
271 | #endif | |
d5bb1221 TG |
272 | irq_set_chip(irq, NULL); |
273 | irq_set_chip_data(irq, NULL); | |
1f192015 IM |
274 | } |
275 | } | |
276 | ||
277 | /*--------------------------------------------------------------------------*/ | |
278 | ||
279 | #ifdef CONFIG_PM | |
280 | static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state) | |
281 | { | |
7acb706c | 282 | struct t7l66xb *t7l66xb = platform_get_drvdata(dev); |
1f192015 IM |
283 | struct t7l66xb_platform_data *pdata = dev->dev.platform_data; |
284 | ||
285 | if (pdata && pdata->suspend) | |
286 | pdata->suspend(dev); | |
7acb706c | 287 | clk_disable(t7l66xb->clk48m); |
1f192015 IM |
288 | |
289 | return 0; | |
290 | } | |
291 | ||
292 | static int t7l66xb_resume(struct platform_device *dev) | |
293 | { | |
7acb706c | 294 | struct t7l66xb *t7l66xb = platform_get_drvdata(dev); |
1f192015 IM |
295 | struct t7l66xb_platform_data *pdata = dev->dev.platform_data; |
296 | ||
7acb706c | 297 | clk_enable(t7l66xb->clk48m); |
1f192015 IM |
298 | if (pdata && pdata->resume) |
299 | pdata->resume(dev); | |
300 | ||
64e8867b IM |
301 | tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0, |
302 | t7l66xb_mmc_resources[0].start & 0xfffe); | |
303 | ||
1f192015 IM |
304 | return 0; |
305 | } | |
306 | #else | |
307 | #define t7l66xb_suspend NULL | |
308 | #define t7l66xb_resume NULL | |
309 | #endif | |
310 | ||
311 | /*--------------------------------------------------------------------------*/ | |
312 | ||
313 | static int t7l66xb_probe(struct platform_device *dev) | |
314 | { | |
315 | struct t7l66xb_platform_data *pdata = dev->dev.platform_data; | |
316 | struct t7l66xb *t7l66xb; | |
317 | struct resource *iomem, *rscr; | |
318 | int ret; | |
319 | ||
9ad285d6 SO |
320 | if (pdata == NULL) |
321 | return -EINVAL; | |
322 | ||
1f192015 IM |
323 | iomem = platform_get_resource(dev, IORESOURCE_MEM, 0); |
324 | if (!iomem) | |
325 | return -EINVAL; | |
326 | ||
327 | t7l66xb = kzalloc(sizeof *t7l66xb, GFP_KERNEL); | |
328 | if (!t7l66xb) | |
329 | return -ENOMEM; | |
330 | ||
331 | spin_lock_init(&t7l66xb->lock); | |
332 | ||
333 | platform_set_drvdata(dev, t7l66xb); | |
334 | ||
335 | ret = platform_get_irq(dev, 0); | |
336 | if (ret >= 0) | |
337 | t7l66xb->irq = ret; | |
338 | else | |
339 | goto err_noirq; | |
340 | ||
341 | t7l66xb->irq_base = pdata->irq_base; | |
342 | ||
7acb706c IM |
343 | t7l66xb->clk32k = clk_get(&dev->dev, "CLK_CK32K"); |
344 | if (IS_ERR(t7l66xb->clk32k)) { | |
345 | ret = PTR_ERR(t7l66xb->clk32k); | |
346 | goto err_clk32k_get; | |
347 | } | |
348 | ||
349 | t7l66xb->clk48m = clk_get(&dev->dev, "CLK_CK48M"); | |
350 | if (IS_ERR(t7l66xb->clk48m)) { | |
351 | ret = PTR_ERR(t7l66xb->clk48m); | |
7acb706c IM |
352 | goto err_clk48m_get; |
353 | } | |
354 | ||
1f192015 IM |
355 | rscr = &t7l66xb->rscr; |
356 | rscr->name = "t7l66xb-core"; | |
357 | rscr->start = iomem->start; | |
358 | rscr->end = iomem->start + 0xff; | |
359 | rscr->flags = IORESOURCE_MEM; | |
360 | ||
361 | ret = request_resource(iomem, rscr); | |
362 | if (ret) | |
363 | goto err_request_scr; | |
364 | ||
c02e6a5f | 365 | t7l66xb->scr = ioremap(rscr->start, resource_size(rscr)); |
1f192015 IM |
366 | if (!t7l66xb->scr) { |
367 | ret = -ENOMEM; | |
368 | goto err_ioremap; | |
369 | } | |
370 | ||
7acb706c IM |
371 | clk_enable(t7l66xb->clk48m); |
372 | ||
1f192015 IM |
373 | if (pdata && pdata->enable) |
374 | pdata->enable(dev); | |
375 | ||
376 | /* Mask all interrupts */ | |
377 | tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR); | |
378 | ||
379 | printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n", | |
380 | dev->name, tmio_ioread8(t7l66xb->scr + SCR_REVID), | |
381 | (unsigned long)iomem->start, t7l66xb->irq); | |
382 | ||
383 | t7l66xb_attach_irq(dev); | |
384 | ||
d9d01f4b | 385 | t7l66xb_cells[T7L66XB_CELL_NAND].mfd_data = pdata->nand_data; |
8a4fbe01 | 386 | |
56bf2bda SO |
387 | ret = mfd_add_devices(&dev->dev, dev->id, |
388 | t7l66xb_cells, ARRAY_SIZE(t7l66xb_cells), | |
389 | iomem, t7l66xb->irq_base); | |
1f192015 IM |
390 | |
391 | if (!ret) | |
392 | return 0; | |
393 | ||
394 | t7l66xb_detach_irq(dev); | |
395 | iounmap(t7l66xb->scr); | |
396 | err_ioremap: | |
397 | release_resource(&t7l66xb->rscr); | |
1f192015 | 398 | err_request_scr: |
7acb706c IM |
399 | clk_put(t7l66xb->clk48m); |
400 | err_clk48m_get: | |
401 | clk_put(t7l66xb->clk32k); | |
402 | err_clk32k_get: | |
403 | err_noirq: | |
0e820ab6 | 404 | kfree(t7l66xb); |
1f192015 IM |
405 | return ret; |
406 | } | |
407 | ||
408 | static int t7l66xb_remove(struct platform_device *dev) | |
409 | { | |
410 | struct t7l66xb_platform_data *pdata = dev->dev.platform_data; | |
411 | struct t7l66xb *t7l66xb = platform_get_drvdata(dev); | |
412 | int ret; | |
413 | ||
414 | ret = pdata->disable(dev); | |
7acb706c IM |
415 | clk_disable(t7l66xb->clk48m); |
416 | clk_put(t7l66xb->clk48m); | |
d2d272a9 AL |
417 | clk_disable(t7l66xb->clk32k); |
418 | clk_put(t7l66xb->clk32k); | |
1f192015 IM |
419 | t7l66xb_detach_irq(dev); |
420 | iounmap(t7l66xb->scr); | |
421 | release_resource(&t7l66xb->rscr); | |
56bf2bda | 422 | mfd_remove_devices(&dev->dev); |
1f192015 IM |
423 | platform_set_drvdata(dev, NULL); |
424 | kfree(t7l66xb); | |
425 | ||
426 | return ret; | |
427 | ||
428 | } | |
429 | ||
430 | static struct platform_driver t7l66xb_platform_driver = { | |
431 | .driver = { | |
432 | .name = "t7l66xb", | |
433 | .owner = THIS_MODULE, | |
434 | }, | |
435 | .suspend = t7l66xb_suspend, | |
436 | .resume = t7l66xb_resume, | |
437 | .probe = t7l66xb_probe, | |
438 | .remove = t7l66xb_remove, | |
439 | }; | |
440 | ||
441 | /*--------------------------------------------------------------------------*/ | |
442 | ||
443 | static int __init t7l66xb_init(void) | |
444 | { | |
445 | int retval = 0; | |
446 | ||
447 | retval = platform_driver_register(&t7l66xb_platform_driver); | |
448 | return retval; | |
449 | } | |
450 | ||
451 | static void __exit t7l66xb_exit(void) | |
452 | { | |
453 | platform_driver_unregister(&t7l66xb_platform_driver); | |
454 | } | |
455 | ||
456 | module_init(t7l66xb_init); | |
457 | module_exit(t7l66xb_exit); | |
458 | ||
459 | MODULE_DESCRIPTION("Toshiba T7L66XB core driver"); | |
460 | MODULE_LICENSE("GPL v2"); | |
461 | MODULE_AUTHOR("Ian Molton"); | |
462 | MODULE_ALIAS("platform:t7l66xb"); |