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d6315949 DB |
1 | /* |
2 | * Toshiba TC6393XB SoC support | |
3 | * | |
4 | * Copyright(c) 2005-2006 Chris Humbert | |
5 | * Copyright(c) 2005 Dirk Opfer | |
6 | * Copyright(c) 2005 Ian Molton <spyro@f2s.com> | |
7 | * Copyright(c) 2007 Dmitry Baryshkov | |
8 | * | |
9 | * Based on code written by Sharp/Lineo for 2.4 kernels | |
10 | * Based on locomo.c | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/platform_device.h> | |
d6315949 | 22 | #include <linux/clk.h> |
25d6cbd8 | 23 | #include <linux/err.h> |
f024ff10 DB |
24 | #include <linux/mfd/core.h> |
25 | #include <linux/mfd/tmio.h> | |
d6315949 DB |
26 | #include <linux/mfd/tc6393xb.h> |
27 | #include <linux/gpio.h> | |
28 | ||
29 | #define SCR_REVID 0x08 /* b Revision ID */ | |
30 | #define SCR_ISR 0x50 /* b Interrupt Status */ | |
31 | #define SCR_IMR 0x52 /* b Interrupt Mask */ | |
32 | #define SCR_IRR 0x54 /* b Interrupt Routing */ | |
33 | #define SCR_GPER 0x60 /* w GP Enable */ | |
34 | #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */ | |
35 | #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */ | |
36 | #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */ | |
37 | #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */ | |
38 | #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */ | |
39 | #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */ | |
40 | #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */ | |
41 | #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */ | |
42 | #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */ | |
43 | #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */ | |
44 | #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */ | |
45 | #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */ | |
46 | #define SCR_CCR 0x98 /* w Clock Control */ | |
47 | #define SCR_PLL2CR 0x9a /* w PLL2 Control */ | |
48 | #define SCR_PLL1CR 0x9c /* l PLL1 Control */ | |
49 | #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */ | |
50 | #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */ | |
51 | #define SCR_FER 0xe0 /* b Function Enable */ | |
52 | #define SCR_MCR 0xe4 /* w Mode Control */ | |
53 | #define SCR_CONFIG 0xfc /* b Configuration Control */ | |
54 | #define SCR_DEBUG 0xff /* b Debug */ | |
55 | ||
56 | #define SCR_CCR_CK32K BIT(0) | |
57 | #define SCR_CCR_USBCK BIT(1) | |
58 | #define SCR_CCR_UNK1 BIT(4) | |
59 | #define SCR_CCR_MCLK_MASK (7 << 8) | |
60 | #define SCR_CCR_MCLK_OFF (0 << 8) | |
61 | #define SCR_CCR_MCLK_12 (1 << 8) | |
62 | #define SCR_CCR_MCLK_24 (2 << 8) | |
63 | #define SCR_CCR_MCLK_48 (3 << 8) | |
64 | #define SCR_CCR_HCLK_MASK (3 << 12) | |
65 | #define SCR_CCR_HCLK_24 (0 << 12) | |
66 | #define SCR_CCR_HCLK_48 (1 << 12) | |
67 | ||
68 | #define SCR_FER_USBEN BIT(0) /* USB host enable */ | |
69 | #define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */ | |
70 | #define SCR_FER_SLCDEN BIT(2) /* SLCD enable */ | |
71 | ||
72 | #define SCR_MCR_RDY_MASK (3 << 0) | |
73 | #define SCR_MCR_RDY_OPENDRAIN (0 << 0) | |
74 | #define SCR_MCR_RDY_TRISTATE (1 << 0) | |
75 | #define SCR_MCR_RDY_PUSHPULL (2 << 0) | |
76 | #define SCR_MCR_RDY_UNK BIT(2) | |
77 | #define SCR_MCR_RDY_EN BIT(3) | |
78 | #define SCR_MCR_INT_MASK (3 << 4) | |
79 | #define SCR_MCR_INT_OPENDRAIN (0 << 4) | |
80 | #define SCR_MCR_INT_TRISTATE (1 << 4) | |
81 | #define SCR_MCR_INT_PUSHPULL (2 << 4) | |
82 | #define SCR_MCR_INT_UNK BIT(6) | |
83 | #define SCR_MCR_INT_EN BIT(7) | |
84 | /* bits 8 - 16 are unknown */ | |
85 | ||
86 | #define TC_GPIO_BIT(i) (1 << (i & 0x7)) | |
87 | ||
88 | /*--------------------------------------------------------------------------*/ | |
89 | ||
90 | struct tc6393xb { | |
91 | void __iomem *scr; | |
92 | ||
93 | struct gpio_chip gpio; | |
94 | ||
95 | struct clk *clk; /* 3,6 Mhz */ | |
96 | ||
97 | spinlock_t lock; /* protects RMW cycles */ | |
98 | ||
99 | struct { | |
100 | u8 fer; | |
101 | u16 ccr; | |
102 | u8 gpi_bcr[3]; | |
103 | u8 gpo_dsr[3]; | |
104 | u8 gpo_doecr[3]; | |
105 | } suspend_state; | |
106 | ||
107 | struct resource rscr; | |
108 | struct resource *iomem; | |
109 | int irq; | |
110 | int irq_base; | |
111 | }; | |
112 | ||
f024ff10 DB |
113 | enum { |
114 | TC6393XB_CELL_NAND, | |
25d6cbd8 | 115 | TC6393XB_CELL_MMC, |
f024ff10 DB |
116 | }; |
117 | ||
118 | /*--------------------------------------------------------------------------*/ | |
119 | ||
120 | static int tc6393xb_nand_enable(struct platform_device *nand) | |
121 | { | |
122 | struct platform_device *dev = to_platform_device(nand->dev.parent); | |
123 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
124 | unsigned long flags; | |
125 | ||
126 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
127 | ||
128 | /* SMD buffer on */ | |
129 | dev_dbg(&dev->dev, "SMD buffer on\n"); | |
25d6cbd8 | 130 | tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1)); |
f024ff10 DB |
131 | |
132 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
137 | static struct resource __devinitdata tc6393xb_nand_resources[] = { | |
138 | { | |
25d6cbd8 IM |
139 | .start = 0x1000, |
140 | .end = 0x1007, | |
f024ff10 DB |
141 | .flags = IORESOURCE_MEM, |
142 | }, | |
143 | { | |
25d6cbd8 IM |
144 | .start = 0x0100, |
145 | .end = 0x01ff, | |
f024ff10 DB |
146 | .flags = IORESOURCE_MEM, |
147 | }, | |
148 | { | |
f024ff10 DB |
149 | .start = IRQ_TC6393_NAND, |
150 | .end = IRQ_TC6393_NAND, | |
151 | .flags = IORESOURCE_IRQ, | |
152 | }, | |
153 | }; | |
154 | ||
25d6cbd8 IM |
155 | static struct resource __devinitdata tc6393xb_mmc_resources[] = { |
156 | { | |
157 | .start = 0x800, | |
158 | .end = 0x9ff, | |
159 | .flags = IORESOURCE_MEM, | |
160 | }, | |
161 | { | |
162 | .start = 0x200, | |
163 | .end = 0x2ff, | |
164 | .flags = IORESOURCE_MEM, | |
165 | }, | |
166 | { | |
167 | .start = IRQ_TC6393_MMC, | |
168 | .end = IRQ_TC6393_MMC, | |
169 | .flags = IORESOURCE_IRQ, | |
170 | }, | |
171 | }; | |
172 | ||
f024ff10 DB |
173 | static struct mfd_cell __devinitdata tc6393xb_cells[] = { |
174 | [TC6393XB_CELL_NAND] = { | |
175 | .name = "tmio-nand", | |
176 | .enable = tc6393xb_nand_enable, | |
177 | .num_resources = ARRAY_SIZE(tc6393xb_nand_resources), | |
178 | .resources = tc6393xb_nand_resources, | |
179 | }, | |
25d6cbd8 IM |
180 | [TC6393XB_CELL_MMC] = { |
181 | .name = "tmio-mmc", | |
182 | .num_resources = ARRAY_SIZE(tc6393xb_mmc_resources), | |
183 | .resources = tc6393xb_mmc_resources, | |
184 | }, | |
f024ff10 DB |
185 | }; |
186 | ||
d6315949 DB |
187 | /*--------------------------------------------------------------------------*/ |
188 | ||
189 | static int tc6393xb_gpio_get(struct gpio_chip *chip, | |
190 | unsigned offset) | |
191 | { | |
192 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
193 | ||
194 | /* XXX: does dsr also represent inputs? */ | |
25d6cbd8 | 195 | return tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8)) |
d6315949 DB |
196 | & TC_GPIO_BIT(offset); |
197 | } | |
198 | ||
199 | static void __tc6393xb_gpio_set(struct gpio_chip *chip, | |
200 | unsigned offset, int value) | |
201 | { | |
202 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
203 | u8 dsr; | |
204 | ||
25d6cbd8 | 205 | dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8)); |
d6315949 DB |
206 | if (value) |
207 | dsr |= TC_GPIO_BIT(offset); | |
208 | else | |
209 | dsr &= ~TC_GPIO_BIT(offset); | |
210 | ||
25d6cbd8 | 211 | tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8)); |
d6315949 DB |
212 | } |
213 | ||
214 | static void tc6393xb_gpio_set(struct gpio_chip *chip, | |
215 | unsigned offset, int value) | |
216 | { | |
217 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
218 | unsigned long flags; | |
219 | ||
220 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
221 | ||
222 | __tc6393xb_gpio_set(chip, offset, value); | |
223 | ||
224 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
225 | } | |
226 | ||
227 | static int tc6393xb_gpio_direction_input(struct gpio_chip *chip, | |
228 | unsigned offset) | |
229 | { | |
230 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
231 | unsigned long flags; | |
232 | u8 doecr; | |
233 | ||
234 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
235 | ||
25d6cbd8 | 236 | doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); |
d6315949 | 237 | doecr &= ~TC_GPIO_BIT(offset); |
25d6cbd8 | 238 | tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); |
d6315949 DB |
239 | |
240 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | static int tc6393xb_gpio_direction_output(struct gpio_chip *chip, | |
246 | unsigned offset, int value) | |
247 | { | |
248 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
249 | unsigned long flags; | |
250 | u8 doecr; | |
251 | ||
252 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
253 | ||
254 | __tc6393xb_gpio_set(chip, offset, value); | |
255 | ||
25d6cbd8 | 256 | doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); |
d6315949 | 257 | doecr |= TC_GPIO_BIT(offset); |
25d6cbd8 | 258 | tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); |
d6315949 DB |
259 | |
260 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base) | |
266 | { | |
267 | tc6393xb->gpio.label = "tc6393xb"; | |
268 | tc6393xb->gpio.base = gpio_base; | |
269 | tc6393xb->gpio.ngpio = 16; | |
270 | tc6393xb->gpio.set = tc6393xb_gpio_set; | |
271 | tc6393xb->gpio.get = tc6393xb_gpio_get; | |
272 | tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input; | |
273 | tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output; | |
274 | ||
275 | return gpiochip_add(&tc6393xb->gpio); | |
276 | } | |
277 | ||
278 | /*--------------------------------------------------------------------------*/ | |
279 | ||
280 | static void | |
281 | tc6393xb_irq(unsigned int irq, struct irq_desc *desc) | |
282 | { | |
283 | struct tc6393xb *tc6393xb = get_irq_data(irq); | |
284 | unsigned int isr; | |
285 | unsigned int i, irq_base; | |
286 | ||
287 | irq_base = tc6393xb->irq_base; | |
288 | ||
25d6cbd8 IM |
289 | while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) & |
290 | ~tmio_ioread8(tc6393xb->scr + SCR_IMR))) | |
d6315949 DB |
291 | for (i = 0; i < TC6393XB_NR_IRQS; i++) { |
292 | if (isr & (1 << i)) | |
293 | generic_handle_irq(irq_base + i); | |
294 | } | |
295 | } | |
296 | ||
297 | static void tc6393xb_irq_ack(unsigned int irq) | |
298 | { | |
299 | } | |
300 | ||
301 | static void tc6393xb_irq_mask(unsigned int irq) | |
302 | { | |
303 | struct tc6393xb *tc6393xb = get_irq_chip_data(irq); | |
304 | unsigned long flags; | |
305 | u8 imr; | |
306 | ||
307 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
25d6cbd8 | 308 | imr = tmio_ioread8(tc6393xb->scr + SCR_IMR); |
d6315949 | 309 | imr |= 1 << (irq - tc6393xb->irq_base); |
25d6cbd8 | 310 | tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR); |
d6315949 DB |
311 | spin_unlock_irqrestore(&tc6393xb->lock, flags); |
312 | } | |
313 | ||
314 | static void tc6393xb_irq_unmask(unsigned int irq) | |
315 | { | |
316 | struct tc6393xb *tc6393xb = get_irq_chip_data(irq); | |
317 | unsigned long flags; | |
318 | u8 imr; | |
319 | ||
320 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
25d6cbd8 | 321 | imr = tmio_ioread8(tc6393xb->scr + SCR_IMR); |
d6315949 | 322 | imr &= ~(1 << (irq - tc6393xb->irq_base)); |
25d6cbd8 | 323 | tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR); |
d6315949 DB |
324 | spin_unlock_irqrestore(&tc6393xb->lock, flags); |
325 | } | |
326 | ||
327 | static struct irq_chip tc6393xb_chip = { | |
328 | .name = "tc6393xb", | |
329 | .ack = tc6393xb_irq_ack, | |
330 | .mask = tc6393xb_irq_mask, | |
331 | .unmask = tc6393xb_irq_unmask, | |
332 | }; | |
333 | ||
334 | static void tc6393xb_attach_irq(struct platform_device *dev) | |
335 | { | |
336 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
337 | unsigned int irq, irq_base; | |
338 | ||
339 | irq_base = tc6393xb->irq_base; | |
340 | ||
341 | for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) { | |
342 | set_irq_chip(irq, &tc6393xb_chip); | |
343 | set_irq_chip_data(irq, tc6393xb); | |
344 | set_irq_handler(irq, handle_edge_irq); | |
345 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
346 | } | |
347 | ||
6cab4860 | 348 | set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING); |
d6315949 DB |
349 | set_irq_data(tc6393xb->irq, tc6393xb); |
350 | set_irq_chained_handler(tc6393xb->irq, tc6393xb_irq); | |
351 | } | |
352 | ||
353 | static void tc6393xb_detach_irq(struct platform_device *dev) | |
354 | { | |
355 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
356 | unsigned int irq, irq_base; | |
357 | ||
358 | set_irq_chained_handler(tc6393xb->irq, NULL); | |
359 | set_irq_data(tc6393xb->irq, NULL); | |
360 | ||
361 | irq_base = tc6393xb->irq_base; | |
362 | ||
363 | for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) { | |
364 | set_irq_flags(irq, 0); | |
365 | set_irq_chip(irq, NULL); | |
366 | set_irq_chip_data(irq, NULL); | |
367 | } | |
368 | } | |
369 | ||
370 | /*--------------------------------------------------------------------------*/ | |
371 | ||
d6315949 DB |
372 | static int __devinit tc6393xb_probe(struct platform_device *dev) |
373 | { | |
374 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
375 | struct tc6393xb *tc6393xb; | |
25d6cbd8 IM |
376 | struct resource *iomem, *rscr; |
377 | int ret, temp; | |
d6315949 DB |
378 | |
379 | iomem = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
380 | if (!iomem) | |
381 | return -EINVAL; | |
382 | ||
383 | tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL); | |
384 | if (!tc6393xb) { | |
25d6cbd8 | 385 | ret = -ENOMEM; |
d6315949 DB |
386 | goto err_kzalloc; |
387 | } | |
388 | ||
389 | spin_lock_init(&tc6393xb->lock); | |
390 | ||
391 | platform_set_drvdata(dev, tc6393xb); | |
25d6cbd8 IM |
392 | |
393 | ret = platform_get_irq(dev, 0); | |
394 | if (ret >= 0) | |
395 | tc6393xb->irq = ret; | |
396 | else | |
397 | goto err_noirq; | |
398 | ||
d6315949 | 399 | tc6393xb->iomem = iomem; |
d6315949 DB |
400 | tc6393xb->irq_base = tcpd->irq_base; |
401 | ||
25d6cbd8 | 402 | tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI"); |
d6315949 | 403 | if (IS_ERR(tc6393xb->clk)) { |
25d6cbd8 | 404 | ret = PTR_ERR(tc6393xb->clk); |
d6315949 DB |
405 | goto err_clk_get; |
406 | } | |
407 | ||
408 | rscr = &tc6393xb->rscr; | |
409 | rscr->name = "tc6393xb-core"; | |
410 | rscr->start = iomem->start; | |
411 | rscr->end = iomem->start + 0xff; | |
412 | rscr->flags = IORESOURCE_MEM; | |
413 | ||
25d6cbd8 IM |
414 | ret = request_resource(iomem, rscr); |
415 | if (ret) | |
d6315949 DB |
416 | goto err_request_scr; |
417 | ||
418 | tc6393xb->scr = ioremap(rscr->start, rscr->end - rscr->start + 1); | |
419 | if (!tc6393xb->scr) { | |
25d6cbd8 | 420 | ret = -ENOMEM; |
d6315949 DB |
421 | goto err_ioremap; |
422 | } | |
423 | ||
25d6cbd8 IM |
424 | ret = clk_enable(tc6393xb->clk); |
425 | if (ret) | |
d6315949 DB |
426 | goto err_clk_enable; |
427 | ||
25d6cbd8 IM |
428 | ret = tcpd->enable(dev); |
429 | if (ret) | |
d6315949 DB |
430 | goto err_enable; |
431 | ||
f98a0bd0 DB |
432 | iowrite8(0, tc6393xb->scr + SCR_FER); |
433 | iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR); | |
434 | iowrite16(SCR_CCR_UNK1 | SCR_CCR_HCLK_48, | |
435 | tc6393xb->scr + SCR_CCR); | |
436 | iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN | | |
437 | SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN | | |
438 | BIT(15), tc6393xb->scr + SCR_MCR); | |
439 | iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER); | |
440 | iowrite8(0, tc6393xb->scr + SCR_IRR); | |
441 | iowrite8(0xbf, tc6393xb->scr + SCR_IMR); | |
d6315949 DB |
442 | |
443 | printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n", | |
25d6cbd8 | 444 | tmio_ioread8(tc6393xb->scr + SCR_REVID), |
d6315949 DB |
445 | (unsigned long) iomem->start, tc6393xb->irq); |
446 | ||
447 | tc6393xb->gpio.base = -1; | |
448 | ||
449 | if (tcpd->gpio_base >= 0) { | |
25d6cbd8 IM |
450 | ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base); |
451 | if (ret) | |
d6315949 DB |
452 | goto err_gpio_add; |
453 | } | |
454 | ||
25d6cbd8 | 455 | tc6393xb_attach_irq(dev); |
d6315949 | 456 | |
1c1b6ffc DB |
457 | if (tcpd->setup) { |
458 | ret = tcpd->setup(dev); | |
459 | if (ret) | |
460 | goto err_setup; | |
461 | } | |
462 | ||
f024ff10 | 463 | tc6393xb_cells[TC6393XB_CELL_NAND].driver_data = tcpd->nand_data; |
56edb58b MR |
464 | tc6393xb_cells[TC6393XB_CELL_NAND].platform_data = |
465 | &tc6393xb_cells[TC6393XB_CELL_NAND]; | |
466 | tc6393xb_cells[TC6393XB_CELL_NAND].data_size = | |
467 | sizeof(tc6393xb_cells[TC6393XB_CELL_NAND]); | |
25d6cbd8 IM |
468 | tc6393xb_cells[TC6393XB_CELL_MMC].platform_data = |
469 | &tc6393xb_cells[TC6393XB_CELL_MMC]; | |
470 | tc6393xb_cells[TC6393XB_CELL_MMC].data_size = | |
471 | sizeof(tc6393xb_cells[TC6393XB_CELL_MMC]); | |
472 | ||
f024ff10 | 473 | |
25d6cbd8 | 474 | ret = mfd_add_devices(&dev->dev, dev->id, |
f024ff10 DB |
475 | tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells), |
476 | iomem, tcpd->irq_base); | |
477 | ||
25d6cbd8 IM |
478 | if (!ret) |
479 | return 0; | |
d6315949 | 480 | |
1c1b6ffc DB |
481 | if (tcpd->teardown) |
482 | tcpd->teardown(dev); | |
483 | ||
484 | err_setup: | |
25d6cbd8 | 485 | tc6393xb_detach_irq(dev); |
d6315949 DB |
486 | |
487 | err_gpio_add: | |
488 | if (tc6393xb->gpio.base != -1) | |
489 | temp = gpiochip_remove(&tc6393xb->gpio); | |
d6315949 DB |
490 | tcpd->disable(dev); |
491 | err_clk_enable: | |
492 | clk_disable(tc6393xb->clk); | |
493 | err_enable: | |
494 | iounmap(tc6393xb->scr); | |
495 | err_ioremap: | |
496 | release_resource(&tc6393xb->rscr); | |
497 | err_request_scr: | |
498 | clk_put(tc6393xb->clk); | |
25d6cbd8 | 499 | err_noirq: |
d6315949 DB |
500 | err_clk_get: |
501 | kfree(tc6393xb); | |
502 | err_kzalloc: | |
25d6cbd8 | 503 | return ret; |
d6315949 DB |
504 | } |
505 | ||
506 | static int __devexit tc6393xb_remove(struct platform_device *dev) | |
507 | { | |
508 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
509 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
510 | int ret; | |
511 | ||
424f525a | 512 | mfd_remove_devices(&dev->dev); |
1c1b6ffc DB |
513 | |
514 | if (tcpd->teardown) | |
515 | tcpd->teardown(dev); | |
516 | ||
25d6cbd8 | 517 | tc6393xb_detach_irq(dev); |
d6315949 DB |
518 | |
519 | if (tc6393xb->gpio.base != -1) { | |
520 | ret = gpiochip_remove(&tc6393xb->gpio); | |
521 | if (ret) { | |
522 | dev_err(&dev->dev, "Can't remove gpio chip: %d\n", ret); | |
523 | return ret; | |
524 | } | |
525 | } | |
526 | ||
527 | ret = tcpd->disable(dev); | |
d6315949 | 528 | clk_disable(tc6393xb->clk); |
d6315949 | 529 | iounmap(tc6393xb->scr); |
d6315949 | 530 | release_resource(&tc6393xb->rscr); |
d6315949 | 531 | platform_set_drvdata(dev, NULL); |
d6315949 | 532 | clk_put(tc6393xb->clk); |
d6315949 DB |
533 | kfree(tc6393xb); |
534 | ||
535 | return ret; | |
536 | } | |
537 | ||
538 | #ifdef CONFIG_PM | |
539 | static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state) | |
540 | { | |
541 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
542 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
25d6cbd8 | 543 | int i, ret; |
d6315949 DB |
544 | |
545 | tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR); | |
546 | tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER); | |
547 | ||
548 | for (i = 0; i < 3; i++) { | |
549 | tc6393xb->suspend_state.gpo_dsr[i] = | |
550 | ioread8(tc6393xb->scr + SCR_GPO_DSR(i)); | |
551 | tc6393xb->suspend_state.gpo_doecr[i] = | |
552 | ioread8(tc6393xb->scr + SCR_GPO_DOECR(i)); | |
553 | tc6393xb->suspend_state.gpi_bcr[i] = | |
554 | ioread8(tc6393xb->scr + SCR_GPI_BCR(i)); | |
555 | } | |
25d6cbd8 IM |
556 | ret = tcpd->suspend(dev); |
557 | clk_disable(tc6393xb->clk); | |
d6315949 | 558 | |
25d6cbd8 | 559 | return ret; |
d6315949 DB |
560 | } |
561 | ||
562 | static int tc6393xb_resume(struct platform_device *dev) | |
563 | { | |
564 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
25d6cbd8 IM |
565 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); |
566 | int ret; | |
f98a0bd0 | 567 | int i; |
25d6cbd8 IM |
568 | |
569 | clk_enable(tc6393xb->clk); | |
570 | ||
571 | ret = tcpd->resume(dev); | |
d6315949 DB |
572 | if (ret) |
573 | return ret; | |
574 | ||
f98a0bd0 DB |
575 | if (!tcpd->resume_restore) |
576 | return 0; | |
577 | ||
578 | iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER); | |
579 | iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR); | |
580 | iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR); | |
581 | iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN | | |
582 | SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN | | |
583 | BIT(15), tc6393xb->scr + SCR_MCR); | |
584 | iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER); | |
585 | iowrite8(0, tc6393xb->scr + SCR_IRR); | |
586 | iowrite8(0xbf, tc6393xb->scr + SCR_IMR); | |
587 | ||
588 | for (i = 0; i < 3; i++) { | |
589 | iowrite8(tc6393xb->suspend_state.gpo_dsr[i], | |
590 | tc6393xb->scr + SCR_GPO_DSR(i)); | |
591 | iowrite8(tc6393xb->suspend_state.gpo_doecr[i], | |
592 | tc6393xb->scr + SCR_GPO_DOECR(i)); | |
593 | iowrite8(tc6393xb->suspend_state.gpi_bcr[i], | |
594 | tc6393xb->scr + SCR_GPI_BCR(i)); | |
595 | } | |
596 | ||
597 | return 0; | |
d6315949 DB |
598 | } |
599 | #else | |
600 | #define tc6393xb_suspend NULL | |
601 | #define tc6393xb_resume NULL | |
602 | #endif | |
603 | ||
604 | static struct platform_driver tc6393xb_driver = { | |
605 | .probe = tc6393xb_probe, | |
606 | .remove = __devexit_p(tc6393xb_remove), | |
607 | .suspend = tc6393xb_suspend, | |
608 | .resume = tc6393xb_resume, | |
609 | ||
610 | .driver = { | |
611 | .name = "tc6393xb", | |
612 | .owner = THIS_MODULE, | |
613 | }, | |
614 | }; | |
615 | ||
616 | static int __init tc6393xb_init(void) | |
617 | { | |
618 | return platform_driver_register(&tc6393xb_driver); | |
619 | } | |
620 | ||
621 | static void __exit tc6393xb_exit(void) | |
622 | { | |
623 | platform_driver_unregister(&tc6393xb_driver); | |
624 | } | |
625 | ||
626 | subsys_initcall(tc6393xb_init); | |
627 | module_exit(tc6393xb_exit); | |
628 | ||
25d6cbd8 | 629 | MODULE_LICENSE("GPL v2"); |
d6315949 DB |
630 | MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer"); |
631 | MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller"); | |
632 | MODULE_ALIAS("platform:tc6393xb"); |