[mirror_ubuntu-jammy-kernel.git] / drivers / mfd / tc6393xb.c

/*
 * Toshiba TC6393XB SoC support
 *
 * Copyright(c) 2005-2006 Chris Humbert
 * Copyright(c) 2005 Dirk Opfer
 * Copyright(c) 2005 Ian Molton <spyro@f2s.com>
 * Copyright(c) 2007 Dmitry Baryshkov
 *
 * Based on code written by Sharp/Lineo for 2.4 kernels
 * Based on locomo.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tmio.h>
#include <linux/mfd/tc6393xb.h>
#include <linux/gpio.h>

#define SCR_REVID	0x08		/* b Revision ID	*/
#define SCR_ISR		0x50		/* b Interrupt Status	*/
#define SCR_IMR		0x52		/* b Interrupt Mask	*/
#define SCR_IRR		0x54		/* b Interrupt Routing	*/
#define SCR_GPER	0x60		/* w GP Enable		*/
#define SCR_GPI_SR(i)	(0x64 + (i))	/* b3 GPI Status	*/
#define SCR_GPI_IMR(i)	(0x68 + (i))	/* b3 GPI INT Mask	*/
#define SCR_GPI_EDER(i)	(0x6c + (i))	/* b3 GPI Edge Detect Enable */
#define SCR_GPI_LIR(i)	(0x70 + (i))	/* b3 GPI Level Invert	*/
#define SCR_GPO_DSR(i)	(0x78 + (i))	/* b3 GPO Data Set	*/
#define SCR_GPO_DOECR(i) (0x7c + (i))	/* b3 GPO Data OE Control */
#define SCR_GP_IARCR(i)	(0x80 + (i))	/* b3 GP Internal Active Register Control */
#define SCR_GP_IARLCR(i) (0x84 + (i))	/* b3 GP INTERNAL Active Register Level Control */
#define SCR_GPI_BCR(i)	(0x88 + (i))	/* b3 GPI Buffer Control */
#define SCR_GPA_IARCR	0x8c		/* w GPa Internal Active Register Control */
#define SCR_GPA_IARLCR	0x90		/* w GPa Internal Active Register Level Control */
#define SCR_GPA_BCR	0x94		/* w GPa Buffer Control */
#define SCR_CCR		0x98		/* w Clock Control	*/
#define SCR_PLL2CR	0x9a		/* w PLL2 Control	*/
#define SCR_PLL1CR	0x9c		/* l PLL1 Control	*/
#define SCR_DIARCR	0xa0		/* b Device Internal Active Register Control */
#define SCR_DBOCR	0xa1		/* b Device Buffer Off Control */
#define SCR_FER		0xe0		/* b Function Enable	*/
#define SCR_MCR		0xe4		/* w Mode Control	*/
#define SCR_CONFIG	0xfc		/* b Configuration Control */
#define SCR_DEBUG	0xff		/* b Debug		*/

#define SCR_CCR_CK32K	BIT(0)
#define SCR_CCR_USBCK	BIT(1)
#define SCR_CCR_UNK1	BIT(4)
#define SCR_CCR_MCLK_MASK	(7 << 8)
#define SCR_CCR_MCLK_OFF	(0 << 8)
#define SCR_CCR_MCLK_12	(1 << 8)
#define SCR_CCR_MCLK_24	(2 << 8)
#define SCR_CCR_MCLK_48	(3 << 8)
#define SCR_CCR_HCLK_MASK	(3 << 12)
#define SCR_CCR_HCLK_24	(0 << 12)
#define SCR_CCR_HCLK_48	(1 << 12)

#define SCR_FER_USBEN		BIT(0)	/* USB host enable */
#define SCR_FER_LCDCVEN		BIT(1)	/* polysilicon TFT enable */
#define SCR_FER_SLCDEN		BIT(2)	/* SLCD enable */

#define SCR_MCR_RDY_MASK		(3 << 0)
#define SCR_MCR_RDY_OPENDRAIN	(0 << 0)
#define SCR_MCR_RDY_TRISTATE	(1 << 0)
#define SCR_MCR_RDY_PUSHPULL	(2 << 0)
#define SCR_MCR_RDY_UNK		BIT(2)
#define SCR_MCR_RDY_EN		BIT(3)
#define SCR_MCR_INT_MASK		(3 << 4)
#define SCR_MCR_INT_OPENDRAIN	(0 << 4)
#define SCR_MCR_INT_TRISTATE	(1 << 4)
#define SCR_MCR_INT_PUSHPULL	(2 << 4)
#define SCR_MCR_INT_UNK		BIT(6)
#define SCR_MCR_INT_EN		BIT(7)
/* bits 8 - 16 are unknown */

#define TC_GPIO_BIT(i)		(1 << (i & 0x7))

/*--------------------------------------------------------------------------*/

struct tc6393xb {
	void __iomem		*scr;

	struct gpio_chip	gpio;

	struct clk		*clk; /* 3,6 Mhz */

	spinlock_t		lock; /* protects RMW cycles */

	struct {
		u8		fer;
		u16		ccr;
		u8		gpi_bcr[3];
		u8		gpo_dsr[3];
		u8		gpo_doecr[3];
	} suspend_state;

	struct resource		rscr;
	struct resource		*iomem;
	int			irq;
	int			irq_base;
};

enum {
	TC6393XB_CELL_NAND,
	TC6393XB_CELL_MMC,
};

/*--------------------------------------------------------------------------*/

static int tc6393xb_nand_enable(struct platform_device *nand)
{
	struct platform_device *dev = to_platform_device(nand->dev.parent);
	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	unsigned long flags;

	spin_lock_irqsave(&tc6393xb->lock, flags);

	/* SMD buffer on */
	dev_dbg(&dev->dev, "SMD buffer on\n");
	tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1));

	spin_unlock_irqrestore(&tc6393xb->lock, flags);

	return 0;
}

static struct resource __devinitdata tc6393xb_nand_resources[] = {
	{
		.start	= 0x1000,
		.end	= 0x1007,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= 0x0100,
		.end	= 0x01ff,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_TC6393_NAND,
		.end	= IRQ_TC6393_NAND,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct resource __devinitdata tc6393xb_mmc_resources[] = {
	{
		.start	= 0x800,
		.end	= 0x9ff,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= 0x200,
		.end	= 0x2ff,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_TC6393_MMC,
		.end	= IRQ_TC6393_MMC,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mfd_cell __devinitdata tc6393xb_cells[] = {
	[TC6393XB_CELL_NAND] = {
		.name = "tmio-nand",
		.enable = tc6393xb_nand_enable,
		.num_resources = ARRAY_SIZE(tc6393xb_nand_resources),
		.resources = tc6393xb_nand_resources,
	},
	[TC6393XB_CELL_MMC] = {
		.name = "tmio-mmc",
		.num_resources = ARRAY_SIZE(tc6393xb_mmc_resources),
		.resources = tc6393xb_mmc_resources,
	},
};

/*--------------------------------------------------------------------------*/

static int tc6393xb_gpio_get(struct gpio_chip *chip,
		unsigned offset)
{
	struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);

	/* XXX: does dsr also represent inputs? */
	return tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8))
		& TC_GPIO_BIT(offset);
}

static void __tc6393xb_gpio_set(struct gpio_chip *chip,
		unsigned offset, int value)
{
	struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
	u8  dsr;

	dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8));
	if (value)
		dsr |= TC_GPIO_BIT(offset);
	else
		dsr &= ~TC_GPIO_BIT(offset);

	tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8));
}

static void tc6393xb_gpio_set(struct gpio_chip *chip,
		unsigned offset, int value)
{
	struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
	unsigned long flags;

	spin_lock_irqsave(&tc6393xb->lock, flags);

	__tc6393xb_gpio_set(chip, offset, value);

	spin_unlock_irqrestore(&tc6393xb->lock, flags);
}

static int tc6393xb_gpio_direction_input(struct gpio_chip *chip,
			unsigned offset)
{
	struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
	unsigned long flags;
	u8 doecr;

	spin_lock_irqsave(&tc6393xb->lock, flags);

	doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
	doecr &= ~TC_GPIO_BIT(offset);
	tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));

	spin_unlock_irqrestore(&tc6393xb->lock, flags);

	return 0;
}

static int tc6393xb_gpio_direction_output(struct gpio_chip *chip,
			unsigned offset, int value)
{
	struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
	unsigned long flags;
	u8 doecr;

	spin_lock_irqsave(&tc6393xb->lock, flags);

	__tc6393xb_gpio_set(chip, offset, value);

	doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
	doecr |= TC_GPIO_BIT(offset);
	tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));

	spin_unlock_irqrestore(&tc6393xb->lock, flags);

	return 0;
}

static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base)
{
	tc6393xb->gpio.label = "tc6393xb";
	tc6393xb->gpio.base = gpio_base;
	tc6393xb->gpio.ngpio = 16;
	tc6393xb->gpio.set = tc6393xb_gpio_set;
	tc6393xb->gpio.get = tc6393xb_gpio_get;
	tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input;
	tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output;

	return gpiochip_add(&tc6393xb->gpio);
}

/*--------------------------------------------------------------------------*/

static void
tc6393xb_irq(unsigned int irq, struct irq_desc *desc)
{
	struct tc6393xb *tc6393xb = get_irq_data(irq);
	unsigned int isr;
	unsigned int i, irq_base;

	irq_base = tc6393xb->irq_base;

	while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) &
				~tmio_ioread8(tc6393xb->scr + SCR_IMR)))
		for (i = 0; i < TC6393XB_NR_IRQS; i++) {
			if (isr & (1 << i))
				generic_handle_irq(irq_base + i);
		}
}

static void tc6393xb_irq_ack(unsigned int irq)
{
}

static void tc6393xb_irq_mask(unsigned int irq)
{
	struct tc6393xb *tc6393xb = get_irq_chip_data(irq);
	unsigned long flags;
	u8 imr;

	spin_lock_irqsave(&tc6393xb->lock, flags);
	imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
	imr |= 1 << (irq - tc6393xb->irq_base);
	tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
	spin_unlock_irqrestore(&tc6393xb->lock, flags);
}

static void tc6393xb_irq_unmask(unsigned int irq)
{
	struct tc6393xb *tc6393xb = get_irq_chip_data(irq);
	unsigned long flags;
	u8 imr;

	spin_lock_irqsave(&tc6393xb->lock, flags);
	imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
	imr &= ~(1 << (irq - tc6393xb->irq_base));
	tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
	spin_unlock_irqrestore(&tc6393xb->lock, flags);
}

static struct irq_chip tc6393xb_chip = {
	.name	= "tc6393xb",
	.ack	= tc6393xb_irq_ack,
	.mask	= tc6393xb_irq_mask,
	.unmask	= tc6393xb_irq_unmask,
};

static void tc6393xb_attach_irq(struct platform_device *dev)
{
	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	unsigned int irq, irq_base;

	irq_base = tc6393xb->irq_base;

	for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
		set_irq_chip(irq, &tc6393xb_chip);
		set_irq_chip_data(irq, tc6393xb);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING);
	set_irq_data(tc6393xb->irq, tc6393xb);
	set_irq_chained_handler(tc6393xb->irq, tc6393xb_irq);
}

static void tc6393xb_detach_irq(struct platform_device *dev)
{
	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	unsigned int irq, irq_base;

	set_irq_chained_handler(tc6393xb->irq, NULL);
	set_irq_data(tc6393xb->irq, NULL);

	irq_base = tc6393xb->irq_base;

	for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
		set_irq_flags(irq, 0);
		set_irq_chip(irq, NULL);
		set_irq_chip_data(irq, NULL);
	}
}

/*--------------------------------------------------------------------------*/

static int tc6393xb_hw_init(struct platform_device *dev)
{
	struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	int i;

	iowrite8(tc6393xb->suspend_state.fer,	tc6393xb->scr + SCR_FER);
	iowrite16(tcpd->scr_pll2cr,		tc6393xb->scr + SCR_PLL2CR);
	iowrite16(tc6393xb->suspend_state.ccr,	tc6393xb->scr + SCR_CCR);
	iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
		  SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
		  BIT(15),			tc6393xb->scr + SCR_MCR);
	iowrite16(tcpd->scr_gper,		tc6393xb->scr + SCR_GPER);
	iowrite8(0,				tc6393xb->scr + SCR_IRR);
	iowrite8(0xbf,				tc6393xb->scr + SCR_IMR);

	for (i = 0; i < 3; i++) {
		iowrite8(tc6393xb->suspend_state.gpo_dsr[i],
					tc6393xb->scr + SCR_GPO_DSR(i));
		iowrite8(tc6393xb->suspend_state.gpo_doecr[i],
					tc6393xb->scr + SCR_GPO_DOECR(i));
		iowrite8(tc6393xb->suspend_state.gpi_bcr[i],
					tc6393xb->scr + SCR_GPI_BCR(i));
	}

	return 0;
}

static int __devinit tc6393xb_probe(struct platform_device *dev)
{
	struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
	struct tc6393xb *tc6393xb;
	struct resource *iomem, *rscr;
	int ret, temp;
	int i;

	iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!iomem)
		return -EINVAL;

	tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
	if (!tc6393xb) {
		ret = -ENOMEM;
		goto err_kzalloc;
	}

	spin_lock_init(&tc6393xb->lock);

	platform_set_drvdata(dev, tc6393xb);

	ret = platform_get_irq(dev, 0);
	if (ret >= 0)
		tc6393xb->irq = ret;
	else
		goto err_noirq;

	tc6393xb->iomem = iomem;
	tc6393xb->irq_base = tcpd->irq_base;

	tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI");
	if (IS_ERR(tc6393xb->clk)) {
		ret = PTR_ERR(tc6393xb->clk);
		goto err_clk_get;
	}

	rscr = &tc6393xb->rscr;
	rscr->name = "tc6393xb-core";
	rscr->start = iomem->start;
	rscr->end = iomem->start + 0xff;
	rscr->flags = IORESOURCE_MEM;

	ret = request_resource(iomem, rscr);
	if (ret)
		goto err_request_scr;

	tc6393xb->scr = ioremap(rscr->start, rscr->end - rscr->start + 1);
	if (!tc6393xb->scr) {
		ret = -ENOMEM;
		goto err_ioremap;
	}

	ret = clk_enable(tc6393xb->clk);
	if (ret)
		goto err_clk_enable;

	ret = tcpd->enable(dev);
	if (ret)
		goto err_enable;

	tc6393xb->suspend_state.fer = 0;

	for (i = 0; i < 3; i++) {
		tc6393xb->suspend_state.gpo_dsr[i] =
			(tcpd->scr_gpo_dsr >> (8 * i)) & 0xff;
		tc6393xb->suspend_state.gpo_doecr[i] =
			(tcpd->scr_gpo_doecr >> (8 * i)) & 0xff;
	}

	tc6393xb->suspend_state.ccr = SCR_CCR_UNK1 |
					SCR_CCR_HCLK_48;

	ret = tc6393xb_hw_init(dev);
	if (ret)
		goto err_hw_init;

	printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
			tmio_ioread8(tc6393xb->scr + SCR_REVID),
			(unsigned long) iomem->start, tc6393xb->irq);

	tc6393xb->gpio.base = -1;

	if (tcpd->gpio_base >= 0) {
		ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base);
		if (ret)
			goto err_gpio_add;
	}

	tc6393xb_attach_irq(dev);

	tc6393xb_cells[TC6393XB_CELL_NAND].driver_data = tcpd->nand_data;
	tc6393xb_cells[TC6393XB_CELL_NAND].platform_data =
		&tc6393xb_cells[TC6393XB_CELL_NAND];
	tc6393xb_cells[TC6393XB_CELL_NAND].data_size =
		sizeof(tc6393xb_cells[TC6393XB_CELL_NAND]);
	tc6393xb_cells[TC6393XB_CELL_MMC].platform_data =
		&tc6393xb_cells[TC6393XB_CELL_MMC];
	tc6393xb_cells[TC6393XB_CELL_MMC].data_size =
		sizeof(tc6393xb_cells[TC6393XB_CELL_MMC]);


	ret = mfd_add_devices(&dev->dev, dev->id,
			tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells),
			iomem, tcpd->irq_base);

	if (!ret)
		return 0;

	tc6393xb_detach_irq(dev);

err_gpio_add:
	if (tc6393xb->gpio.base != -1)
		temp = gpiochip_remove(&tc6393xb->gpio);
err_hw_init:
	tcpd->disable(dev);
err_clk_enable:
	clk_disable(tc6393xb->clk);
err_enable:
	iounmap(tc6393xb->scr);
err_ioremap:
	release_resource(&tc6393xb->rscr);
err_request_scr:
	clk_put(tc6393xb->clk);
err_noirq:
err_clk_get:
	kfree(tc6393xb);
err_kzalloc:
	return ret;
}

static int __devexit tc6393xb_remove(struct platform_device *dev)
{
	struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	int ret;

	mfd_remove_devices(&dev->dev);
	tc6393xb_detach_irq(dev);

	if (tc6393xb->gpio.base != -1) {
		ret = gpiochip_remove(&tc6393xb->gpio);
		if (ret) {
			dev_err(&dev->dev, "Can't remove gpio chip: %d\n", ret);
			return ret;
		}
	}

	ret = tcpd->disable(dev);
	clk_disable(tc6393xb->clk);
	iounmap(tc6393xb->scr);
	release_resource(&tc6393xb->rscr);
	platform_set_drvdata(dev, NULL);
	clk_put(tc6393xb->clk);
	kfree(tc6393xb);

	return ret;
}

#ifdef CONFIG_PM
static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
{
	struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	int i, ret;

	tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR);
	tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER);

	for (i = 0; i < 3; i++) {
		tc6393xb->suspend_state.gpo_dsr[i] =
			ioread8(tc6393xb->scr + SCR_GPO_DSR(i));
		tc6393xb->suspend_state.gpo_doecr[i] =
			ioread8(tc6393xb->scr + SCR_GPO_DOECR(i));
		tc6393xb->suspend_state.gpi_bcr[i] =
			ioread8(tc6393xb->scr + SCR_GPI_BCR(i));
	}
	ret = tcpd->suspend(dev);
	clk_disable(tc6393xb->clk);

	return ret;
}

static int tc6393xb_resume(struct platform_device *dev)
{
	struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	int ret;

	clk_enable(tc6393xb->clk);

	ret = tcpd->resume(dev);

	if (ret)
		return ret;

	return tc6393xb_hw_init(dev);
}
#else
#define tc6393xb_suspend NULL
#define tc6393xb_resume NULL
#endif

static struct platform_driver tc6393xb_driver = {
	.probe = tc6393xb_probe,
	.remove = __devexit_p(tc6393xb_remove),
	.suspend = tc6393xb_suspend,
	.resume = tc6393xb_resume,

	.driver = {
		.name = "tc6393xb",
		.owner = THIS_MODULE,
	},
};

static int __init tc6393xb_init(void)
{
	return platform_driver_register(&tc6393xb_driver);
}

static void __exit tc6393xb_exit(void)
{
	platform_driver_unregister(&tc6393xb_driver);
}

subsys_initcall(tc6393xb_init);
module_exit(tc6393xb_exit);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer");
MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller");
MODULE_ALIAS("platform:tc6393xb");
Commit	Line	Data
d6315949 DB	1	/*
	2	* Toshiba TC6393XB SoC support
	3	*
	4	* Copyright(c) 2005-2006 Chris Humbert
	5	* Copyright(c) 2005 Dirk Opfer
	6	* Copyright(c) 2005 Ian Molton <spyro@f2s.com>
	7	* Copyright(c) 2007 Dmitry Baryshkov
	8	*
	9	* Based on code written by Sharp/Lineo for 2.4 kernels
	10	* Based on locomo.c
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/io.h>
	20	#include <linux/irq.h>
	21	#include <linux/platform_device.h>
d6315949	22	#include <linux/clk.h>
25d6cbd8	23	#include <linux/err.h>
f024ff10 DB	24	#include <linux/mfd/core.h>
f024ff10 DB	25	#include <linux/mfd/tmio.h>
d6315949 DB	26	#include <linux/mfd/tc6393xb.h>
	27	#include <linux/gpio.h>
	28
	29	#define SCR_REVID 0x08 /* b Revision ID */
	30	#define SCR_ISR 0x50 /* b Interrupt Status */
	31	#define SCR_IMR 0x52 /* b Interrupt Mask */
	32	#define SCR_IRR 0x54 /* b Interrupt Routing */
	33	#define SCR_GPER 0x60 /* w GP Enable */
	34	#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
	35	#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
	36	#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
	37	#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
	38	#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
	39	#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
	40	#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
	41	#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
	42	#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
	43	#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
	44	#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
	45	#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
	46	#define SCR_CCR 0x98 /* w Clock Control */
	47	#define SCR_PLL2CR 0x9a /* w PLL2 Control */
	48	#define SCR_PLL1CR 0x9c /* l PLL1 Control */
	49	#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
	50	#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
	51	#define SCR_FER 0xe0 /* b Function Enable */
	52	#define SCR_MCR 0xe4 /* w Mode Control */
	53	#define SCR_CONFIG 0xfc /* b Configuration Control */
	54	#define SCR_DEBUG 0xff /* b Debug */
	55
	56	#define SCR_CCR_CK32K BIT(0)
	57	#define SCR_CCR_USBCK BIT(1)
	58	#define SCR_CCR_UNK1 BIT(4)
	59	#define SCR_CCR_MCLK_MASK (7 << 8)
	60	#define SCR_CCR_MCLK_OFF (0 << 8)
	61	#define SCR_CCR_MCLK_12 (1 << 8)
	62	#define SCR_CCR_MCLK_24 (2 << 8)
	63	#define SCR_CCR_MCLK_48 (3 << 8)
	64	#define SCR_CCR_HCLK_MASK (3 << 12)
	65	#define SCR_CCR_HCLK_24 (0 << 12)
	66	#define SCR_CCR_HCLK_48 (1 << 12)
	67
	68	#define SCR_FER_USBEN BIT(0) /* USB host enable */
	69	#define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */
	70	#define SCR_FER_SLCDEN BIT(2) /* SLCD enable */
	71
	72	#define SCR_MCR_RDY_MASK (3 << 0)
	73	#define SCR_MCR_RDY_OPENDRAIN (0 << 0)
	74	#define SCR_MCR_RDY_TRISTATE (1 << 0)
	75	#define SCR_MCR_RDY_PUSHPULL (2 << 0)
	76	#define SCR_MCR_RDY_UNK BIT(2)
	77	#define SCR_MCR_RDY_EN BIT(3)
	78	#define SCR_MCR_INT_MASK (3 << 4)
	79	#define SCR_MCR_INT_OPENDRAIN (0 << 4)
	80	#define SCR_MCR_INT_TRISTATE (1 << 4)
	81	#define SCR_MCR_INT_PUSHPULL (2 << 4)
	82	#define SCR_MCR_INT_UNK BIT(6)
	83	#define SCR_MCR_INT_EN BIT(7)
	84	/* bits 8 - 16 are unknown */
	85
	86	#define TC_GPIO_BIT(i) (1 << (i & 0x7))
	87
	88	/--------------------------------------------------------------------------/
	89
90	struct tc6393xb {
91	void __iomem *scr;
92
93	struct gpio_chip gpio;
94
95	struct clk clk; / 3,6 Mhz */
96
97	spinlock_t lock; /* protects RMW cycles */
98
99	struct {
100	u8 fer;
101	u16 ccr;
102	u8 gpi_bcr[3];
103	u8 gpo_dsr[3];
104	u8 gpo_doecr[3];
105	} suspend_state;
106
107	struct resource rscr;
108	struct resource *iomem;
109	int irq;
110	int irq_base;
111	};
112
f024ff10 DB	113	enum {
f024ff10 DB	114	TC6393XB_CELL_NAND,
25d6cbd8	115	TC6393XB_CELL_MMC,
f024ff10 DB	116	};
	117
	118	/--------------------------------------------------------------------------/
	119
	120	static int tc6393xb_nand_enable(struct platform_device *nand)
	121	{
	122	struct platform_device *dev = to_platform_device(nand->dev.parent);
	123	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	124	unsigned long flags;
	125
	126	spin_lock_irqsave(&tc6393xb->lock, flags);
	127
	128	/* SMD buffer on */
	129	dev_dbg(&dev->dev, "SMD buffer on\n");
25d6cbd8	130	tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1));
f024ff10 DB	131
	132	spin_unlock_irqrestore(&tc6393xb->lock, flags);
	133
	134	return 0;
	135	}
	136
	137	static struct resource __devinitdata tc6393xb_nand_resources[] = {
	138	{
25d6cbd8 IM	139	.start = 0x1000,
25d6cbd8 IM	140	.end = 0x1007,
f024ff10 DB	141	.flags = IORESOURCE_MEM,
	142	},
	143	{
25d6cbd8 IM	144	.start = 0x0100,
25d6cbd8 IM	145	.end = 0x01ff,
f024ff10 DB	146	.flags = IORESOURCE_MEM,
	147	},
	148	{
f024ff10 DB	149	.start = IRQ_TC6393_NAND,
	150	.end = IRQ_TC6393_NAND,
	151	.flags = IORESOURCE_IRQ,
	152	},
	153	};
	154
25d6cbd8 IM	155	static struct resource __devinitdata tc6393xb_mmc_resources[] = {
	156	{
	157	.start = 0x800,
	158	.end = 0x9ff,
	159	.flags = IORESOURCE_MEM,
	160	},
	161	{
	162	.start = 0x200,
	163	.end = 0x2ff,
	164	.flags = IORESOURCE_MEM,
	165	},
	166	{
	167	.start = IRQ_TC6393_MMC,
	168	.end = IRQ_TC6393_MMC,
	169	.flags = IORESOURCE_IRQ,
	170	},
	171	};
	172
f024ff10 DB	173	static struct mfd_cell __devinitdata tc6393xb_cells[] = {
	174	[TC6393XB_CELL_NAND] = {
	175	.name = "tmio-nand",
	176	.enable = tc6393xb_nand_enable,
	177	.num_resources = ARRAY_SIZE(tc6393xb_nand_resources),
	178	.resources = tc6393xb_nand_resources,
	179	},
25d6cbd8 IM	180	[TC6393XB_CELL_MMC] = {
	181	.name = "tmio-mmc",
	182	.num_resources = ARRAY_SIZE(tc6393xb_mmc_resources),
	183	.resources = tc6393xb_mmc_resources,
	184	},
f024ff10 DB	185	};
f024ff10 DB	186
d6315949 DB	187	/--------------------------------------------------------------------------/
	188
	189	static int tc6393xb_gpio_get(struct gpio_chip *chip,
	190	unsigned offset)
	191	{
	192	struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
	193
	194	/* XXX: does dsr also represent inputs? */
25d6cbd8	195	return tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8))
d6315949 DB	196	& TC_GPIO_BIT(offset);
	197	}
	198
	199	static void __tc6393xb_gpio_set(struct gpio_chip *chip,
	200	unsigned offset, int value)
	201	{
	202	struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
	203	u8 dsr;
	204
25d6cbd8	205	dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8));
d6315949 DB	206	if (value)
	207	dsr \|= TC_GPIO_BIT(offset);
	208	else
	209	dsr &= ~TC_GPIO_BIT(offset);
	210
25d6cbd8	211	tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8));
d6315949 DB	212	}
	213
	214	static void tc6393xb_gpio_set(struct gpio_chip *chip,
	215	unsigned offset, int value)
	216	{
	217	struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
	218	unsigned long flags;
	219
	220	spin_lock_irqsave(&tc6393xb->lock, flags);
	221
	222	__tc6393xb_gpio_set(chip, offset, value);
	223
	224	spin_unlock_irqrestore(&tc6393xb->lock, flags);
	225	}
	226
	227	static int tc6393xb_gpio_direction_input(struct gpio_chip *chip,
	228	unsigned offset)
	229	{
	230	struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
	231	unsigned long flags;
	232	u8 doecr;
	233
	234	spin_lock_irqsave(&tc6393xb->lock, flags);
	235
25d6cbd8	236	doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
d6315949	237	doecr &= ~TC_GPIO_BIT(offset);
25d6cbd8	238	tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
d6315949 DB	239
	240	spin_unlock_irqrestore(&tc6393xb->lock, flags);
	241
	242	return 0;
	243	}
	244
	245	static int tc6393xb_gpio_direction_output(struct gpio_chip *chip,
	246	unsigned offset, int value)
	247	{
	248	struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
	249	unsigned long flags;
	250	u8 doecr;
	251
	252	spin_lock_irqsave(&tc6393xb->lock, flags);
	253
	254	__tc6393xb_gpio_set(chip, offset, value);
	255
25d6cbd8	256	doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
d6315949	257	doecr \|= TC_GPIO_BIT(offset);
25d6cbd8	258	tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
d6315949 DB	259
	260	spin_unlock_irqrestore(&tc6393xb->lock, flags);
	261
	262	return 0;
	263	}
	264
	265	static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base)
	266	{
	267	tc6393xb->gpio.label = "tc6393xb";
	268	tc6393xb->gpio.base = gpio_base;
	269	tc6393xb->gpio.ngpio = 16;
	270	tc6393xb->gpio.set = tc6393xb_gpio_set;
	271	tc6393xb->gpio.get = tc6393xb_gpio_get;
	272	tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input;
	273	tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output;
	274
	275	return gpiochip_add(&tc6393xb->gpio);
	276	}
	277
	278	/--------------------------------------------------------------------------/
	279
	280	static void
	281	tc6393xb_irq(unsigned int irq, struct irq_desc *desc)
	282	{
	283	struct tc6393xb *tc6393xb = get_irq_data(irq);
	284	unsigned int isr;
	285	unsigned int i, irq_base;
	286
	287	irq_base = tc6393xb->irq_base;
	288
25d6cbd8 IM	289	while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) &
25d6cbd8 IM	290	~tmio_ioread8(tc6393xb->scr + SCR_IMR)))
d6315949 DB	291	for (i = 0; i < TC6393XB_NR_IRQS; i++) {
	292	if (isr & (1 << i))
	293	generic_handle_irq(irq_base + i);
	294	}
	295	}
	296
	297	static void tc6393xb_irq_ack(unsigned int irq)
	298	{
	299	}
	300
	301	static void tc6393xb_irq_mask(unsigned int irq)
	302	{
	303	struct tc6393xb *tc6393xb = get_irq_chip_data(irq);
	304	unsigned long flags;
	305	u8 imr;
	306
	307	spin_lock_irqsave(&tc6393xb->lock, flags);
25d6cbd8	308	imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
d6315949	309	imr \|= 1 << (irq - tc6393xb->irq_base);
25d6cbd8	310	tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
d6315949 DB	311	spin_unlock_irqrestore(&tc6393xb->lock, flags);
	312	}
	313
	314	static void tc6393xb_irq_unmask(unsigned int irq)
	315	{
	316	struct tc6393xb *tc6393xb = get_irq_chip_data(irq);
	317	unsigned long flags;
	318	u8 imr;
	319
	320	spin_lock_irqsave(&tc6393xb->lock, flags);
25d6cbd8	321	imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
d6315949	322	imr &= ~(1 << (irq - tc6393xb->irq_base));
25d6cbd8	323	tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
d6315949 DB	324	spin_unlock_irqrestore(&tc6393xb->lock, flags);
	325	}
	326
	327	static struct irq_chip tc6393xb_chip = {
	328	.name = "tc6393xb",
	329	.ack = tc6393xb_irq_ack,
	330	.mask = tc6393xb_irq_mask,
	331	.unmask = tc6393xb_irq_unmask,
	332	};
	333
	334	static void tc6393xb_attach_irq(struct platform_device *dev)
	335	{
	336	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	337	unsigned int irq, irq_base;
	338
	339	irq_base = tc6393xb->irq_base;
	340
	341	for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
	342	set_irq_chip(irq, &tc6393xb_chip);
	343	set_irq_chip_data(irq, tc6393xb);
	344	set_irq_handler(irq, handle_edge_irq);
	345	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	346	}
	347
6cab4860	348	set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING);
d6315949 DB	349	set_irq_data(tc6393xb->irq, tc6393xb);
	350	set_irq_chained_handler(tc6393xb->irq, tc6393xb_irq);
	351	}
	352
	353	static void tc6393xb_detach_irq(struct platform_device *dev)
	354	{
	355	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	356	unsigned int irq, irq_base;
	357
	358	set_irq_chained_handler(tc6393xb->irq, NULL);
	359	set_irq_data(tc6393xb->irq, NULL);
	360
	361	irq_base = tc6393xb->irq_base;
	362
	363	for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
	364	set_irq_flags(irq, 0);
	365	set_irq_chip(irq, NULL);
	366	set_irq_chip_data(irq, NULL);
	367	}
	368	}
	369
	370	/--------------------------------------------------------------------------/
	371
	372	static int tc6393xb_hw_init(struct platform_device *dev)
	373	{
	374	struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
	375	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	376	int i;
	377
	378	iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER);
	379	iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
	380	iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR);
	381	iowrite16(SCR_MCR_RDY_OPENDRAIN \| SCR_MCR_RDY_UNK \| SCR_MCR_RDY_EN \|
	382	SCR_MCR_INT_OPENDRAIN \| SCR_MCR_INT_UNK \| SCR_MCR_INT_EN \|
	383	BIT(15), tc6393xb->scr + SCR_MCR);
	384	iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
	385	iowrite8(0, tc6393xb->scr + SCR_IRR);
	386	iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
	387
	388	for (i = 0; i < 3; i++) {
	389	iowrite8(tc6393xb->suspend_state.gpo_dsr[i],
	390	tc6393xb->scr + SCR_GPO_DSR(i));
	391	iowrite8(tc6393xb->suspend_state.gpo_doecr[i],
	392	tc6393xb->scr + SCR_GPO_DOECR(i));
	393	iowrite8(tc6393xb->suspend_state.gpi_bcr[i],
	394	tc6393xb->scr + SCR_GPI_BCR(i));
	395	}
	396
	397	return 0;
	398	}
	399
	400	static int __devinit tc6393xb_probe(struct platform_device *dev)
	401	{
	402	struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
	403	struct tc6393xb *tc6393xb;
25d6cbd8 IM	404	struct resource iomem, rscr;
25d6cbd8 IM	405	int ret, temp;
d6315949 DB	406	int i;
	407
	408	iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
	409	if (!iomem)
	410	return -EINVAL;
	411
	412	tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
	413	if (!tc6393xb) {
25d6cbd8	414	ret = -ENOMEM;
d6315949 DB	415	goto err_kzalloc;
	416	}
	417
	418	spin_lock_init(&tc6393xb->lock);
	419
	420	platform_set_drvdata(dev, tc6393xb);
25d6cbd8 IM	421
	422	ret = platform_get_irq(dev, 0);
	423	if (ret >= 0)
	424	tc6393xb->irq = ret;
	425	else
	426	goto err_noirq;
	427
d6315949	428	tc6393xb->iomem = iomem;
d6315949 DB	429	tc6393xb->irq_base = tcpd->irq_base;
d6315949 DB	430
25d6cbd8	431	tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI");
d6315949	432	if (IS_ERR(tc6393xb->clk)) {
25d6cbd8	433	ret = PTR_ERR(tc6393xb->clk);
d6315949 DB	434	goto err_clk_get;
	435	}
	436
	437	rscr = &tc6393xb->rscr;
	438	rscr->name = "tc6393xb-core";
	439	rscr->start = iomem->start;
	440	rscr->end = iomem->start + 0xff;
	441	rscr->flags = IORESOURCE_MEM;
	442
25d6cbd8 IM	443	ret = request_resource(iomem, rscr);
25d6cbd8 IM	444	if (ret)
d6315949 DB	445	goto err_request_scr;
	446
	447	tc6393xb->scr = ioremap(rscr->start, rscr->end - rscr->start + 1);
	448	if (!tc6393xb->scr) {
25d6cbd8	449	ret = -ENOMEM;
d6315949 DB	450	goto err_ioremap;
	451	}
	452
25d6cbd8 IM	453	ret = clk_enable(tc6393xb->clk);
25d6cbd8 IM	454	if (ret)
d6315949 DB	455	goto err_clk_enable;
d6315949 DB	456
25d6cbd8 IM	457	ret = tcpd->enable(dev);
25d6cbd8 IM	458	if (ret)
d6315949 DB	459	goto err_enable;
	460
	461	tc6393xb->suspend_state.fer = 0;
25d6cbd8	462
d6315949 DB	463	for (i = 0; i < 3; i++) {
	464	tc6393xb->suspend_state.gpo_dsr[i] =
	465	(tcpd->scr_gpo_dsr >> (8 * i)) & 0xff;
	466	tc6393xb->suspend_state.gpo_doecr[i] =
	467	(tcpd->scr_gpo_doecr >> (8 * i)) & 0xff;
	468	}
25d6cbd8	469
d6315949 DB	470	tc6393xb->suspend_state.ccr = SCR_CCR_UNK1 \|
	471	SCR_CCR_HCLK_48;
	472
25d6cbd8 IM	473	ret = tc6393xb_hw_init(dev);
25d6cbd8 IM	474	if (ret)
d6315949 DB	475	goto err_hw_init;
	476
	477	printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
25d6cbd8	478	tmio_ioread8(tc6393xb->scr + SCR_REVID),
d6315949 DB	479	(unsigned long) iomem->start, tc6393xb->irq);
	480
	481	tc6393xb->gpio.base = -1;
	482
	483	if (tcpd->gpio_base >= 0) {
25d6cbd8 IM	484	ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base);
25d6cbd8 IM	485	if (ret)
d6315949 DB	486	goto err_gpio_add;
	487	}
	488
25d6cbd8	489	tc6393xb_attach_irq(dev);
d6315949	490
f024ff10	491	tc6393xb_cells[TC6393XB_CELL_NAND].driver_data = tcpd->nand_data;
56edb58b MR	492	tc6393xb_cells[TC6393XB_CELL_NAND].platform_data =
	493	&tc6393xb_cells[TC6393XB_CELL_NAND];
	494	tc6393xb_cells[TC6393XB_CELL_NAND].data_size =
	495	sizeof(tc6393xb_cells[TC6393XB_CELL_NAND]);
25d6cbd8 IM	496	tc6393xb_cells[TC6393XB_CELL_MMC].platform_data =
	497	&tc6393xb_cells[TC6393XB_CELL_MMC];
	498	tc6393xb_cells[TC6393XB_CELL_MMC].data_size =
	499	sizeof(tc6393xb_cells[TC6393XB_CELL_MMC]);
	500
f024ff10	501
25d6cbd8	502	ret = mfd_add_devices(&dev->dev, dev->id,
f024ff10 DB	503	tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells),
	504	iomem, tcpd->irq_base);
	505
25d6cbd8 IM	506	if (!ret)
25d6cbd8 IM	507	return 0;
d6315949	508
25d6cbd8	509	tc6393xb_detach_irq(dev);
d6315949 DB	510
	511	err_gpio_add:
	512	if (tc6393xb->gpio.base != -1)
	513	temp = gpiochip_remove(&tc6393xb->gpio);
	514	err_hw_init:
	515	tcpd->disable(dev);
	516	err_clk_enable:
	517	clk_disable(tc6393xb->clk);
	518	err_enable:
	519	iounmap(tc6393xb->scr);
	520	err_ioremap:
	521	release_resource(&tc6393xb->rscr);
	522	err_request_scr:
	523	clk_put(tc6393xb->clk);
25d6cbd8	524	err_noirq:
d6315949 DB	525	err_clk_get:
	526	kfree(tc6393xb);
	527	err_kzalloc:
25d6cbd8	528	return ret;
d6315949 DB	529	}
	530
	531	static int __devexit tc6393xb_remove(struct platform_device *dev)
	532	{
	533	struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
	534	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	535	int ret;
	536
424f525a	537	mfd_remove_devices(&dev->dev);
25d6cbd8	538	tc6393xb_detach_irq(dev);
d6315949 DB	539
	540	if (tc6393xb->gpio.base != -1) {
	541	ret = gpiochip_remove(&tc6393xb->gpio);
	542	if (ret) {
	543	dev_err(&dev->dev, "Can't remove gpio chip: %d\n", ret);
	544	return ret;
	545	}
	546	}
	547
	548	ret = tcpd->disable(dev);
d6315949	549	clk_disable(tc6393xb->clk);
d6315949	550	iounmap(tc6393xb->scr);
d6315949	551	release_resource(&tc6393xb->rscr);
d6315949	552	platform_set_drvdata(dev, NULL);
d6315949	553	clk_put(tc6393xb->clk);
d6315949 DB	554	kfree(tc6393xb);
	555
	556	return ret;
	557	}
	558
	559	#ifdef CONFIG_PM
	560	static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
	561	{
	562	struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
	563	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
25d6cbd8	564	int i, ret;
d6315949 DB	565
	566	tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR);
	567	tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER);
	568
	569	for (i = 0; i < 3; i++) {
	570	tc6393xb->suspend_state.gpo_dsr[i] =
	571	ioread8(tc6393xb->scr + SCR_GPO_DSR(i));
	572	tc6393xb->suspend_state.gpo_doecr[i] =
	573	ioread8(tc6393xb->scr + SCR_GPO_DOECR(i));
	574	tc6393xb->suspend_state.gpi_bcr[i] =
	575	ioread8(tc6393xb->scr + SCR_GPI_BCR(i));
	576	}
25d6cbd8 IM	577	ret = tcpd->suspend(dev);
25d6cbd8 IM	578	clk_disable(tc6393xb->clk);
d6315949	579
25d6cbd8	580	return ret;
d6315949 DB	581	}
	582
	583	static int tc6393xb_resume(struct platform_device *dev)
	584	{
	585	struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
25d6cbd8 IM	586	struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
	587	int ret;
	588
	589	clk_enable(tc6393xb->clk);
	590
	591	ret = tcpd->resume(dev);
d6315949 DB	592
	593	if (ret)
	594	return ret;
	595
	596	return tc6393xb_hw_init(dev);
	597	}
	598	#else
	599	#define tc6393xb_suspend NULL
	600	#define tc6393xb_resume NULL
	601	#endif
	602
	603	static struct platform_driver tc6393xb_driver = {
	604	.probe = tc6393xb_probe,
	605	.remove = __devexit_p(tc6393xb_remove),
	606	.suspend = tc6393xb_suspend,
	607	.resume = tc6393xb_resume,
	608
	609	.driver = {
	610	.name = "tc6393xb",
	611	.owner = THIS_MODULE,
	612	},
	613	};
	614
	615	static int __init tc6393xb_init(void)
	616	{
	617	return platform_driver_register(&tc6393xb_driver);
	618	}
	619
	620	static void __exit tc6393xb_exit(void)
	621	{
	622	platform_driver_unregister(&tc6393xb_driver);
	623	}
	624
	625	subsys_initcall(tc6393xb_init);
	626	module_exit(tc6393xb_exit);
	627
25d6cbd8	628	MODULE_LICENSE("GPL v2");
d6315949 DB	629	MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer");
	630	MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller");
	631	MODULE_ALIAS("platform:tc6393xb");