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d6315949 DB |
1 | /* |
2 | * Toshiba TC6393XB SoC support | |
3 | * | |
4 | * Copyright(c) 2005-2006 Chris Humbert | |
5 | * Copyright(c) 2005 Dirk Opfer | |
6 | * Copyright(c) 2005 Ian Molton <spyro@f2s.com> | |
7 | * Copyright(c) 2007 Dmitry Baryshkov | |
8 | * | |
9 | * Based on code written by Sharp/Lineo for 2.4 kernels | |
10 | * Based on locomo.c | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/platform_device.h> | |
d6315949 | 22 | #include <linux/clk.h> |
25d6cbd8 | 23 | #include <linux/err.h> |
f024ff10 DB |
24 | #include <linux/mfd/core.h> |
25 | #include <linux/mfd/tmio.h> | |
d6315949 DB |
26 | #include <linux/mfd/tc6393xb.h> |
27 | #include <linux/gpio.h> | |
28 | ||
29 | #define SCR_REVID 0x08 /* b Revision ID */ | |
30 | #define SCR_ISR 0x50 /* b Interrupt Status */ | |
31 | #define SCR_IMR 0x52 /* b Interrupt Mask */ | |
32 | #define SCR_IRR 0x54 /* b Interrupt Routing */ | |
33 | #define SCR_GPER 0x60 /* w GP Enable */ | |
34 | #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */ | |
35 | #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */ | |
36 | #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */ | |
37 | #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */ | |
38 | #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */ | |
39 | #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */ | |
40 | #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */ | |
41 | #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */ | |
42 | #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */ | |
43 | #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */ | |
44 | #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */ | |
45 | #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */ | |
46 | #define SCR_CCR 0x98 /* w Clock Control */ | |
47 | #define SCR_PLL2CR 0x9a /* w PLL2 Control */ | |
48 | #define SCR_PLL1CR 0x9c /* l PLL1 Control */ | |
49 | #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */ | |
50 | #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */ | |
51 | #define SCR_FER 0xe0 /* b Function Enable */ | |
52 | #define SCR_MCR 0xe4 /* w Mode Control */ | |
53 | #define SCR_CONFIG 0xfc /* b Configuration Control */ | |
54 | #define SCR_DEBUG 0xff /* b Debug */ | |
55 | ||
56 | #define SCR_CCR_CK32K BIT(0) | |
57 | #define SCR_CCR_USBCK BIT(1) | |
58 | #define SCR_CCR_UNK1 BIT(4) | |
59 | #define SCR_CCR_MCLK_MASK (7 << 8) | |
60 | #define SCR_CCR_MCLK_OFF (0 << 8) | |
61 | #define SCR_CCR_MCLK_12 (1 << 8) | |
62 | #define SCR_CCR_MCLK_24 (2 << 8) | |
63 | #define SCR_CCR_MCLK_48 (3 << 8) | |
64 | #define SCR_CCR_HCLK_MASK (3 << 12) | |
65 | #define SCR_CCR_HCLK_24 (0 << 12) | |
66 | #define SCR_CCR_HCLK_48 (1 << 12) | |
67 | ||
68 | #define SCR_FER_USBEN BIT(0) /* USB host enable */ | |
69 | #define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */ | |
70 | #define SCR_FER_SLCDEN BIT(2) /* SLCD enable */ | |
71 | ||
72 | #define SCR_MCR_RDY_MASK (3 << 0) | |
73 | #define SCR_MCR_RDY_OPENDRAIN (0 << 0) | |
74 | #define SCR_MCR_RDY_TRISTATE (1 << 0) | |
75 | #define SCR_MCR_RDY_PUSHPULL (2 << 0) | |
76 | #define SCR_MCR_RDY_UNK BIT(2) | |
77 | #define SCR_MCR_RDY_EN BIT(3) | |
78 | #define SCR_MCR_INT_MASK (3 << 4) | |
79 | #define SCR_MCR_INT_OPENDRAIN (0 << 4) | |
80 | #define SCR_MCR_INT_TRISTATE (1 << 4) | |
81 | #define SCR_MCR_INT_PUSHPULL (2 << 4) | |
82 | #define SCR_MCR_INT_UNK BIT(6) | |
83 | #define SCR_MCR_INT_EN BIT(7) | |
84 | /* bits 8 - 16 are unknown */ | |
85 | ||
86 | #define TC_GPIO_BIT(i) (1 << (i & 0x7)) | |
87 | ||
88 | /*--------------------------------------------------------------------------*/ | |
89 | ||
90 | struct tc6393xb { | |
91 | void __iomem *scr; | |
92 | ||
93 | struct gpio_chip gpio; | |
94 | ||
95 | struct clk *clk; /* 3,6 Mhz */ | |
96 | ||
97 | spinlock_t lock; /* protects RMW cycles */ | |
98 | ||
99 | struct { | |
100 | u8 fer; | |
101 | u16 ccr; | |
102 | u8 gpi_bcr[3]; | |
103 | u8 gpo_dsr[3]; | |
104 | u8 gpo_doecr[3]; | |
105 | } suspend_state; | |
106 | ||
107 | struct resource rscr; | |
108 | struct resource *iomem; | |
109 | int irq; | |
110 | int irq_base; | |
111 | }; | |
112 | ||
f024ff10 DB |
113 | enum { |
114 | TC6393XB_CELL_NAND, | |
25d6cbd8 | 115 | TC6393XB_CELL_MMC, |
51a55623 | 116 | TC6393XB_CELL_OHCI, |
9e78cfe5 | 117 | TC6393XB_CELL_FB, |
f024ff10 DB |
118 | }; |
119 | ||
120 | /*--------------------------------------------------------------------------*/ | |
121 | ||
122 | static int tc6393xb_nand_enable(struct platform_device *nand) | |
123 | { | |
124 | struct platform_device *dev = to_platform_device(nand->dev.parent); | |
125 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
126 | unsigned long flags; | |
127 | ||
128 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
129 | ||
130 | /* SMD buffer on */ | |
131 | dev_dbg(&dev->dev, "SMD buffer on\n"); | |
25d6cbd8 | 132 | tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1)); |
f024ff10 DB |
133 | |
134 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | static struct resource __devinitdata tc6393xb_nand_resources[] = { | |
140 | { | |
25d6cbd8 IM |
141 | .start = 0x1000, |
142 | .end = 0x1007, | |
f024ff10 DB |
143 | .flags = IORESOURCE_MEM, |
144 | }, | |
145 | { | |
25d6cbd8 IM |
146 | .start = 0x0100, |
147 | .end = 0x01ff, | |
f024ff10 DB |
148 | .flags = IORESOURCE_MEM, |
149 | }, | |
150 | { | |
f024ff10 DB |
151 | .start = IRQ_TC6393_NAND, |
152 | .end = IRQ_TC6393_NAND, | |
153 | .flags = IORESOURCE_IRQ, | |
154 | }, | |
155 | }; | |
156 | ||
25d6cbd8 IM |
157 | static struct resource __devinitdata tc6393xb_mmc_resources[] = { |
158 | { | |
159 | .start = 0x800, | |
160 | .end = 0x9ff, | |
161 | .flags = IORESOURCE_MEM, | |
162 | }, | |
25d6cbd8 IM |
163 | { |
164 | .start = IRQ_TC6393_MMC, | |
165 | .end = IRQ_TC6393_MMC, | |
166 | .flags = IORESOURCE_IRQ, | |
167 | }, | |
168 | }; | |
169 | ||
3446d4bb | 170 | static const struct resource tc6393xb_ohci_resources[] = { |
51a55623 DB |
171 | { |
172 | .start = 0x3000, | |
173 | .end = 0x31ff, | |
174 | .flags = IORESOURCE_MEM, | |
175 | }, | |
176 | { | |
177 | .start = 0x0300, | |
178 | .end = 0x03ff, | |
179 | .flags = IORESOURCE_MEM, | |
180 | }, | |
181 | { | |
182 | .start = 0x010000, | |
183 | .end = 0x017fff, | |
184 | .flags = IORESOURCE_MEM, | |
185 | }, | |
186 | { | |
187 | .start = 0x018000, | |
188 | .end = 0x01ffff, | |
189 | .flags = IORESOURCE_MEM, | |
190 | }, | |
191 | { | |
192 | .start = IRQ_TC6393_OHCI, | |
193 | .end = IRQ_TC6393_OHCI, | |
194 | .flags = IORESOURCE_IRQ, | |
195 | }, | |
196 | }; | |
197 | ||
9e78cfe5 DB |
198 | static struct resource __devinitdata tc6393xb_fb_resources[] = { |
199 | { | |
200 | .start = 0x5000, | |
201 | .end = 0x51ff, | |
202 | .flags = IORESOURCE_MEM, | |
203 | }, | |
204 | { | |
205 | .start = 0x0500, | |
206 | .end = 0x05ff, | |
207 | .flags = IORESOURCE_MEM, | |
208 | }, | |
209 | { | |
210 | .start = 0x100000, | |
211 | .end = 0x1fffff, | |
212 | .flags = IORESOURCE_MEM, | |
213 | }, | |
214 | { | |
215 | .start = IRQ_TC6393_FB, | |
216 | .end = IRQ_TC6393_FB, | |
217 | .flags = IORESOURCE_IRQ, | |
218 | }, | |
219 | }; | |
220 | ||
51a55623 DB |
221 | static int tc6393xb_ohci_enable(struct platform_device *dev) |
222 | { | |
223 | struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent); | |
224 | unsigned long flags; | |
225 | u16 ccr; | |
226 | u8 fer; | |
227 | ||
228 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
229 | ||
230 | ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR); | |
231 | ccr |= SCR_CCR_USBCK; | |
232 | tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR); | |
233 | ||
234 | fer = tmio_ioread8(tc6393xb->scr + SCR_FER); | |
235 | fer |= SCR_FER_USBEN; | |
236 | tmio_iowrite8(fer, tc6393xb->scr + SCR_FER); | |
237 | ||
238 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
243 | static int tc6393xb_ohci_disable(struct platform_device *dev) | |
244 | { | |
245 | struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent); | |
246 | unsigned long flags; | |
247 | u16 ccr; | |
248 | u8 fer; | |
249 | ||
250 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
251 | ||
252 | fer = tmio_ioread8(tc6393xb->scr + SCR_FER); | |
253 | fer &= ~SCR_FER_USBEN; | |
254 | tmio_iowrite8(fer, tc6393xb->scr + SCR_FER); | |
255 | ||
256 | ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR); | |
257 | ccr &= ~SCR_CCR_USBCK; | |
258 | tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR); | |
259 | ||
260 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
9e78cfe5 DB |
265 | static int tc6393xb_fb_enable(struct platform_device *dev) |
266 | { | |
267 | struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent); | |
268 | unsigned long flags; | |
269 | u16 ccr; | |
270 | ||
271 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
272 | ||
273 | ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR); | |
274 | ccr &= ~SCR_CCR_MCLK_MASK; | |
275 | ccr |= SCR_CCR_MCLK_48; | |
276 | tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR); | |
277 | ||
278 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
283 | static int tc6393xb_fb_disable(struct platform_device *dev) | |
284 | { | |
285 | struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent); | |
286 | unsigned long flags; | |
287 | u16 ccr; | |
288 | ||
289 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
290 | ||
291 | ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR); | |
292 | ccr &= ~SCR_CCR_MCLK_MASK; | |
293 | ccr |= SCR_CCR_MCLK_OFF; | |
294 | tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR); | |
295 | ||
296 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
301 | int tc6393xb_lcd_set_power(struct platform_device *fb, bool on) | |
302 | { | |
303 | struct platform_device *dev = to_platform_device(fb->dev.parent); | |
304 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
305 | u8 fer; | |
306 | unsigned long flags; | |
307 | ||
308 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
309 | ||
310 | fer = ioread8(tc6393xb->scr + SCR_FER); | |
311 | if (on) | |
312 | fer |= SCR_FER_SLCDEN; | |
313 | else | |
314 | fer &= ~SCR_FER_SLCDEN; | |
315 | iowrite8(fer, tc6393xb->scr + SCR_FER); | |
316 | ||
317 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
318 | ||
319 | return 0; | |
320 | } | |
321 | EXPORT_SYMBOL(tc6393xb_lcd_set_power); | |
322 | ||
323 | int tc6393xb_lcd_mode(struct platform_device *fb, | |
324 | const struct fb_videomode *mode) { | |
325 | struct platform_device *dev = to_platform_device(fb->dev.parent); | |
326 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
327 | unsigned long flags; | |
328 | ||
329 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
330 | ||
331 | iowrite16(mode->pixclock, tc6393xb->scr + SCR_PLL1CR + 0); | |
332 | iowrite16(mode->pixclock >> 16, tc6393xb->scr + SCR_PLL1CR + 2); | |
333 | ||
334 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
335 | ||
336 | return 0; | |
337 | } | |
338 | EXPORT_SYMBOL(tc6393xb_lcd_mode); | |
339 | ||
64e8867b IM |
340 | static int tc6393xb_mmc_enable(struct platform_device *mmc) |
341 | { | |
342 | struct platform_device *dev = to_platform_device(mmc->dev.parent); | |
343 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
344 | ||
345 | tmio_core_mmc_enable(tc6393xb->scr + 0x200, 0, | |
346 | tc6393xb_mmc_resources[0].start & 0xfffe); | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
351 | static int tc6393xb_mmc_resume(struct platform_device *mmc) | |
352 | { | |
353 | struct platform_device *dev = to_platform_device(mmc->dev.parent); | |
354 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
355 | ||
356 | tmio_core_mmc_resume(tc6393xb->scr + 0x200, 0, | |
357 | tc6393xb_mmc_resources[0].start & 0xfffe); | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static void tc6393xb_mmc_pwr(struct platform_device *mmc, int state) | |
363 | { | |
364 | struct platform_device *dev = to_platform_device(mmc->dev.parent); | |
365 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
366 | ||
367 | tmio_core_mmc_pwr(tc6393xb->scr + 0x200, 0, state); | |
368 | } | |
369 | ||
370 | static void tc6393xb_mmc_clk_div(struct platform_device *mmc, int state) | |
371 | { | |
372 | struct platform_device *dev = to_platform_device(mmc->dev.parent); | |
373 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
374 | ||
375 | tmio_core_mmc_clk_div(tc6393xb->scr + 0x200, 0, state); | |
376 | } | |
377 | ||
378 | static struct tmio_mmc_data tc6393xb_mmc_data = { | |
379 | .hclk = 24000000, | |
380 | .set_pwr = tc6393xb_mmc_pwr, | |
381 | .set_clk_div = tc6393xb_mmc_clk_div, | |
382 | }; | |
383 | ||
f024ff10 DB |
384 | static struct mfd_cell __devinitdata tc6393xb_cells[] = { |
385 | [TC6393XB_CELL_NAND] = { | |
386 | .name = "tmio-nand", | |
387 | .enable = tc6393xb_nand_enable, | |
388 | .num_resources = ARRAY_SIZE(tc6393xb_nand_resources), | |
389 | .resources = tc6393xb_nand_resources, | |
390 | }, | |
25d6cbd8 IM |
391 | [TC6393XB_CELL_MMC] = { |
392 | .name = "tmio-mmc", | |
64e8867b IM |
393 | .enable = tc6393xb_mmc_enable, |
394 | .resume = tc6393xb_mmc_resume, | |
f0e46cc4 | 395 | .driver_data = &tc6393xb_mmc_data, |
25d6cbd8 IM |
396 | .num_resources = ARRAY_SIZE(tc6393xb_mmc_resources), |
397 | .resources = tc6393xb_mmc_resources, | |
398 | }, | |
51a55623 DB |
399 | [TC6393XB_CELL_OHCI] = { |
400 | .name = "tmio-ohci", | |
401 | .num_resources = ARRAY_SIZE(tc6393xb_ohci_resources), | |
402 | .resources = tc6393xb_ohci_resources, | |
403 | .enable = tc6393xb_ohci_enable, | |
404 | .suspend = tc6393xb_ohci_disable, | |
405 | .resume = tc6393xb_ohci_enable, | |
406 | .disable = tc6393xb_ohci_disable, | |
407 | }, | |
9e78cfe5 DB |
408 | [TC6393XB_CELL_FB] = { |
409 | .name = "tmio-fb", | |
410 | .num_resources = ARRAY_SIZE(tc6393xb_fb_resources), | |
411 | .resources = tc6393xb_fb_resources, | |
412 | .enable = tc6393xb_fb_enable, | |
413 | .suspend = tc6393xb_fb_disable, | |
414 | .resume = tc6393xb_fb_enable, | |
415 | .disable = tc6393xb_fb_disable, | |
416 | }, | |
f024ff10 DB |
417 | }; |
418 | ||
d6315949 DB |
419 | /*--------------------------------------------------------------------------*/ |
420 | ||
421 | static int tc6393xb_gpio_get(struct gpio_chip *chip, | |
422 | unsigned offset) | |
423 | { | |
424 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
425 | ||
426 | /* XXX: does dsr also represent inputs? */ | |
25d6cbd8 | 427 | return tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8)) |
d6315949 DB |
428 | & TC_GPIO_BIT(offset); |
429 | } | |
430 | ||
431 | static void __tc6393xb_gpio_set(struct gpio_chip *chip, | |
432 | unsigned offset, int value) | |
433 | { | |
434 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
435 | u8 dsr; | |
436 | ||
25d6cbd8 | 437 | dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8)); |
d6315949 DB |
438 | if (value) |
439 | dsr |= TC_GPIO_BIT(offset); | |
440 | else | |
441 | dsr &= ~TC_GPIO_BIT(offset); | |
442 | ||
25d6cbd8 | 443 | tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8)); |
d6315949 DB |
444 | } |
445 | ||
446 | static void tc6393xb_gpio_set(struct gpio_chip *chip, | |
447 | unsigned offset, int value) | |
448 | { | |
449 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
450 | unsigned long flags; | |
451 | ||
452 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
453 | ||
454 | __tc6393xb_gpio_set(chip, offset, value); | |
455 | ||
456 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
457 | } | |
458 | ||
459 | static int tc6393xb_gpio_direction_input(struct gpio_chip *chip, | |
460 | unsigned offset) | |
461 | { | |
462 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
463 | unsigned long flags; | |
464 | u8 doecr; | |
465 | ||
466 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
467 | ||
25d6cbd8 | 468 | doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); |
d6315949 | 469 | doecr &= ~TC_GPIO_BIT(offset); |
25d6cbd8 | 470 | tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); |
d6315949 DB |
471 | |
472 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
477 | static int tc6393xb_gpio_direction_output(struct gpio_chip *chip, | |
478 | unsigned offset, int value) | |
479 | { | |
480 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
481 | unsigned long flags; | |
482 | u8 doecr; | |
483 | ||
484 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
485 | ||
486 | __tc6393xb_gpio_set(chip, offset, value); | |
487 | ||
25d6cbd8 | 488 | doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); |
d6315949 | 489 | doecr |= TC_GPIO_BIT(offset); |
25d6cbd8 | 490 | tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); |
d6315949 DB |
491 | |
492 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
497 | static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base) | |
498 | { | |
499 | tc6393xb->gpio.label = "tc6393xb"; | |
500 | tc6393xb->gpio.base = gpio_base; | |
501 | tc6393xb->gpio.ngpio = 16; | |
502 | tc6393xb->gpio.set = tc6393xb_gpio_set; | |
503 | tc6393xb->gpio.get = tc6393xb_gpio_get; | |
504 | tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input; | |
505 | tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output; | |
506 | ||
507 | return gpiochip_add(&tc6393xb->gpio); | |
508 | } | |
509 | ||
510 | /*--------------------------------------------------------------------------*/ | |
511 | ||
512 | static void | |
513 | tc6393xb_irq(unsigned int irq, struct irq_desc *desc) | |
514 | { | |
515 | struct tc6393xb *tc6393xb = get_irq_data(irq); | |
516 | unsigned int isr; | |
517 | unsigned int i, irq_base; | |
518 | ||
519 | irq_base = tc6393xb->irq_base; | |
520 | ||
25d6cbd8 IM |
521 | while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) & |
522 | ~tmio_ioread8(tc6393xb->scr + SCR_IMR))) | |
d6315949 DB |
523 | for (i = 0; i < TC6393XB_NR_IRQS; i++) { |
524 | if (isr & (1 << i)) | |
525 | generic_handle_irq(irq_base + i); | |
526 | } | |
527 | } | |
528 | ||
529 | static void tc6393xb_irq_ack(unsigned int irq) | |
530 | { | |
531 | } | |
532 | ||
533 | static void tc6393xb_irq_mask(unsigned int irq) | |
534 | { | |
535 | struct tc6393xb *tc6393xb = get_irq_chip_data(irq); | |
536 | unsigned long flags; | |
537 | u8 imr; | |
538 | ||
539 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
25d6cbd8 | 540 | imr = tmio_ioread8(tc6393xb->scr + SCR_IMR); |
d6315949 | 541 | imr |= 1 << (irq - tc6393xb->irq_base); |
25d6cbd8 | 542 | tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR); |
d6315949 DB |
543 | spin_unlock_irqrestore(&tc6393xb->lock, flags); |
544 | } | |
545 | ||
546 | static void tc6393xb_irq_unmask(unsigned int irq) | |
547 | { | |
548 | struct tc6393xb *tc6393xb = get_irq_chip_data(irq); | |
549 | unsigned long flags; | |
550 | u8 imr; | |
551 | ||
552 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
25d6cbd8 | 553 | imr = tmio_ioread8(tc6393xb->scr + SCR_IMR); |
d6315949 | 554 | imr &= ~(1 << (irq - tc6393xb->irq_base)); |
25d6cbd8 | 555 | tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR); |
d6315949 DB |
556 | spin_unlock_irqrestore(&tc6393xb->lock, flags); |
557 | } | |
558 | ||
559 | static struct irq_chip tc6393xb_chip = { | |
560 | .name = "tc6393xb", | |
561 | .ack = tc6393xb_irq_ack, | |
562 | .mask = tc6393xb_irq_mask, | |
563 | .unmask = tc6393xb_irq_unmask, | |
564 | }; | |
565 | ||
566 | static void tc6393xb_attach_irq(struct platform_device *dev) | |
567 | { | |
568 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
569 | unsigned int irq, irq_base; | |
570 | ||
571 | irq_base = tc6393xb->irq_base; | |
572 | ||
573 | for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) { | |
574 | set_irq_chip(irq, &tc6393xb_chip); | |
575 | set_irq_chip_data(irq, tc6393xb); | |
576 | set_irq_handler(irq, handle_edge_irq); | |
577 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
578 | } | |
579 | ||
6cab4860 | 580 | set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING); |
d6315949 DB |
581 | set_irq_data(tc6393xb->irq, tc6393xb); |
582 | set_irq_chained_handler(tc6393xb->irq, tc6393xb_irq); | |
583 | } | |
584 | ||
585 | static void tc6393xb_detach_irq(struct platform_device *dev) | |
586 | { | |
587 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
588 | unsigned int irq, irq_base; | |
589 | ||
590 | set_irq_chained_handler(tc6393xb->irq, NULL); | |
591 | set_irq_data(tc6393xb->irq, NULL); | |
592 | ||
593 | irq_base = tc6393xb->irq_base; | |
594 | ||
595 | for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) { | |
596 | set_irq_flags(irq, 0); | |
597 | set_irq_chip(irq, NULL); | |
598 | set_irq_chip_data(irq, NULL); | |
599 | } | |
600 | } | |
601 | ||
602 | /*--------------------------------------------------------------------------*/ | |
603 | ||
d6315949 DB |
604 | static int __devinit tc6393xb_probe(struct platform_device *dev) |
605 | { | |
606 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
607 | struct tc6393xb *tc6393xb; | |
25d6cbd8 IM |
608 | struct resource *iomem, *rscr; |
609 | int ret, temp; | |
d6315949 DB |
610 | |
611 | iomem = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
612 | if (!iomem) | |
613 | return -EINVAL; | |
614 | ||
615 | tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL); | |
616 | if (!tc6393xb) { | |
25d6cbd8 | 617 | ret = -ENOMEM; |
d6315949 DB |
618 | goto err_kzalloc; |
619 | } | |
620 | ||
621 | spin_lock_init(&tc6393xb->lock); | |
622 | ||
623 | platform_set_drvdata(dev, tc6393xb); | |
25d6cbd8 IM |
624 | |
625 | ret = platform_get_irq(dev, 0); | |
626 | if (ret >= 0) | |
627 | tc6393xb->irq = ret; | |
628 | else | |
629 | goto err_noirq; | |
630 | ||
d6315949 | 631 | tc6393xb->iomem = iomem; |
d6315949 DB |
632 | tc6393xb->irq_base = tcpd->irq_base; |
633 | ||
25d6cbd8 | 634 | tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI"); |
d6315949 | 635 | if (IS_ERR(tc6393xb->clk)) { |
25d6cbd8 | 636 | ret = PTR_ERR(tc6393xb->clk); |
d6315949 DB |
637 | goto err_clk_get; |
638 | } | |
639 | ||
640 | rscr = &tc6393xb->rscr; | |
641 | rscr->name = "tc6393xb-core"; | |
642 | rscr->start = iomem->start; | |
643 | rscr->end = iomem->start + 0xff; | |
644 | rscr->flags = IORESOURCE_MEM; | |
645 | ||
25d6cbd8 IM |
646 | ret = request_resource(iomem, rscr); |
647 | if (ret) | |
d6315949 DB |
648 | goto err_request_scr; |
649 | ||
1ecc09e7 | 650 | tc6393xb->scr = ioremap(rscr->start, resource_size(rscr)); |
d6315949 | 651 | if (!tc6393xb->scr) { |
25d6cbd8 | 652 | ret = -ENOMEM; |
d6315949 DB |
653 | goto err_ioremap; |
654 | } | |
655 | ||
25d6cbd8 IM |
656 | ret = clk_enable(tc6393xb->clk); |
657 | if (ret) | |
d6315949 DB |
658 | goto err_clk_enable; |
659 | ||
25d6cbd8 IM |
660 | ret = tcpd->enable(dev); |
661 | if (ret) | |
d6315949 DB |
662 | goto err_enable; |
663 | ||
f98a0bd0 DB |
664 | iowrite8(0, tc6393xb->scr + SCR_FER); |
665 | iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR); | |
666 | iowrite16(SCR_CCR_UNK1 | SCR_CCR_HCLK_48, | |
667 | tc6393xb->scr + SCR_CCR); | |
668 | iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN | | |
669 | SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN | | |
670 | BIT(15), tc6393xb->scr + SCR_MCR); | |
671 | iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER); | |
672 | iowrite8(0, tc6393xb->scr + SCR_IRR); | |
673 | iowrite8(0xbf, tc6393xb->scr + SCR_IMR); | |
d6315949 DB |
674 | |
675 | printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n", | |
25d6cbd8 | 676 | tmio_ioread8(tc6393xb->scr + SCR_REVID), |
d6315949 DB |
677 | (unsigned long) iomem->start, tc6393xb->irq); |
678 | ||
679 | tc6393xb->gpio.base = -1; | |
680 | ||
681 | if (tcpd->gpio_base >= 0) { | |
25d6cbd8 IM |
682 | ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base); |
683 | if (ret) | |
d6315949 DB |
684 | goto err_gpio_add; |
685 | } | |
686 | ||
25d6cbd8 | 687 | tc6393xb_attach_irq(dev); |
d6315949 | 688 | |
1c1b6ffc DB |
689 | if (tcpd->setup) { |
690 | ret = tcpd->setup(dev); | |
691 | if (ret) | |
692 | goto err_setup; | |
693 | } | |
694 | ||
f024ff10 | 695 | tc6393xb_cells[TC6393XB_CELL_NAND].driver_data = tcpd->nand_data; |
56edb58b MR |
696 | tc6393xb_cells[TC6393XB_CELL_NAND].platform_data = |
697 | &tc6393xb_cells[TC6393XB_CELL_NAND]; | |
698 | tc6393xb_cells[TC6393XB_CELL_NAND].data_size = | |
699 | sizeof(tc6393xb_cells[TC6393XB_CELL_NAND]); | |
9e78cfe5 | 700 | |
25d6cbd8 IM |
701 | tc6393xb_cells[TC6393XB_CELL_MMC].platform_data = |
702 | &tc6393xb_cells[TC6393XB_CELL_MMC]; | |
703 | tc6393xb_cells[TC6393XB_CELL_MMC].data_size = | |
704 | sizeof(tc6393xb_cells[TC6393XB_CELL_MMC]); | |
705 | ||
51a55623 DB |
706 | tc6393xb_cells[TC6393XB_CELL_OHCI].platform_data = |
707 | &tc6393xb_cells[TC6393XB_CELL_OHCI]; | |
708 | tc6393xb_cells[TC6393XB_CELL_OHCI].data_size = | |
709 | sizeof(tc6393xb_cells[TC6393XB_CELL_OHCI]); | |
710 | ||
9e78cfe5 DB |
711 | tc6393xb_cells[TC6393XB_CELL_FB].driver_data = tcpd->fb_data; |
712 | tc6393xb_cells[TC6393XB_CELL_FB].platform_data = | |
713 | &tc6393xb_cells[TC6393XB_CELL_FB]; | |
714 | tc6393xb_cells[TC6393XB_CELL_FB].data_size = | |
715 | sizeof(tc6393xb_cells[TC6393XB_CELL_FB]); | |
f024ff10 | 716 | |
25d6cbd8 | 717 | ret = mfd_add_devices(&dev->dev, dev->id, |
f024ff10 DB |
718 | tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells), |
719 | iomem, tcpd->irq_base); | |
720 | ||
25d6cbd8 IM |
721 | if (!ret) |
722 | return 0; | |
d6315949 | 723 | |
1c1b6ffc DB |
724 | if (tcpd->teardown) |
725 | tcpd->teardown(dev); | |
726 | ||
727 | err_setup: | |
25d6cbd8 | 728 | tc6393xb_detach_irq(dev); |
d6315949 DB |
729 | |
730 | err_gpio_add: | |
731 | if (tc6393xb->gpio.base != -1) | |
732 | temp = gpiochip_remove(&tc6393xb->gpio); | |
d6315949 DB |
733 | tcpd->disable(dev); |
734 | err_clk_enable: | |
735 | clk_disable(tc6393xb->clk); | |
736 | err_enable: | |
737 | iounmap(tc6393xb->scr); | |
738 | err_ioremap: | |
739 | release_resource(&tc6393xb->rscr); | |
740 | err_request_scr: | |
741 | clk_put(tc6393xb->clk); | |
25d6cbd8 | 742 | err_noirq: |
d6315949 DB |
743 | err_clk_get: |
744 | kfree(tc6393xb); | |
745 | err_kzalloc: | |
25d6cbd8 | 746 | return ret; |
d6315949 DB |
747 | } |
748 | ||
749 | static int __devexit tc6393xb_remove(struct platform_device *dev) | |
750 | { | |
751 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
752 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
753 | int ret; | |
754 | ||
424f525a | 755 | mfd_remove_devices(&dev->dev); |
1c1b6ffc DB |
756 | |
757 | if (tcpd->teardown) | |
758 | tcpd->teardown(dev); | |
759 | ||
25d6cbd8 | 760 | tc6393xb_detach_irq(dev); |
d6315949 DB |
761 | |
762 | if (tc6393xb->gpio.base != -1) { | |
763 | ret = gpiochip_remove(&tc6393xb->gpio); | |
764 | if (ret) { | |
765 | dev_err(&dev->dev, "Can't remove gpio chip: %d\n", ret); | |
766 | return ret; | |
767 | } | |
768 | } | |
769 | ||
770 | ret = tcpd->disable(dev); | |
d6315949 | 771 | clk_disable(tc6393xb->clk); |
d6315949 | 772 | iounmap(tc6393xb->scr); |
d6315949 | 773 | release_resource(&tc6393xb->rscr); |
d6315949 | 774 | platform_set_drvdata(dev, NULL); |
d6315949 | 775 | clk_put(tc6393xb->clk); |
d6315949 DB |
776 | kfree(tc6393xb); |
777 | ||
778 | return ret; | |
779 | } | |
780 | ||
781 | #ifdef CONFIG_PM | |
782 | static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state) | |
783 | { | |
784 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
785 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
25d6cbd8 | 786 | int i, ret; |
d6315949 DB |
787 | |
788 | tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR); | |
789 | tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER); | |
790 | ||
791 | for (i = 0; i < 3; i++) { | |
792 | tc6393xb->suspend_state.gpo_dsr[i] = | |
793 | ioread8(tc6393xb->scr + SCR_GPO_DSR(i)); | |
794 | tc6393xb->suspend_state.gpo_doecr[i] = | |
795 | ioread8(tc6393xb->scr + SCR_GPO_DOECR(i)); | |
796 | tc6393xb->suspend_state.gpi_bcr[i] = | |
797 | ioread8(tc6393xb->scr + SCR_GPI_BCR(i)); | |
798 | } | |
25d6cbd8 IM |
799 | ret = tcpd->suspend(dev); |
800 | clk_disable(tc6393xb->clk); | |
d6315949 | 801 | |
25d6cbd8 | 802 | return ret; |
d6315949 DB |
803 | } |
804 | ||
805 | static int tc6393xb_resume(struct platform_device *dev) | |
806 | { | |
807 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
25d6cbd8 IM |
808 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); |
809 | int ret; | |
f98a0bd0 | 810 | int i; |
25d6cbd8 IM |
811 | |
812 | clk_enable(tc6393xb->clk); | |
813 | ||
814 | ret = tcpd->resume(dev); | |
d6315949 DB |
815 | if (ret) |
816 | return ret; | |
817 | ||
f98a0bd0 DB |
818 | if (!tcpd->resume_restore) |
819 | return 0; | |
820 | ||
821 | iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER); | |
822 | iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR); | |
823 | iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR); | |
824 | iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN | | |
825 | SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN | | |
826 | BIT(15), tc6393xb->scr + SCR_MCR); | |
827 | iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER); | |
828 | iowrite8(0, tc6393xb->scr + SCR_IRR); | |
829 | iowrite8(0xbf, tc6393xb->scr + SCR_IMR); | |
830 | ||
831 | for (i = 0; i < 3; i++) { | |
832 | iowrite8(tc6393xb->suspend_state.gpo_dsr[i], | |
833 | tc6393xb->scr + SCR_GPO_DSR(i)); | |
834 | iowrite8(tc6393xb->suspend_state.gpo_doecr[i], | |
835 | tc6393xb->scr + SCR_GPO_DOECR(i)); | |
836 | iowrite8(tc6393xb->suspend_state.gpi_bcr[i], | |
837 | tc6393xb->scr + SCR_GPI_BCR(i)); | |
838 | } | |
839 | ||
840 | return 0; | |
d6315949 DB |
841 | } |
842 | #else | |
843 | #define tc6393xb_suspend NULL | |
844 | #define tc6393xb_resume NULL | |
845 | #endif | |
846 | ||
847 | static struct platform_driver tc6393xb_driver = { | |
848 | .probe = tc6393xb_probe, | |
849 | .remove = __devexit_p(tc6393xb_remove), | |
850 | .suspend = tc6393xb_suspend, | |
851 | .resume = tc6393xb_resume, | |
852 | ||
853 | .driver = { | |
854 | .name = "tc6393xb", | |
855 | .owner = THIS_MODULE, | |
856 | }, | |
857 | }; | |
858 | ||
859 | static int __init tc6393xb_init(void) | |
860 | { | |
861 | return platform_driver_register(&tc6393xb_driver); | |
862 | } | |
863 | ||
864 | static void __exit tc6393xb_exit(void) | |
865 | { | |
866 | platform_driver_unregister(&tc6393xb_driver); | |
867 | } | |
868 | ||
869 | subsys_initcall(tc6393xb_init); | |
870 | module_exit(tc6393xb_exit); | |
871 | ||
25d6cbd8 | 872 | MODULE_LICENSE("GPL v2"); |
d6315949 DB |
873 | MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer"); |
874 | MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller"); | |
875 | MODULE_ALIAS("platform:tc6393xb"); | |
64e8867b | 876 |