[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / ti_am335x_tscadc.c

/*
 * TI Touch Screen / ADC MFD driver
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/sched.h>

#include <linux/mfd/ti_am335x_tscadc.h>

static const struct regmap_config tscadc_regmap_config = {
	.name = "ti_tscadc",
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
};

void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tscadc, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&tscadc->reg_lock, flags);
	tscadc->reg_se_cache |= val;
	if (tscadc->adc_waiting)
		wake_up(&tscadc->reg_se_wait);
	else if (!tscadc->adc_in_use)
		regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);

	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);

static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tscadc)
{
	DEFINE_WAIT(wait);
	u32 reg;

	regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
	if (reg & SEQ_STATUS) {
		tscadc->adc_waiting = true;
		prepare_to_wait(&tscadc->reg_se_wait, &wait,
				TASK_UNINTERRUPTIBLE);
		spin_unlock_irq(&tscadc->reg_lock);

		schedule();

		spin_lock_irq(&tscadc->reg_lock);
		finish_wait(&tscadc->reg_se_wait, &wait);

		/*
		 * Sequencer should either be idle or
		 * busy applying the charge step.
		 */
		regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
		WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP));
		tscadc->adc_waiting = false;
	}
	tscadc->adc_in_use = true;
}

void am335x_tsc_se_set_once(struct ti_tscadc_dev *tscadc, u32 val)
{
	spin_lock_irq(&tscadc->reg_lock);
	am335x_tscadc_need_adc(tscadc);

	regmap_write(tscadc->regmap, REG_SE, val);
	spin_unlock_irq(&tscadc->reg_lock);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);

void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tscadc)
{
	unsigned long flags;

	spin_lock_irqsave(&tscadc->reg_lock, flags);
	tscadc->adc_in_use = false;
	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);

void am335x_tsc_se_clr(struct ti_tscadc_dev *tscadc, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&tscadc->reg_lock, flags);
	tscadc->reg_se_cache &= ~val;
	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);

static void tscadc_idle_config(struct ti_tscadc_dev *tscadc)
{
	unsigned int idleconfig;

	idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM |
			STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN;

	regmap_write(tscadc->regmap, REG_IDLECONFIG, idleconfig);
}

static	int ti_tscadc_probe(struct platform_device *pdev)
{
	struct ti_tscadc_dev	*tscadc;
	struct resource		*res;
	struct clk		*clk;
	struct device_node	*node = pdev->dev.of_node;
	struct mfd_cell		*cell;
	struct property         *prop;
	const __be32            *cur;
	u32			val;
	int			err, ctrl;
	int			clock_rate;
	int			tsc_wires = 0, adc_channels = 0, total_channels;
	int			readouts = 0;

	if (!pdev->dev.of_node) {
		dev_err(&pdev->dev, "Could not find valid DT data.\n");
		return -EINVAL;
	}

	node = of_get_child_by_name(pdev->dev.of_node, "tsc");
	of_property_read_u32(node, "ti,wires", &tsc_wires);
	of_property_read_u32(node, "ti,coordiante-readouts", &readouts);

	node = of_get_child_by_name(pdev->dev.of_node, "adc");
	of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
		adc_channels++;
		if (val > 7) {
			dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
					val);
			return -EINVAL;
		}
	}
	total_channels = tsc_wires + adc_channels;
	if (total_channels > 8) {
		dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
		return -EINVAL;
	}
	if (total_channels == 0) {
		dev_err(&pdev->dev, "Need atleast one channel.\n");
		return -EINVAL;
	}

	if (readouts * 2 + 2 + adc_channels > 16) {
		dev_err(&pdev->dev, "Too many step configurations requested\n");
		return -EINVAL;
	}

	/* Allocate memory for device */
	tscadc = devm_kzalloc(&pdev->dev, sizeof(*tscadc), GFP_KERNEL);
	if (!tscadc) {
		dev_err(&pdev->dev, "failed to allocate memory.\n");
		return -ENOMEM;
	}
	tscadc->dev = &pdev->dev;

	err = platform_get_irq(pdev, 0);
	if (err < 0) {
		dev_err(&pdev->dev, "no irq ID is specified.\n");
		goto ret;
	} else
		tscadc->irq = err;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	tscadc->tscadc_phys_base = res->start;
	tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(tscadc->tscadc_base))
		return PTR_ERR(tscadc->tscadc_base);

	tscadc->regmap = devm_regmap_init_mmio(&pdev->dev,
			tscadc->tscadc_base, &tscadc_regmap_config);
	if (IS_ERR(tscadc->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		err = PTR_ERR(tscadc->regmap);
		goto ret;
	}

	spin_lock_init(&tscadc->reg_lock);
	init_waitqueue_head(&tscadc->reg_se_wait);

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	/*
	 * The TSC_ADC_Subsystem has 2 clock domains
	 * OCP_CLK and ADC_CLK.
	 * The ADC clock is expected to run at target of 3MHz,
	 * and expected to capture 12-bit data at a rate of 200 KSPS.
	 * The TSC_ADC_SS controller design assumes the OCP clock is
	 * at least 6x faster than the ADC clock.
	 */
	clk = clk_get(&pdev->dev, "adc_tsc_fck");
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get TSC fck\n");
		err = PTR_ERR(clk);
		goto err_disable_clk;
	}
	clock_rate = clk_get_rate(clk);
	clk_put(clk);
	tscadc->clk_div = clock_rate / ADC_CLK;

	/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
	tscadc->clk_div--;
	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);

	/* Set the control register bits */
	ctrl = CNTRLREG_STEPCONFIGWRT |	CNTRLREG_STEPID;
	regmap_write(tscadc->regmap, REG_CTRL, ctrl);

	/* Set register bits for Idle Config Mode */
	if (tsc_wires > 0) {
		tscadc->tsc_wires = tsc_wires;
		if (tsc_wires == 5)
			ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
		else
			ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
		tscadc_idle_config(tscadc);
	}

	/* Enable the TSC module enable bit */
	ctrl |= CNTRLREG_TSCSSENB;
	regmap_write(tscadc->regmap, REG_CTRL, ctrl);

	tscadc->used_cells = 0;
	tscadc->tsc_cell = -1;
	tscadc->adc_cell = -1;

	/* TSC Cell */
	if (tsc_wires > 0) {
		tscadc->tsc_cell = tscadc->used_cells;
		cell = &tscadc->cells[tscadc->used_cells++];
		cell->name = "TI-am335x-tsc";
		cell->of_compatible = "ti,am3359-tsc";
		cell->platform_data = &tscadc;
		cell->pdata_size = sizeof(tscadc);
	}

	/* ADC Cell */
	if (adc_channels > 0) {
		tscadc->adc_cell = tscadc->used_cells;
		cell = &tscadc->cells[tscadc->used_cells++];
		cell->name = "TI-am335x-adc";
		cell->of_compatible = "ti,am3359-adc";
		cell->platform_data = &tscadc;
		cell->pdata_size = sizeof(tscadc);
	}

	err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
			tscadc->used_cells, NULL, 0, NULL);
	if (err < 0)
		goto err_disable_clk;

	device_init_wakeup(&pdev->dev, true);
	platform_set_drvdata(pdev, tscadc);
	return 0;

err_disable_clk:
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
ret:
	return err;
}

static int ti_tscadc_remove(struct platform_device *pdev)
{
	struct ti_tscadc_dev	*tscadc = platform_get_drvdata(pdev);

	regmap_write(tscadc->regmap, REG_SE, 0x00);

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	mfd_remove_devices(tscadc->dev);

	return 0;
}

static int __maybe_unused tscadc_suspend(struct device *dev)
{
	struct ti_tscadc_dev	*tscadc = dev_get_drvdata(dev);

	regmap_write(tscadc->regmap, REG_SE, 0x00);
	pm_runtime_put_sync(dev);

	return 0;
}

static int __maybe_unused tscadc_resume(struct device *dev)
{
	struct ti_tscadc_dev	*tscadc = dev_get_drvdata(dev);
	u32 ctrl;

	pm_runtime_get_sync(dev);

	/* context restore */
	ctrl = CNTRLREG_STEPCONFIGWRT |	CNTRLREG_STEPID;
	regmap_write(tscadc->regmap, REG_CTRL, ctrl);

	if (tscadc->tsc_cell != -1) {
		if (tscadc->tsc_wires == 5)
			ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
		else
			ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
		tscadc_idle_config(tscadc);
	}
	ctrl |= CNTRLREG_TSCSSENB;
	regmap_write(tscadc->regmap, REG_CTRL, ctrl);

	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);

	return 0;
}

static SIMPLE_DEV_PM_OPS(tscadc_pm_ops, tscadc_suspend, tscadc_resume);

static const struct of_device_id ti_tscadc_dt_ids[] = {
	{ .compatible = "ti,am3359-tscadc", },
	{ }
};
MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);

static struct platform_driver ti_tscadc_driver = {
	.driver = {
		.name   = "ti_am3359-tscadc",
		.pm	= &tscadc_pm_ops,
		.of_match_table = ti_tscadc_dt_ids,
	},
	.probe	= ti_tscadc_probe,
	.remove	= ti_tscadc_remove,

};

module_platform_driver(ti_tscadc_driver);

MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
01636eb9 PR	1	/*
	2	* TI Touch Screen / ADC MFD driver
	3	*
	4	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation version 2.
	9	*
	10	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	11	* kind, whether express or implied; without even the implied warranty
	12	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/module.h>
01636eb9 PR	17	#include <linux/slab.h>
	18	#include <linux/err.h>
	19	#include <linux/io.h>
	20	#include <linux/clk.h>
	21	#include <linux/regmap.h>
	22	#include <linux/mfd/core.h>
	23	#include <linux/pm_runtime.h>
a6543a1c PR	24	#include <linux/of.h>
a6543a1c PR	25	#include <linux/of_device.h>
7ca6740c	26	#include <linux/sched.h>
01636eb9 PR	27
	28	#include <linux/mfd/ti_am335x_tscadc.h>
	29
01636eb9 PR	30	static const struct regmap_config tscadc_regmap_config = {
	31	.name = "ti_tscadc",
	32	.reg_bits = 32,
	33	.reg_stride = 4,
	34	.val_bits = 32,
	35	};
	36
a318b7d0	37	void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tscadc, u32 val)
abeccee4	38	{
317b2099 SAS	39	unsigned long flags;
317b2099 SAS	40
a318b7d0 AD	41	spin_lock_irqsave(&tscadc->reg_lock, flags);
	42	tscadc->reg_se_cache \|= val;
	43	if (tscadc->adc_waiting)
	44	wake_up(&tscadc->reg_se_wait);
	45	else if (!tscadc->adc_in_use)
0d3a7cce	46	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
7ca6740c	47
a318b7d0	48	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
abeccee4	49	}
7e170c6e SAS	50	EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);
7e170c6e SAS	51
a318b7d0	52	static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tscadc)
7ca6740c SAS	53	{
	54	DEFINE_WAIT(wait);
	55	u32 reg;
	56
0d3a7cce	57	regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
7ca6740c	58	if (reg & SEQ_STATUS) {
a318b7d0 AD	59	tscadc->adc_waiting = true;
a318b7d0 AD	60	prepare_to_wait(&tscadc->reg_se_wait, &wait,
7ca6740c	61	TASK_UNINTERRUPTIBLE);
a318b7d0	62	spin_unlock_irq(&tscadc->reg_lock);
7ca6740c SAS	63
	64	schedule();
	65
a318b7d0 AD	66	spin_lock_irq(&tscadc->reg_lock);
a318b7d0 AD	67	finish_wait(&tscadc->reg_se_wait, &wait);
7ca6740c	68
b10848e6 V	69	/*
	70	* Sequencer should either be idle or
	71	* busy applying the charge step.
	72	*/
0d3a7cce	73	regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
b10848e6	74	WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP));
a318b7d0	75	tscadc->adc_waiting = false;
7ca6740c	76	}
a318b7d0	77	tscadc->adc_in_use = true;
7ca6740c SAS	78	}
7ca6740c SAS	79
a318b7d0	80	void am335x_tsc_se_set_once(struct ti_tscadc_dev *tscadc, u32 val)
7ca6740c	81	{
a318b7d0 AD	82	spin_lock_irq(&tscadc->reg_lock);
a318b7d0 AD	83	am335x_tscadc_need_adc(tscadc);
7ca6740c	84
0d3a7cce	85	regmap_write(tscadc->regmap, REG_SE, val);
a318b7d0	86	spin_unlock_irq(&tscadc->reg_lock);
7ca6740c SAS	87	}
	88	EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);
	89
a318b7d0	90	void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tscadc)
7e170c6e SAS	91	{
	92	unsigned long flags;
	93
a318b7d0 AD	94	spin_lock_irqsave(&tscadc->reg_lock, flags);
a318b7d0 AD	95	tscadc->adc_in_use = false;
0d3a7cce	96	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
a318b7d0	97	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
7e170c6e	98	}
7ca6740c	99	EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);
abeccee4	100
a318b7d0	101	void am335x_tsc_se_clr(struct ti_tscadc_dev *tscadc, u32 val)
abeccee4	102	{
317b2099 SAS	103	unsigned long flags;
317b2099 SAS	104
a318b7d0 AD	105	spin_lock_irqsave(&tscadc->reg_lock, flags);
a318b7d0 AD	106	tscadc->reg_se_cache &= ~val;
0d3a7cce	107	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
a318b7d0	108	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
abeccee4 PR	109	}
	110	EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
	111
a318b7d0	112	static void tscadc_idle_config(struct ti_tscadc_dev *tscadc)
01636eb9 PR	113	{
	114	unsigned int idleconfig;
	115
	116	idleconfig = STEPCONFIG_YNN \| STEPCONFIG_INM_ADCREFM \|
	117	STEPCONFIG_INP_ADCREFM \| STEPCONFIG_YPN;
	118
0d3a7cce	119	regmap_write(tscadc->regmap, REG_IDLECONFIG, idleconfig);
01636eb9 PR	120	}
01636eb9 PR	121
612b95cd	122	static int ti_tscadc_probe(struct platform_device *pdev)
01636eb9 PR	123	{
	124	struct ti_tscadc_dev *tscadc;
	125	struct resource *res;
	126	struct clk *clk;
a6543a1c	127	struct device_node *node = pdev->dev.of_node;
2b99bafa	128	struct mfd_cell *cell;
18926ede SAS	129	struct property *prop;
	130	const __be32 *cur;
	131	u32 val;
01636eb9	132	int err, ctrl;
e90f8754	133	int clock_rate;
a6543a1c	134	int tsc_wires = 0, adc_channels = 0, total_channels;
18926ede	135	int readouts = 0;
01636eb9	136
9e5775f3 SAS	137	if (!pdev->dev.of_node) {
9e5775f3 SAS	138	dev_err(&pdev->dev, "Could not find valid DT data.\n");
01636eb9 PR	139	return -EINVAL;
	140	}
	141
9e5775f3 SAS	142	node = of_get_child_by_name(pdev->dev.of_node, "tsc");
9e5775f3 SAS	143	of_property_read_u32(node, "ti,wires", &tsc_wires);
18926ede	144	of_property_read_u32(node, "ti,coordiante-readouts", &readouts);
a6543a1c	145
9e5775f3	146	node = of_get_child_by_name(pdev->dev.of_node, "adc");
18926ede SAS	147	of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
	148	adc_channels++;
	149	if (val > 7) {
	150	dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
	151	val);
	152	return -EINVAL;
	153	}
	154	}
5e53a69b	155	total_channels = tsc_wires + adc_channels;
5e53a69b PR	156	if (total_channels > 8) {
	157	dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
	158	return -EINVAL;
	159	}
24d5c82f PA	160	if (total_channels == 0) {
	161	dev_err(&pdev->dev, "Need atleast one channel.\n");
	162	return -EINVAL;
	163	}
2b99bafa	164
18926ede SAS	165	if (readouts * 2 + 2 + adc_channels > 16) {
	166	dev_err(&pdev->dev, "Too many step configurations requested\n");
	167	return -EINVAL;
	168	}
	169
01636eb9	170	/* Allocate memory for device */
dea1c703	171	tscadc = devm_kzalloc(&pdev->dev, sizeof(*tscadc), GFP_KERNEL);
01636eb9 PR	172	if (!tscadc) {
	173	dev_err(&pdev->dev, "failed to allocate memory.\n");
	174	return -ENOMEM;
	175	}
	176	tscadc->dev = &pdev->dev;
3c39c9c6 PR	177
	178	err = platform_get_irq(pdev, 0);
	179	if (err < 0) {
	180	dev_err(&pdev->dev, "no irq ID is specified.\n");
	181	goto ret;
	182	} else
	183	tscadc->irq = err;
01636eb9	184
924ff918	185	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c9329d86	186	tscadc->tscadc_phys_base = res->start;
924ff918 JH	187	tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res);
	188	if (IS_ERR(tscadc->tscadc_base))
	189	return PTR_ERR(tscadc->tscadc_base);
01636eb9	190
0d3a7cce	191	tscadc->regmap = devm_regmap_init_mmio(&pdev->dev,
01636eb9	192	tscadc->tscadc_base, &tscadc_regmap_config);
0d3a7cce	193	if (IS_ERR(tscadc->regmap)) {
01636eb9	194	dev_err(&pdev->dev, "regmap init failed\n");
0d3a7cce	195	err = PTR_ERR(tscadc->regmap);
3c39c9c6	196	goto ret;
01636eb9 PR	197	}
01636eb9 PR	198
abeccee4	199	spin_lock_init(&tscadc->reg_lock);
7ca6740c SAS	200	init_waitqueue_head(&tscadc->reg_se_wait);
7ca6740c SAS	201
01636eb9 PR	202	pm_runtime_enable(&pdev->dev);
	203	pm_runtime_get_sync(&pdev->dev);
	204
	205	/*
	206	* The TSC_ADC_Subsystem has 2 clock domains
	207	* OCP_CLK and ADC_CLK.
	208	* The ADC clock is expected to run at target of 3MHz,
	209	* and expected to capture 12-bit data at a rate of 200 KSPS.
	210	* The TSC_ADC_SS controller design assumes the OCP clock is
	211	* at least 6x faster than the ADC clock.
	212	*/
	213	clk = clk_get(&pdev->dev, "adc_tsc_fck");
	214	if (IS_ERR(clk)) {
	215	dev_err(&pdev->dev, "failed to get TSC fck\n");
	216	err = PTR_ERR(clk);
	217	goto err_disable_clk;
	218	}
	219	clock_rate = clk_get_rate(clk);
	220	clk_put(clk);
e90f8754	221	tscadc->clk_div = clock_rate / ADC_CLK;
efe3126a	222
01636eb9	223	/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
e90f8754	224	tscadc->clk_div--;
0d3a7cce	225	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);
01636eb9 PR	226
01636eb9 PR	227	/* Set the control register bits */
f0933a60	228	ctrl = CNTRLREG_STEPCONFIGWRT \| CNTRLREG_STEPID;
0d3a7cce	229	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
01636eb9 PR	230
01636eb9 PR	231	/* Set register bits for Idle Config Mode */
f0933a60 JL	232	if (tsc_wires > 0) {
	233	tscadc->tsc_wires = tsc_wires;
	234	if (tsc_wires == 5)
	235	ctrl \|= CNTRLREG_5WIRE \| CNTRLREG_TSCENB;
	236	else
	237	ctrl \|= CNTRLREG_4WIRE \| CNTRLREG_TSCENB;
b5f8b763	238	tscadc_idle_config(tscadc);
f0933a60	239	}
01636eb9 PR	240
01636eb9 PR	241	/* Enable the TSC module enable bit */
01636eb9	242	ctrl \|= CNTRLREG_TSCSSENB;
0d3a7cce	243	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
01636eb9	244
24d5c82f PA	245	tscadc->used_cells = 0;
	246	tscadc->tsc_cell = -1;
	247	tscadc->adc_cell = -1;
	248
2b99bafa	249	/* TSC Cell */
24d5c82f PA	250	if (tsc_wires > 0) {
	251	tscadc->tsc_cell = tscadc->used_cells;
	252	cell = &tscadc->cells[tscadc->used_cells++];
5f184e63	253	cell->name = "TI-am335x-tsc";
24d5c82f PA	254	cell->of_compatible = "ti,am3359-tsc";
	255	cell->platform_data = &tscadc;
	256	cell->pdata_size = sizeof(tscadc);
	257	}
2b99bafa	258
5e53a69b	259	/* ADC Cell */
24d5c82f PA	260	if (adc_channels > 0) {
	261	tscadc->adc_cell = tscadc->used_cells;
	262	cell = &tscadc->cells[tscadc->used_cells++];
9f99928f	263	cell->name = "TI-am335x-adc";
24d5c82f PA	264	cell->of_compatible = "ti,am3359-adc";
	265	cell->platform_data = &tscadc;
	266	cell->pdata_size = sizeof(tscadc);
	267	}
5e53a69b	268
01636eb9	269	err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
24d5c82f	270	tscadc->used_cells, NULL, 0, NULL);
01636eb9 PR	271	if (err < 0)
	272	goto err_disable_clk;
	273
	274	device_init_wakeup(&pdev->dev, true);
	275	platform_set_drvdata(pdev, tscadc);
01636eb9 PR	276	return 0;
	277
	278	err_disable_clk:
	279	pm_runtime_put_sync(&pdev->dev);
	280	pm_runtime_disable(&pdev->dev);
3c39c9c6	281	ret:
01636eb9 PR	282	return err;
	283	}
	284
612b95cd	285	static int ti_tscadc_remove(struct platform_device *pdev)
01636eb9 PR	286	{
	287	struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);
	288
0d3a7cce	289	regmap_write(tscadc->regmap, REG_SE, 0x00);
01636eb9 PR	290
	291	pm_runtime_put_sync(&pdev->dev);
	292	pm_runtime_disable(&pdev->dev);
	293
	294	mfd_remove_devices(tscadc->dev);
	295
	296	return 0;
	297	}
	298
dae936a0	299	static int __maybe_unused tscadc_suspend(struct device *dev)
01636eb9	300	{
a318b7d0	301	struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev);
01636eb9	302
0d3a7cce	303	regmap_write(tscadc->regmap, REG_SE, 0x00);
01636eb9 PR	304	pm_runtime_put_sync(dev);
	305
	306	return 0;
	307	}
	308
dae936a0	309	static int __maybe_unused tscadc_resume(struct device *dev)
01636eb9	310	{
a318b7d0	311	struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev);
f0933a60	312	u32 ctrl;
01636eb9 PR	313
	314	pm_runtime_get_sync(dev);
	315
	316	/* context restore */
b5f8b763	317	ctrl = CNTRLREG_STEPCONFIGWRT \| CNTRLREG_STEPID;
0d3a7cce	318	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
b5f8b763	319
a318b7d0 AD	320	if (tscadc->tsc_cell != -1) {
a318b7d0 AD	321	if (tscadc->tsc_wires == 5)
f0933a60 JL	322	ctrl \|= CNTRLREG_5WIRE \| CNTRLREG_TSCENB;
	323	else
	324	ctrl \|= CNTRLREG_4WIRE \| CNTRLREG_TSCENB;
a318b7d0	325	tscadc_idle_config(tscadc);
f0933a60 JL	326	}
f0933a60 JL	327	ctrl \|= CNTRLREG_TSCSSENB;
0d3a7cce	328	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
01636eb9	329
0d3a7cce	330	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);
e90f8754	331
01636eb9 PR	332	return 0;
	333	}
	334
dae936a0	335	static SIMPLE_DEV_PM_OPS(tscadc_pm_ops, tscadc_suspend, tscadc_resume);
01636eb9	336
a6543a1c PR	337	static const struct of_device_id ti_tscadc_dt_ids[] = {
	338	{ .compatible = "ti,am3359-tscadc", },
	339	{ }
	340	};
	341	MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);
	342
01636eb9 PR	343	static struct platform_driver ti_tscadc_driver = {
01636eb9 PR	344	.driver = {
a6543a1c	345	.name = "ti_am3359-tscadc",
dae936a0	346	.pm = &tscadc_pm_ops,
131221bc	347	.of_match_table = ti_tscadc_dt_ids,
01636eb9 PR	348	},
01636eb9 PR	349	.probe = ti_tscadc_probe,
612b95cd	350	.remove = ti_tscadc_remove,
01636eb9 PR	351
	352	};
	353
	354	module_platform_driver(ti_tscadc_driver);
	355
	356	MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
	357	MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
	358	MODULE_LICENSE("GPL");