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Commit | Line | Data |
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27c6750e GG |
1 | /* |
2 | * tps65910.c -- TI TPS6591x | |
3 | * | |
4 | * Copyright 2010 Texas Instruments Inc. | |
5 | * | |
6 | * Author: Graeme Gregory <gg@slimlogic.co.uk> | |
7 | * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/moduleparam.h> | |
18 | #include <linux/init.h> | |
dc9913a0 | 19 | #include <linux/err.h> |
27c6750e GG |
20 | #include <linux/slab.h> |
21 | #include <linux/i2c.h> | |
4aab3fad LD |
22 | #include <linux/interrupt.h> |
23 | #include <linux/irq.h> | |
24 | #include <linux/irqdomain.h> | |
27c6750e | 25 | #include <linux/mfd/core.h> |
dc9913a0 | 26 | #include <linux/regmap.h> |
27c6750e | 27 | #include <linux/mfd/tps65910.h> |
1fead3f3 | 28 | #include <linux/of.h> |
cd4209ce | 29 | #include <linux/of_device.h> |
27c6750e | 30 | |
5863eabb VB |
31 | static struct resource rtc_resources[] = { |
32 | { | |
33 | .start = TPS65910_IRQ_RTC_ALARM, | |
34 | .end = TPS65910_IRQ_RTC_ALARM, | |
35 | .flags = IORESOURCE_IRQ, | |
36 | } | |
37 | }; | |
38 | ||
30fe2b5b | 39 | static const struct mfd_cell tps65910s[] = { |
32df986e LD |
40 | { |
41 | .name = "tps65910-gpio", | |
42 | }, | |
27c6750e GG |
43 | { |
44 | .name = "tps65910-pmic", | |
45 | }, | |
46 | { | |
47 | .name = "tps65910-rtc", | |
5863eabb VB |
48 | .num_resources = ARRAY_SIZE(rtc_resources), |
49 | .resources = &rtc_resources[0], | |
27c6750e GG |
50 | }, |
51 | { | |
52 | .name = "tps65910-power", | |
53 | }, | |
54 | }; | |
55 | ||
56 | ||
4aab3fad LD |
57 | static const struct regmap_irq tps65911_irqs[] = { |
58 | /* INT_STS */ | |
59 | [TPS65911_IRQ_PWRHOLD_F] = { | |
60 | .mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK, | |
61 | .reg_offset = 0, | |
62 | }, | |
63 | [TPS65911_IRQ_VBAT_VMHI] = { | |
64 | .mask = INT_MSK_VMBHI_IT_MSK_MASK, | |
65 | .reg_offset = 0, | |
66 | }, | |
67 | [TPS65911_IRQ_PWRON] = { | |
68 | .mask = INT_MSK_PWRON_IT_MSK_MASK, | |
69 | .reg_offset = 0, | |
70 | }, | |
71 | [TPS65911_IRQ_PWRON_LP] = { | |
72 | .mask = INT_MSK_PWRON_LP_IT_MSK_MASK, | |
73 | .reg_offset = 0, | |
74 | }, | |
75 | [TPS65911_IRQ_PWRHOLD_R] = { | |
76 | .mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK, | |
77 | .reg_offset = 0, | |
78 | }, | |
79 | [TPS65911_IRQ_HOTDIE] = { | |
80 | .mask = INT_MSK_HOTDIE_IT_MSK_MASK, | |
81 | .reg_offset = 0, | |
82 | }, | |
83 | [TPS65911_IRQ_RTC_ALARM] = { | |
84 | .mask = INT_MSK_RTC_ALARM_IT_MSK_MASK, | |
85 | .reg_offset = 0, | |
86 | }, | |
87 | [TPS65911_IRQ_RTC_PERIOD] = { | |
88 | .mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK, | |
89 | .reg_offset = 0, | |
90 | }, | |
91 | ||
92 | /* INT_STS2 */ | |
93 | [TPS65911_IRQ_GPIO0_R] = { | |
94 | .mask = INT_MSK2_GPIO0_R_IT_MSK_MASK, | |
95 | .reg_offset = 1, | |
96 | }, | |
97 | [TPS65911_IRQ_GPIO0_F] = { | |
98 | .mask = INT_MSK2_GPIO0_F_IT_MSK_MASK, | |
99 | .reg_offset = 1, | |
100 | }, | |
101 | [TPS65911_IRQ_GPIO1_R] = { | |
102 | .mask = INT_MSK2_GPIO1_R_IT_MSK_MASK, | |
103 | .reg_offset = 1, | |
104 | }, | |
105 | [TPS65911_IRQ_GPIO1_F] = { | |
106 | .mask = INT_MSK2_GPIO1_F_IT_MSK_MASK, | |
107 | .reg_offset = 1, | |
108 | }, | |
109 | [TPS65911_IRQ_GPIO2_R] = { | |
110 | .mask = INT_MSK2_GPIO2_R_IT_MSK_MASK, | |
111 | .reg_offset = 1, | |
112 | }, | |
113 | [TPS65911_IRQ_GPIO2_F] = { | |
114 | .mask = INT_MSK2_GPIO2_F_IT_MSK_MASK, | |
115 | .reg_offset = 1, | |
116 | }, | |
117 | [TPS65911_IRQ_GPIO3_R] = { | |
118 | .mask = INT_MSK2_GPIO3_R_IT_MSK_MASK, | |
119 | .reg_offset = 1, | |
120 | }, | |
121 | [TPS65911_IRQ_GPIO3_F] = { | |
122 | .mask = INT_MSK2_GPIO3_F_IT_MSK_MASK, | |
123 | .reg_offset = 1, | |
124 | }, | |
125 | ||
126 | /* INT_STS2 */ | |
127 | [TPS65911_IRQ_GPIO4_R] = { | |
128 | .mask = INT_MSK3_GPIO4_R_IT_MSK_MASK, | |
129 | .reg_offset = 2, | |
130 | }, | |
131 | [TPS65911_IRQ_GPIO4_F] = { | |
132 | .mask = INT_MSK3_GPIO4_F_IT_MSK_MASK, | |
133 | .reg_offset = 2, | |
134 | }, | |
135 | [TPS65911_IRQ_GPIO5_R] = { | |
136 | .mask = INT_MSK3_GPIO5_R_IT_MSK_MASK, | |
137 | .reg_offset = 2, | |
138 | }, | |
139 | [TPS65911_IRQ_GPIO5_F] = { | |
140 | .mask = INT_MSK3_GPIO5_F_IT_MSK_MASK, | |
141 | .reg_offset = 2, | |
142 | }, | |
143 | [TPS65911_IRQ_WTCHDG] = { | |
144 | .mask = INT_MSK3_WTCHDG_IT_MSK_MASK, | |
145 | .reg_offset = 2, | |
146 | }, | |
147 | [TPS65911_IRQ_VMBCH2_H] = { | |
148 | .mask = INT_MSK3_VMBCH2_H_IT_MSK_MASK, | |
149 | .reg_offset = 2, | |
150 | }, | |
151 | [TPS65911_IRQ_VMBCH2_L] = { | |
152 | .mask = INT_MSK3_VMBCH2_L_IT_MSK_MASK, | |
153 | .reg_offset = 2, | |
154 | }, | |
155 | [TPS65911_IRQ_PWRDN] = { | |
156 | .mask = INT_MSK3_PWRDN_IT_MSK_MASK, | |
157 | .reg_offset = 2, | |
158 | }, | |
159 | }; | |
160 | ||
161 | static const struct regmap_irq tps65910_irqs[] = { | |
162 | /* INT_STS */ | |
163 | [TPS65910_IRQ_VBAT_VMBDCH] = { | |
164 | .mask = TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK, | |
165 | .reg_offset = 0, | |
166 | }, | |
167 | [TPS65910_IRQ_VBAT_VMHI] = { | |
168 | .mask = TPS65910_INT_MSK_VMBHI_IT_MSK_MASK, | |
169 | .reg_offset = 0, | |
170 | }, | |
171 | [TPS65910_IRQ_PWRON] = { | |
172 | .mask = TPS65910_INT_MSK_PWRON_IT_MSK_MASK, | |
173 | .reg_offset = 0, | |
174 | }, | |
175 | [TPS65910_IRQ_PWRON_LP] = { | |
176 | .mask = TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK, | |
177 | .reg_offset = 0, | |
178 | }, | |
179 | [TPS65910_IRQ_PWRHOLD] = { | |
180 | .mask = TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK, | |
181 | .reg_offset = 0, | |
182 | }, | |
183 | [TPS65910_IRQ_HOTDIE] = { | |
184 | .mask = TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK, | |
185 | .reg_offset = 0, | |
186 | }, | |
187 | [TPS65910_IRQ_RTC_ALARM] = { | |
188 | .mask = TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK, | |
189 | .reg_offset = 0, | |
190 | }, | |
191 | [TPS65910_IRQ_RTC_PERIOD] = { | |
192 | .mask = TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK, | |
193 | .reg_offset = 0, | |
194 | }, | |
195 | ||
196 | /* INT_STS2 */ | |
197 | [TPS65910_IRQ_GPIO_R] = { | |
198 | .mask = TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK, | |
199 | .reg_offset = 1, | |
200 | }, | |
201 | [TPS65910_IRQ_GPIO_F] = { | |
202 | .mask = TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK, | |
203 | .reg_offset = 1, | |
204 | }, | |
205 | }; | |
206 | ||
207 | static struct regmap_irq_chip tps65911_irq_chip = { | |
208 | .name = "tps65910", | |
209 | .irqs = tps65911_irqs, | |
210 | .num_irqs = ARRAY_SIZE(tps65911_irqs), | |
211 | .num_regs = 3, | |
212 | .irq_reg_stride = 2, | |
213 | .status_base = TPS65910_INT_STS, | |
214 | .mask_base = TPS65910_INT_MSK, | |
0582c0fa | 215 | .ack_base = TPS65910_INT_STS, |
4aab3fad LD |
216 | }; |
217 | ||
218 | static struct regmap_irq_chip tps65910_irq_chip = { | |
219 | .name = "tps65910", | |
220 | .irqs = tps65910_irqs, | |
221 | .num_irqs = ARRAY_SIZE(tps65910_irqs), | |
222 | .num_regs = 2, | |
223 | .irq_reg_stride = 2, | |
224 | .status_base = TPS65910_INT_STS, | |
225 | .mask_base = TPS65910_INT_MSK, | |
0582c0fa | 226 | .ack_base = TPS65910_INT_STS, |
4aab3fad LD |
227 | }; |
228 | ||
229 | static int tps65910_irq_init(struct tps65910 *tps65910, int irq, | |
230 | struct tps65910_platform_data *pdata) | |
231 | { | |
232 | int ret = 0; | |
233 | static struct regmap_irq_chip *tps6591x_irqs_chip; | |
234 | ||
235 | if (!irq) { | |
236 | dev_warn(tps65910->dev, "No interrupt support, no core IRQ\n"); | |
237 | return -EINVAL; | |
238 | } | |
239 | ||
240 | if (!pdata) { | |
241 | dev_warn(tps65910->dev, "No interrupt support, no pdata\n"); | |
242 | return -EINVAL; | |
243 | } | |
244 | ||
245 | switch (tps65910_chip_id(tps65910)) { | |
246 | case TPS65910: | |
247 | tps6591x_irqs_chip = &tps65910_irq_chip; | |
248 | break; | |
249 | case TPS65911: | |
250 | tps6591x_irqs_chip = &tps65911_irq_chip; | |
251 | break; | |
252 | } | |
253 | ||
254 | tps65910->chip_irq = irq; | |
6167c5bc LD |
255 | ret = devm_regmap_add_irq_chip(tps65910->dev, tps65910->regmap, |
256 | tps65910->chip_irq, | |
257 | IRQF_ONESHOT, pdata->irq_base, | |
258 | tps6591x_irqs_chip, &tps65910->irq_data); | |
483e2dfd | 259 | if (ret < 0) { |
4aab3fad | 260 | dev_warn(tps65910->dev, "Failed to add irq_chip %d\n", ret); |
483e2dfd KK |
261 | tps65910->chip_irq = 0; |
262 | } | |
4aab3fad LD |
263 | return ret; |
264 | } | |
265 | ||
dc9913a0 LD |
266 | static bool is_volatile_reg(struct device *dev, unsigned int reg) |
267 | { | |
268 | struct tps65910 *tps65910 = dev_get_drvdata(dev); | |
269 | ||
270 | /* | |
271 | * Caching all regulator registers. | |
272 | * All regualator register address range is same for | |
273 | * TPS65910 and TPS65911 | |
274 | */ | |
275 | if ((reg >= TPS65910_VIO) && (reg <= TPS65910_VDAC)) { | |
276 | /* Check for non-existing register */ | |
277 | if (tps65910_chip_id(tps65910) == TPS65910) | |
278 | if ((reg == TPS65911_VDDCTRL_OP) || | |
279 | (reg == TPS65911_VDDCTRL_SR)) | |
280 | return true; | |
281 | return false; | |
282 | } | |
283 | return true; | |
284 | } | |
285 | ||
39ecb037 | 286 | static const struct regmap_config tps65910_regmap_config = { |
dc9913a0 LD |
287 | .reg_bits = 8, |
288 | .val_bits = 8, | |
289 | .volatile_reg = is_volatile_reg, | |
3bf6bf9b | 290 | .max_register = TPS65910_MAX_REGISTER - 1, |
dc9913a0 LD |
291 | .cache_type = REGCACHE_RBTREE, |
292 | }; | |
293 | ||
f791be49 | 294 | static int tps65910_ck32k_init(struct tps65910 *tps65910, |
712db99d JH |
295 | struct tps65910_board *pmic_pdata) |
296 | { | |
712db99d JH |
297 | int ret; |
298 | ||
d02e83cb JH |
299 | if (!pmic_pdata->en_ck32k_xtal) |
300 | return 0; | |
301 | ||
302 | ret = tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL, | |
712db99d | 303 | DEVCTRL_CK32K_CTRL_MASK); |
d02e83cb JH |
304 | if (ret < 0) { |
305 | dev_err(tps65910->dev, "clear ck32k_ctrl failed: %d\n", ret); | |
306 | return ret; | |
712db99d JH |
307 | } |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
f791be49 | 312 | static int tps65910_sleepinit(struct tps65910 *tps65910, |
201cf052 LD |
313 | struct tps65910_board *pmic_pdata) |
314 | { | |
315 | struct device *dev = NULL; | |
316 | int ret = 0; | |
317 | ||
318 | dev = tps65910->dev; | |
319 | ||
320 | if (!pmic_pdata->en_dev_slp) | |
321 | return 0; | |
322 | ||
323 | /* enabling SLEEP device state */ | |
3f7e8275 | 324 | ret = tps65910_reg_set_bits(tps65910, TPS65910_DEVCTRL, |
201cf052 LD |
325 | DEVCTRL_DEV_SLP_MASK); |
326 | if (ret < 0) { | |
327 | dev_err(dev, "set dev_slp failed: %d\n", ret); | |
328 | goto err_sleep_init; | |
329 | } | |
330 | ||
a9bc67de | 331 | if (pmic_pdata->slp_keepon.therm_keepon) { |
3f7e8275 RK |
332 | ret = tps65910_reg_set_bits(tps65910, |
333 | TPS65910_SLEEP_KEEP_RES_ON, | |
201cf052 LD |
334 | SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK); |
335 | if (ret < 0) { | |
336 | dev_err(dev, "set therm_keepon failed: %d\n", ret); | |
337 | goto disable_dev_slp; | |
338 | } | |
339 | } | |
340 | ||
a9bc67de | 341 | if (pmic_pdata->slp_keepon.clkout32k_keepon) { |
3f7e8275 RK |
342 | ret = tps65910_reg_set_bits(tps65910, |
343 | TPS65910_SLEEP_KEEP_RES_ON, | |
201cf052 LD |
344 | SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK); |
345 | if (ret < 0) { | |
346 | dev_err(dev, "set clkout32k_keepon failed: %d\n", ret); | |
347 | goto disable_dev_slp; | |
348 | } | |
349 | } | |
350 | ||
a9bc67de | 351 | if (pmic_pdata->slp_keepon.i2chs_keepon) { |
3f7e8275 RK |
352 | ret = tps65910_reg_set_bits(tps65910, |
353 | TPS65910_SLEEP_KEEP_RES_ON, | |
201cf052 LD |
354 | SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK); |
355 | if (ret < 0) { | |
356 | dev_err(dev, "set i2chs_keepon failed: %d\n", ret); | |
357 | goto disable_dev_slp; | |
358 | } | |
359 | } | |
360 | ||
361 | return 0; | |
362 | ||
363 | disable_dev_slp: | |
3f7e8275 RK |
364 | tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL, |
365 | DEVCTRL_DEV_SLP_MASK); | |
201cf052 LD |
366 | |
367 | err_sleep_init: | |
368 | return ret; | |
369 | } | |
370 | ||
cd4209ce | 371 | #ifdef CONFIG_OF |
c0dfbfe2 | 372 | static const struct of_device_id tps65910_of_match[] = { |
cd4209ce RK |
373 | { .compatible = "ti,tps65910", .data = (void *)TPS65910}, |
374 | { .compatible = "ti,tps65911", .data = (void *)TPS65911}, | |
375 | { }, | |
376 | }; | |
377 | MODULE_DEVICE_TABLE(of, tps65910_of_match); | |
378 | ||
379 | static struct tps65910_board *tps65910_parse_dt(struct i2c_client *client, | |
01a0f4aa | 380 | unsigned long *chip_id) |
cd4209ce RK |
381 | { |
382 | struct device_node *np = client->dev.of_node; | |
383 | struct tps65910_board *board_info; | |
384 | unsigned int prop; | |
385 | const struct of_device_id *match; | |
cd4209ce | 386 | int ret = 0; |
cd4209ce RK |
387 | |
388 | match = of_match_device(tps65910_of_match, &client->dev); | |
389 | if (!match) { | |
390 | dev_err(&client->dev, "Failed to find matching dt id\n"); | |
391 | return NULL; | |
392 | } | |
393 | ||
01a0f4aa | 394 | *chip_id = (unsigned long)match->data; |
cd4209ce RK |
395 | |
396 | board_info = devm_kzalloc(&client->dev, sizeof(*board_info), | |
397 | GFP_KERNEL); | |
93e879ef | 398 | if (!board_info) |
cd4209ce | 399 | return NULL; |
cd4209ce RK |
400 | |
401 | ret = of_property_read_u32(np, "ti,vmbch-threshold", &prop); | |
402 | if (!ret) | |
403 | board_info->vmbch_threshold = prop; | |
cd4209ce RK |
404 | |
405 | ret = of_property_read_u32(np, "ti,vmbch2-threshold", &prop); | |
406 | if (!ret) | |
407 | board_info->vmbch2_threshold = prop; | |
cd4209ce | 408 | |
bcc1dd4c JH |
409 | prop = of_property_read_bool(np, "ti,en-ck32k-xtal"); |
410 | board_info->en_ck32k_xtal = prop; | |
411 | ||
a9bc67de MM |
412 | prop = of_property_read_bool(np, "ti,sleep-enable"); |
413 | board_info->en_dev_slp = prop; | |
414 | ||
415 | prop = of_property_read_bool(np, "ti,sleep-keep-therm"); | |
416 | board_info->slp_keepon.therm_keepon = prop; | |
417 | ||
418 | prop = of_property_read_bool(np, "ti,sleep-keep-ck32k"); | |
419 | board_info->slp_keepon.clkout32k_keepon = prop; | |
420 | ||
421 | prop = of_property_read_bool(np, "ti,sleep-keep-hsclk"); | |
422 | board_info->slp_keepon.i2chs_keepon = prop; | |
423 | ||
cd4209ce RK |
424 | board_info->irq = client->irq; |
425 | board_info->irq_base = -1; | |
b079fa72 BH |
426 | board_info->pm_off = of_property_read_bool(np, |
427 | "ti,system-power-controller"); | |
cd4209ce RK |
428 | |
429 | return board_info; | |
430 | } | |
431 | #else | |
7f65f74c SO |
432 | static inline |
433 | struct tps65910_board *tps65910_parse_dt(struct i2c_client *client, | |
01a0f4aa | 434 | unsigned long *chip_id) |
cd4209ce RK |
435 | { |
436 | return NULL; | |
437 | } | |
438 | #endif | |
201cf052 | 439 | |
b079fa72 BH |
440 | static struct i2c_client *tps65910_i2c_client; |
441 | static void tps65910_power_off(void) | |
442 | { | |
443 | struct tps65910 *tps65910; | |
444 | ||
445 | tps65910 = dev_get_drvdata(&tps65910_i2c_client->dev); | |
446 | ||
447 | if (tps65910_reg_set_bits(tps65910, TPS65910_DEVCTRL, | |
448 | DEVCTRL_PWR_OFF_MASK) < 0) | |
449 | return; | |
450 | ||
451 | tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL, | |
452 | DEVCTRL_DEV_ON_MASK); | |
453 | } | |
454 | ||
f791be49 | 455 | static int tps65910_i2c_probe(struct i2c_client *i2c, |
01a0f4aa | 456 | const struct i2c_device_id *id) |
27c6750e GG |
457 | { |
458 | struct tps65910 *tps65910; | |
2537df72 | 459 | struct tps65910_board *pmic_plat_data; |
cb8d8654 | 460 | struct tps65910_board *of_pmic_plat_data = NULL; |
e3471bdc | 461 | struct tps65910_platform_data *init_data; |
01a0f4aa | 462 | unsigned long chip_id = id->driver_data; |
27c6750e GG |
463 | int ret = 0; |
464 | ||
2537df72 | 465 | pmic_plat_data = dev_get_platdata(&i2c->dev); |
cd4209ce | 466 | |
cb8d8654 | 467 | if (!pmic_plat_data && i2c->dev.of_node) { |
cd4209ce | 468 | pmic_plat_data = tps65910_parse_dt(i2c, &chip_id); |
cb8d8654 LD |
469 | of_pmic_plat_data = pmic_plat_data; |
470 | } | |
cd4209ce | 471 | |
2537df72 GG |
472 | if (!pmic_plat_data) |
473 | return -EINVAL; | |
474 | ||
63fe7dee | 475 | init_data = devm_kzalloc(&i2c->dev, sizeof(*init_data), GFP_KERNEL); |
e3471bdc GG |
476 | if (init_data == NULL) |
477 | return -ENOMEM; | |
478 | ||
63fe7dee LD |
479 | tps65910 = devm_kzalloc(&i2c->dev, sizeof(*tps65910), GFP_KERNEL); |
480 | if (tps65910 == NULL) | |
27c6750e GG |
481 | return -ENOMEM; |
482 | ||
cb8d8654 | 483 | tps65910->of_plat_data = of_pmic_plat_data; |
27c6750e GG |
484 | i2c_set_clientdata(i2c, tps65910); |
485 | tps65910->dev = &i2c->dev; | |
486 | tps65910->i2c_client = i2c; | |
cd4209ce | 487 | tps65910->id = chip_id; |
27c6750e | 488 | |
be1c7700 AVEM |
489 | /* Work around silicon erratum SWCZ010: the tps65910 may miss the |
490 | * first I2C transfer. So issue a dummy transfer before the first | |
491 | * real transfer. | |
492 | */ | |
493 | i2c_master_send(i2c, "", 1); | |
63fe7dee | 494 | tps65910->regmap = devm_regmap_init_i2c(i2c, &tps65910_regmap_config); |
dc9913a0 LD |
495 | if (IS_ERR(tps65910->regmap)) { |
496 | ret = PTR_ERR(tps65910->regmap); | |
497 | dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret); | |
63fe7dee | 498 | return ret; |
dc9913a0 LD |
499 | } |
500 | ||
b1224cd1 | 501 | init_data->irq = pmic_plat_data->irq; |
1773140f | 502 | init_data->irq_base = pmic_plat_data->irq_base; |
b1224cd1 | 503 | |
1e351a95 | 504 | tps65910_irq_init(tps65910, init_data->irq, init_data); |
d02e83cb | 505 | tps65910_ck32k_init(tps65910, pmic_plat_data); |
201cf052 LD |
506 | tps65910_sleepinit(tps65910, pmic_plat_data); |
507 | ||
b079fa72 BH |
508 | if (pmic_plat_data->pm_off && !pm_power_off) { |
509 | tps65910_i2c_client = i2c; | |
510 | pm_power_off = tps65910_power_off; | |
511 | } | |
512 | ||
f3466e77 LD |
513 | ret = devm_mfd_add_devices(tps65910->dev, -1, |
514 | tps65910s, ARRAY_SIZE(tps65910s), | |
515 | NULL, 0, | |
516 | regmap_irq_get_domain(tps65910->irq_data)); | |
10ecb80e LD |
517 | if (ret < 0) { |
518 | dev_err(&i2c->dev, "mfd_add_devices failed: %d\n", ret); | |
519 | return ret; | |
520 | } | |
521 | ||
27c6750e GG |
522 | return ret; |
523 | } | |
524 | ||
27c6750e | 525 | static const struct i2c_device_id tps65910_i2c_id[] = { |
79557056 JEC |
526 | { "tps65910", TPS65910 }, |
527 | { "tps65911", TPS65911 }, | |
27c6750e GG |
528 | { } |
529 | }; | |
530 | MODULE_DEVICE_TABLE(i2c, tps65910_i2c_id); | |
531 | ||
532 | ||
533 | static struct i2c_driver tps65910_i2c_driver = { | |
534 | .driver = { | |
535 | .name = "tps65910", | |
cd4209ce | 536 | .of_match_table = of_match_ptr(tps65910_of_match), |
27c6750e GG |
537 | }, |
538 | .probe = tps65910_i2c_probe, | |
27c6750e GG |
539 | .id_table = tps65910_i2c_id, |
540 | }; | |
541 | ||
542 | static int __init tps65910_i2c_init(void) | |
543 | { | |
544 | return i2c_add_driver(&tps65910_i2c_driver); | |
545 | } | |
546 | /* init early so consumer devices can complete system boot */ | |
547 | subsys_initcall(tps65910_i2c_init); | |
548 | ||
549 | static void __exit tps65910_i2c_exit(void) | |
550 | { | |
551 | i2c_del_driver(&tps65910_i2c_driver); | |
552 | } | |
553 | module_exit(tps65910_i2c_exit); | |
554 | ||
555 | MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); | |
556 | MODULE_AUTHOR("Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>"); | |
557 | MODULE_DESCRIPTION("TPS6591x chip family multi-function driver"); | |
558 | MODULE_LICENSE("GPL"); |