[mirror_ubuntu-zesty-kernel.git] / drivers / mfd / twl4030-power.c

/*
 * linux/drivers/i2c/chips/twl4030-power.c
 *
 * Handle TWL4030 Power initialization
 *
 * Copyright (C) 2008 Nokia Corporation
 * Copyright (C) 2006 Texas Instruments, Inc
 *
 * Written by 	Kalle Jokiniemi
 *		Peter De Schrijver <peter.de-schrijver@nokia.com>
 * Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>
 *
 * This file is subject to the terms and conditions of the GNU General
 * Public License. See the file "COPYING" in the main directory of this
 * archive for more details.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/module.h>
#include <linux/pm.h>
#include <linux/i2c/twl.h>
#include <linux/platform_device.h>

#include <asm/mach-types.h>

static u8 twl4030_start_script_address = 0x2b;

#define PWR_P1_SW_EVENTS	0x10
#define PWR_DEVOFF		(1 << 0)
#define SEQ_OFFSYNC		(1 << 0)

#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
#define PHY_TO_OFF_PM_RECEIVER(p)	(p - 0x5b)

/* resource - hfclk */
#define R_HFCLKOUT_DEV_GRP 	PHY_TO_OFF_PM_RECEIVER(0xe6)

/* PM events */
#define R_P1_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x46)
#define R_P2_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x47)
#define R_P3_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x48)
#define R_CFG_P1_TRANSITION	PHY_TO_OFF_PM_MASTER(0x36)
#define R_CFG_P2_TRANSITION	PHY_TO_OFF_PM_MASTER(0x37)
#define R_CFG_P3_TRANSITION	PHY_TO_OFF_PM_MASTER(0x38)

#define LVL_WAKEUP	0x08

#define ENABLE_WARMRESET (1<<4)

#define END_OF_SCRIPT		0x3f

#define R_SEQ_ADD_A2S		PHY_TO_OFF_PM_MASTER(0x55)
#define R_SEQ_ADD_S2A12		PHY_TO_OFF_PM_MASTER(0x56)
#define	R_SEQ_ADD_S2A3		PHY_TO_OFF_PM_MASTER(0x57)
#define	R_SEQ_ADD_WARM		PHY_TO_OFF_PM_MASTER(0x58)
#define R_MEMORY_ADDRESS	PHY_TO_OFF_PM_MASTER(0x59)
#define R_MEMORY_DATA		PHY_TO_OFF_PM_MASTER(0x5a)

/* resource configuration registers
   <RESOURCE>_DEV_GRP   at address 'n+0'
   <RESOURCE>_TYPE      at address 'n+1'
   <RESOURCE>_REMAP     at address 'n+2'
   <RESOURCE>_DEDICATED at address 'n+3'
*/
#define DEV_GRP_OFFSET		0
#define TYPE_OFFSET		1
#define REMAP_OFFSET		2
#define DEDICATED_OFFSET	3

/* Bit positions in the registers */

/* <RESOURCE>_DEV_GRP */
#define DEV_GRP_SHIFT		5
#define DEV_GRP_MASK		(7 << DEV_GRP_SHIFT)

/* <RESOURCE>_TYPE */
#define TYPE_SHIFT		0
#define TYPE_MASK		(7 << TYPE_SHIFT)
#define TYPE2_SHIFT		3
#define TYPE2_MASK		(3 << TYPE2_SHIFT)

/* <RESOURCE>_REMAP */
#define SLEEP_STATE_SHIFT	0
#define SLEEP_STATE_MASK	(0xf << SLEEP_STATE_SHIFT)
#define OFF_STATE_SHIFT		4
#define OFF_STATE_MASK		(0xf << OFF_STATE_SHIFT)

static u8 res_config_addrs[] = {
	[RES_VAUX1]	= 0x17,
	[RES_VAUX2]	= 0x1b,
	[RES_VAUX3]	= 0x1f,
	[RES_VAUX4]	= 0x23,
	[RES_VMMC1]	= 0x27,
	[RES_VMMC2]	= 0x2b,
	[RES_VPLL1]	= 0x2f,
	[RES_VPLL2]	= 0x33,
	[RES_VSIM]	= 0x37,
	[RES_VDAC]	= 0x3b,
	[RES_VINTANA1]	= 0x3f,
	[RES_VINTANA2]	= 0x43,
	[RES_VINTDIG]	= 0x47,
	[RES_VIO]	= 0x4b,
	[RES_VDD1]	= 0x55,
	[RES_VDD2]	= 0x63,
	[RES_VUSB_1V5]	= 0x71,
	[RES_VUSB_1V8]	= 0x74,
	[RES_VUSB_3V1]	= 0x77,
	[RES_VUSBCP]	= 0x7a,
	[RES_REGEN]	= 0x7f,
	[RES_NRES_PWRON] = 0x82,
	[RES_CLKEN]	= 0x85,
	[RES_SYSEN]	= 0x88,
	[RES_HFCLKOUT]	= 0x8b,
	[RES_32KCLKOUT]	= 0x8e,
	[RES_RESET]	= 0x91,
	[RES_MAIN_REF]	= 0x94,
};

static int twl4030_write_script_byte(u8 address, u8 byte)
{
	int err;

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_MEMORY_ADDRESS);
	if (err)
		goto out;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, byte, R_MEMORY_DATA);
out:
	return err;
}

static int twl4030_write_script_ins(u8 address, u16 pmb_message,
					   u8 delay, u8 next)
{
	int err;

	address *= 4;
	err = twl4030_write_script_byte(address++, pmb_message >> 8);
	if (err)
		goto out;
	err = twl4030_write_script_byte(address++, pmb_message & 0xff);
	if (err)
		goto out;
	err = twl4030_write_script_byte(address++, delay);
	if (err)
		goto out;
	err = twl4030_write_script_byte(address++, next);
out:
	return err;
}

static int twl4030_write_script(u8 address, struct twl4030_ins *script,
				       int len)
{
	int err = -EINVAL;

	for (; len; len--, address++, script++) {
		if (len == 1) {
			err = twl4030_write_script_ins(address,
						script->pmb_message,
						script->delay,
						END_OF_SCRIPT);
			if (err)
				break;
		} else {
			err = twl4030_write_script_ins(address,
						script->pmb_message,
						script->delay,
						address + 1);
			if (err)
				break;
		}
	}
	return err;
}

static int twl4030_config_wakeup3_sequence(u8 address)
{
	int err;
	u8 data;

	/* Set SLEEP to ACTIVE SEQ address for P3 */
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A3);
	if (err)
		goto out;

	/* P3 LVL_WAKEUP should be on LEVEL */
	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P3_SW_EVENTS);
	if (err)
		goto out;
	data |= LVL_WAKEUP;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P3_SW_EVENTS);
out:
	if (err)
		pr_err("TWL4030 wakeup sequence for P3 config error\n");
	return err;
}

static int twl4030_config_wakeup12_sequence(u8 address)
{
	int err = 0;
	u8 data;

	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A12);
	if (err)
		goto out;

	/* P1/P2 LVL_WAKEUP should be on LEVEL */
	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P1_SW_EVENTS);
	if (err)
		goto out;

	data |= LVL_WAKEUP;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P1_SW_EVENTS);
	if (err)
		goto out;

	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P2_SW_EVENTS);
	if (err)
		goto out;

	data |= LVL_WAKEUP;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P2_SW_EVENTS);
	if (err)
		goto out;

	if (machine_is_omap_3430sdp() || machine_is_omap_ldp()) {
		/* Disabling AC charger effect on sleep-active transitions */
		err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data,
				      R_CFG_P1_TRANSITION);
		if (err)
			goto out;
		data &= ~(1<<1);
		err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data,
				       R_CFG_P1_TRANSITION);
		if (err)
			goto out;
	}

out:
	if (err)
		pr_err("TWL4030 wakeup sequence for P1 and P2" \
			"config error\n");
	return err;
}

static int twl4030_config_sleep_sequence(u8 address)
{
	int err;

	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_A2S);

	if (err)
		pr_err("TWL4030 sleep sequence config error\n");

	return err;
}

static int twl4030_config_warmreset_sequence(u8 address)
{
	int err;
	u8 rd_data;

	/* Set WARM RESET SEQ address for P1 */
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_WARM);
	if (err)
		goto out;

	/* P1/P2/P3 enable WARMRESET */
	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P1_SW_EVENTS);
	if (err)
		goto out;

	rd_data |= ENABLE_WARMRESET;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P1_SW_EVENTS);
	if (err)
		goto out;

	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P2_SW_EVENTS);
	if (err)
		goto out;

	rd_data |= ENABLE_WARMRESET;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P2_SW_EVENTS);
	if (err)
		goto out;

	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P3_SW_EVENTS);
	if (err)
		goto out;

	rd_data |= ENABLE_WARMRESET;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P3_SW_EVENTS);
out:
	if (err)
		pr_err("TWL4030 warmreset seq config error\n");
	return err;
}

static int twl4030_configure_resource(struct twl4030_resconfig *rconfig)
{
	int rconfig_addr;
	int err;
	u8 type;
	u8 grp;
	u8 remap;

	if (rconfig->resource > TOTAL_RESOURCES) {
		pr_err("TWL4030 Resource %d does not exist\n",
			rconfig->resource);
		return -EINVAL;
	}

	rconfig_addr = res_config_addrs[rconfig->resource];

	/* Set resource group */
	err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &grp,
			      rconfig_addr + DEV_GRP_OFFSET);
	if (err) {
		pr_err("TWL4030 Resource %d group could not be read\n",
			rconfig->resource);
		return err;
	}

	if (rconfig->devgroup != TWL4030_RESCONFIG_UNDEF) {
		grp &= ~DEV_GRP_MASK;
		grp |= rconfig->devgroup << DEV_GRP_SHIFT;
		err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
				       grp, rconfig_addr + DEV_GRP_OFFSET);
		if (err < 0) {
			pr_err("TWL4030 failed to program devgroup\n");
			return err;
		}
	}

	/* Set resource types */
	err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &type,
				rconfig_addr + TYPE_OFFSET);
	if (err < 0) {
		pr_err("TWL4030 Resource %d type could not be read\n",
			rconfig->resource);
		return err;
	}

	if (rconfig->type != TWL4030_RESCONFIG_UNDEF) {
		type &= ~TYPE_MASK;
		type |= rconfig->type << TYPE_SHIFT;
	}

	if (rconfig->type2 != TWL4030_RESCONFIG_UNDEF) {
		type &= ~TYPE2_MASK;
		type |= rconfig->type2 << TYPE2_SHIFT;
	}

	err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
				type, rconfig_addr + TYPE_OFFSET);
	if (err < 0) {
		pr_err("TWL4030 failed to program resource type\n");
		return err;
	}

	/* Set remap states */
	err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &remap,
			      rconfig_addr + REMAP_OFFSET);
	if (err < 0) {
		pr_err("TWL4030 Resource %d remap could not be read\n",
			rconfig->resource);
		return err;
	}

	if (rconfig->remap_off != TWL4030_RESCONFIG_UNDEF) {
		remap &= ~OFF_STATE_MASK;
		remap |= rconfig->remap_off << OFF_STATE_SHIFT;
	}

	if (rconfig->remap_sleep != TWL4030_RESCONFIG_UNDEF) {
		remap &= ~SLEEP_STATE_MASK;
		remap |= rconfig->remap_sleep << SLEEP_STATE_SHIFT;
	}

	err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
			       remap,
			       rconfig_addr + REMAP_OFFSET);
	if (err < 0) {
		pr_err("TWL4030 failed to program remap\n");
		return err;
	}

	return 0;
}

static int load_twl4030_script(struct twl4030_script *tscript,
	       u8 address)
{
	int err;
	static int order;

	/* Make sure the script isn't going beyond last valid address (0x3f) */
	if ((address + tscript->size) > END_OF_SCRIPT) {
		pr_err("TWL4030 scripts too big error\n");
		return -EINVAL;
	}

	err = twl4030_write_script(address, tscript->script, tscript->size);
	if (err)
		goto out;

	if (tscript->flags & TWL4030_WRST_SCRIPT) {
		err = twl4030_config_warmreset_sequence(address);
		if (err)
			goto out;
	}
	if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) {
		err = twl4030_config_wakeup12_sequence(address);
		if (err)
			goto out;
		order = 1;
	}
	if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) {
		err = twl4030_config_wakeup3_sequence(address);
		if (err)
			goto out;
	}
	if (tscript->flags & TWL4030_SLEEP_SCRIPT) {
		if (!order)
			pr_warning("TWL4030: Bad order of scripts (sleep "\
					"script before wakeup) Leads to boot"\
					"failure on some boards\n");
		err = twl4030_config_sleep_sequence(address);
	}
out:
	return err;
}

int twl4030_remove_script(u8 flags)
{
	int err = 0;

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
			       TWL4030_PM_MASTER_PROTECT_KEY);
	if (err) {
		pr_err("twl4030: unable to unlock PROTECT_KEY\n");
		return err;
	}

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
			       TWL4030_PM_MASTER_PROTECT_KEY);
	if (err) {
		pr_err("twl4030: unable to unlock PROTECT_KEY\n");
		return err;
	}

	if (flags & TWL4030_WRST_SCRIPT) {
		err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
				       R_SEQ_ADD_WARM);
		if (err)
			return err;
	}
	if (flags & TWL4030_WAKEUP12_SCRIPT) {
		err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
				       R_SEQ_ADD_S2A12);
		if (err)
			return err;
	}
	if (flags & TWL4030_WAKEUP3_SCRIPT) {
		err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
				       R_SEQ_ADD_S2A3);
		if (err)
			return err;
	}
	if (flags & TWL4030_SLEEP_SCRIPT) {
		err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
				       R_SEQ_ADD_A2S);
		if (err)
			return err;
	}

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
			       TWL4030_PM_MASTER_PROTECT_KEY);
	if (err)
		pr_err("TWL4030 Unable to relock registers\n");

	return err;
}

/*
 * In master mode, start the power off sequence.
 * After a successful execution, TWL shuts down the power to the SoC
 * and all peripherals connected to it.
 */
void twl4030_power_off(void)
{
	int err;

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, PWR_DEVOFF,
			       TWL4030_PM_MASTER_P1_SW_EVENTS);
	if (err)
		pr_err("TWL4030 Unable to power off\n");
}

void twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
{
	int err = 0;
	int i;
	struct twl4030_resconfig *resconfig;
	u8 val, address = twl4030_start_script_address;

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
			       TWL4030_PM_MASTER_PROTECT_KEY);
	if (err)
		goto unlock;

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
			       TWL4030_PM_MASTER_PROTECT_KEY);
	if (err)
		goto unlock;

	for (i = 0; i < twl4030_scripts->num; i++) {
		err = load_twl4030_script(twl4030_scripts->scripts[i], address);
		if (err)
			goto load;
		address += twl4030_scripts->scripts[i]->size;
	}

	resconfig = twl4030_scripts->resource_config;
	if (resconfig) {
		while (resconfig->resource) {
			err = twl4030_configure_resource(resconfig);
			if (err)
				goto resource;
			resconfig++;

		}
	}

	/* Board has to be wired properly to use this feature */
	if (twl4030_scripts->use_poweroff && !pm_power_off) {
		/* Default for SEQ_OFFSYNC is set, lets ensure this */
		err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
				      TWL4030_PM_MASTER_CFG_P123_TRANSITION);
		if (err) {
			pr_warning("TWL4030 Unable to read registers\n");

		} else if (!(val & SEQ_OFFSYNC)) {
			val |= SEQ_OFFSYNC;
			err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val,
					TWL4030_PM_MASTER_CFG_P123_TRANSITION);
			if (err) {
				pr_err("TWL4030 Unable to setup SEQ_OFFSYNC\n");
				goto relock;
			}
		}

		pm_power_off = twl4030_power_off;
	}

relock:
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
			       TWL4030_PM_MASTER_PROTECT_KEY);
	if (err)
		pr_err("TWL4030 Unable to relock registers\n");
	return;

unlock:
	if (err)
		pr_err("TWL4030 Unable to unlock registers\n");
	return;
load:
	if (err)
		pr_err("TWL4030 failed to load scripts\n");
	return;
resource:
	if (err)
		pr_err("TWL4030 failed to configure resource\n");
	return;
}
Commit	Line	Data
ebf0bd36 AK	1	/*
	2	* linux/drivers/i2c/chips/twl4030-power.c
	3	*
	4	* Handle TWL4030 Power initialization
	5	*
	6	* Copyright (C) 2008 Nokia Corporation
	7	* Copyright (C) 2006 Texas Instruments, Inc
	8	*
	9	* Written by Kalle Jokiniemi
	10	* Peter De Schrijver <peter.de-schrijver@nokia.com>
	11	* Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>
	12	*
	13	* This file is subject to the terms and conditions of the GNU General
	14	* Public License. See the file "COPYING" in the main directory of this
	15	* archive for more details.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	25	*/
	26
	27	#include <linux/module.h>
	28	#include <linux/pm.h>
b07682b6	29	#include <linux/i2c/twl.h>
ebf0bd36 AK	30	#include <linux/platform_device.h>
	31
	32	#include <asm/mach-types.h>
	33
	34	static u8 twl4030_start_script_address = 0x2b;
	35
	36	#define PWR_P1_SW_EVENTS 0x10
26cc3ab9 IG	37	#define PWR_DEVOFF (1 << 0)
26cc3ab9 IG	38	#define SEQ_OFFSYNC (1 << 0)
ebf0bd36 AK	39
	40	#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
	41	#define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
	42
	43	/* resource - hfclk */
	44	#define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
	45
	46	/* PM events */
	47	#define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
	48	#define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
	49	#define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
	50	#define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)
	51	#define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)
	52	#define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)
	53
	54	#define LVL_WAKEUP 0x08
	55
	56	#define ENABLE_WARMRESET (1<<4)
	57
	58	#define END_OF_SCRIPT 0x3f
	59
	60	#define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
	61	#define R_SEQ_ADD_S2A12 PHY_TO_OFF_PM_MASTER(0x56)
	62	#define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
	63	#define R_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
	64	#define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
	65	#define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
	66
890463f0 AK	67	/* resource configuration registers
	68	<RESOURCE>_DEV_GRP at address 'n+0'
	69	<RESOURCE>_TYPE at address 'n+1'
	70	<RESOURCE>_REMAP at address 'n+2'
	71	<RESOURCE>_DEDICATED at address 'n+3'
	72	*/
e97d1546	73	#define DEV_GRP_OFFSET 0
ebf0bd36	74	#define TYPE_OFFSET 1
b4ead61e AK	75	#define REMAP_OFFSET 2
b4ead61e AK	76	#define DEDICATED_OFFSET 3
ebf0bd36	77
e97d1546	78	/* Bit positions in the registers */
890463f0 AK	79
890463f0 AK	80	/* <RESOURCE>_DEV_GRP */
e97d1546 AK	81	#define DEV_GRP_SHIFT 5
e97d1546 AK	82	#define DEV_GRP_MASK (7 << DEV_GRP_SHIFT)
890463f0 AK	83
890463f0 AK	84	/* <RESOURCE>_TYPE */
ebf0bd36 AK	85	#define TYPE_SHIFT 0
	86	#define TYPE_MASK (7 << TYPE_SHIFT)
	87	#define TYPE2_SHIFT 3
	88	#define TYPE2_MASK (3 << TYPE2_SHIFT)
	89
b4ead61e AK	90	/* <RESOURCE>_REMAP */
	91	#define SLEEP_STATE_SHIFT 0
	92	#define SLEEP_STATE_MASK (0xf << SLEEP_STATE_SHIFT)
	93	#define OFF_STATE_SHIFT 4
	94	#define OFF_STATE_MASK (0xf << OFF_STATE_SHIFT)
	95
ebf0bd36 AK	96	static u8 res_config_addrs[] = {
	97	[RES_VAUX1] = 0x17,
	98	[RES_VAUX2] = 0x1b,
	99	[RES_VAUX3] = 0x1f,
	100	[RES_VAUX4] = 0x23,
	101	[RES_VMMC1] = 0x27,
	102	[RES_VMMC2] = 0x2b,
	103	[RES_VPLL1] = 0x2f,
	104	[RES_VPLL2] = 0x33,
	105	[RES_VSIM] = 0x37,
	106	[RES_VDAC] = 0x3b,
	107	[RES_VINTANA1] = 0x3f,
	108	[RES_VINTANA2] = 0x43,
	109	[RES_VINTDIG] = 0x47,
	110	[RES_VIO] = 0x4b,
	111	[RES_VDD1] = 0x55,
	112	[RES_VDD2] = 0x63,
	113	[RES_VUSB_1V5] = 0x71,
	114	[RES_VUSB_1V8] = 0x74,
	115	[RES_VUSB_3V1] = 0x77,
	116	[RES_VUSBCP] = 0x7a,
	117	[RES_REGEN] = 0x7f,
	118	[RES_NRES_PWRON] = 0x82,
	119	[RES_CLKEN] = 0x85,
	120	[RES_SYSEN] = 0x88,
	121	[RES_HFCLKOUT] = 0x8b,
	122	[RES_32KCLKOUT] = 0x8e,
	123	[RES_RESET] = 0x91,
d7ac829f	124	[RES_MAIN_REF] = 0x94,
ebf0bd36 AK	125	};
ebf0bd36 AK	126
f791be49	127	static int twl4030_write_script_byte(u8 address, u8 byte)
ebf0bd36 AK	128	{
	129	int err;
	130
4850f124	131	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_MEMORY_ADDRESS);
ebf0bd36 AK	132	if (err)
ebf0bd36 AK	133	goto out;
4850f124	134	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, byte, R_MEMORY_DATA);
ebf0bd36 AK	135	out:
	136	return err;
	137	}
	138
f791be49	139	static int twl4030_write_script_ins(u8 address, u16 pmb_message,
ebf0bd36 AK	140	u8 delay, u8 next)
	141	{
	142	int err;
	143
	144	address *= 4;
	145	err = twl4030_write_script_byte(address++, pmb_message >> 8);
	146	if (err)
	147	goto out;
	148	err = twl4030_write_script_byte(address++, pmb_message & 0xff);
	149	if (err)
	150	goto out;
	151	err = twl4030_write_script_byte(address++, delay);
	152	if (err)
	153	goto out;
	154	err = twl4030_write_script_byte(address++, next);
	155	out:
	156	return err;
	157	}
	158
f791be49	159	static int twl4030_write_script(u8 address, struct twl4030_ins *script,
ebf0bd36 AK	160	int len)
ebf0bd36 AK	161	{
f65e9eac	162	int err = -EINVAL;
ebf0bd36 AK	163
	164	for (; len; len--, address++, script++) {
	165	if (len == 1) {
	166	err = twl4030_write_script_ins(address,
	167	script->pmb_message,
	168	script->delay,
	169	END_OF_SCRIPT);
	170	if (err)
	171	break;
	172	} else {
	173	err = twl4030_write_script_ins(address,
	174	script->pmb_message,
	175	script->delay,
	176	address + 1);
	177	if (err)
	178	break;
	179	}
	180	}
	181	return err;
	182	}
	183
f791be49	184	static int twl4030_config_wakeup3_sequence(u8 address)
ebf0bd36 AK	185	{
	186	int err;
	187	u8 data;
	188
	189	/* Set SLEEP to ACTIVE SEQ address for P3 */
4850f124	190	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A3);
ebf0bd36 AK	191	if (err)
	192	goto out;
	193
	194	/* P3 LVL_WAKEUP should be on LEVEL */
4850f124	195	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P3_SW_EVENTS);
ebf0bd36 AK	196	if (err)
	197	goto out;
	198	data \|= LVL_WAKEUP;
4850f124	199	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P3_SW_EVENTS);
ebf0bd36 AK	200	out:
	201	if (err)
	202	pr_err("TWL4030 wakeup sequence for P3 config error\n");
	203	return err;
	204	}
	205
f791be49	206	static int twl4030_config_wakeup12_sequence(u8 address)
ebf0bd36 AK	207	{
	208	int err = 0;
	209	u8 data;
	210
	211	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
4850f124	212	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A12);
ebf0bd36 AK	213	if (err)
	214	goto out;
	215
	216	/* P1/P2 LVL_WAKEUP should be on LEVEL */
4850f124	217	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P1_SW_EVENTS);
ebf0bd36 AK	218	if (err)
	219	goto out;
	220
	221	data \|= LVL_WAKEUP;
4850f124	222	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P1_SW_EVENTS);
ebf0bd36 AK	223	if (err)
	224	goto out;
	225
4850f124	226	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P2_SW_EVENTS);
ebf0bd36 AK	227	if (err)
	228	goto out;
	229
	230	data \|= LVL_WAKEUP;
4850f124	231	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P2_SW_EVENTS);
ebf0bd36 AK	232	if (err)
	233	goto out;
	234
	235	if (machine_is_omap_3430sdp() \|\| machine_is_omap_ldp()) {
	236	/* Disabling AC charger effect on sleep-active transitions */
4850f124 PU	237	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data,
4850f124 PU	238	R_CFG_P1_TRANSITION);
ebf0bd36 AK	239	if (err)
	240	goto out;
	241	data &= ~(1<<1);
4850f124 PU	242	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data,
4850f124 PU	243	R_CFG_P1_TRANSITION);
ebf0bd36 AK	244	if (err)
	245	goto out;
	246	}
	247
	248	out:
	249	if (err)
	250	pr_err("TWL4030 wakeup sequence for P1 and P2" \
	251	"config error\n");
	252	return err;
	253	}
	254
f791be49	255	static int twl4030_config_sleep_sequence(u8 address)
ebf0bd36 AK	256	{
	257	int err;
	258
	259	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
4850f124	260	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_A2S);
ebf0bd36 AK	261
	262	if (err)
	263	pr_err("TWL4030 sleep sequence config error\n");
	264
	265	return err;
	266	}
	267
f791be49	268	static int twl4030_config_warmreset_sequence(u8 address)
ebf0bd36 AK	269	{
	270	int err;
	271	u8 rd_data;
	272
	273	/* Set WARM RESET SEQ address for P1 */
4850f124	274	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_WARM);
ebf0bd36 AK	275	if (err)
	276	goto out;
	277
	278	/* P1/P2/P3 enable WARMRESET */
4850f124	279	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P1_SW_EVENTS);
ebf0bd36 AK	280	if (err)
	281	goto out;
	282
	283	rd_data \|= ENABLE_WARMRESET;
4850f124	284	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P1_SW_EVENTS);
ebf0bd36 AK	285	if (err)
	286	goto out;
	287
4850f124	288	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P2_SW_EVENTS);
ebf0bd36 AK	289	if (err)
	290	goto out;
	291
	292	rd_data \|= ENABLE_WARMRESET;
4850f124	293	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P2_SW_EVENTS);
ebf0bd36 AK	294	if (err)
	295	goto out;
	296
4850f124	297	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P3_SW_EVENTS);
ebf0bd36 AK	298	if (err)
	299	goto out;
	300
	301	rd_data \|= ENABLE_WARMRESET;
4850f124	302	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P3_SW_EVENTS);
ebf0bd36 AK	303	out:
	304	if (err)
	305	pr_err("TWL4030 warmreset seq config error\n");
	306	return err;
	307	}
	308
f791be49	309	static int twl4030_configure_resource(struct twl4030_resconfig *rconfig)
ebf0bd36 AK	310	{
	311	int rconfig_addr;
	312	int err;
	313	u8 type;
	314	u8 grp;
b4ead61e	315	u8 remap;
ebf0bd36 AK	316
	317	if (rconfig->resource > TOTAL_RESOURCES) {
	318	pr_err("TWL4030 Resource %d does not exist\n",
	319	rconfig->resource);
	320	return -EINVAL;
	321	}
	322
	323	rconfig_addr = res_config_addrs[rconfig->resource];
	324
	325	/* Set resource group */
4850f124	326	err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &grp,
fc7b92fc	327	rconfig_addr + DEV_GRP_OFFSET);
ebf0bd36 AK	328	if (err) {
	329	pr_err("TWL4030 Resource %d group could not be read\n",
	330	rconfig->resource);
	331	return err;
	332	}
	333
56baa667	334	if (rconfig->devgroup != TWL4030_RESCONFIG_UNDEF) {
e97d1546 AK	335	grp &= ~DEV_GRP_MASK;
e97d1546 AK	336	grp \|= rconfig->devgroup << DEV_GRP_SHIFT;
4850f124	337	err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
fc7b92fc	338	grp, rconfig_addr + DEV_GRP_OFFSET);
ebf0bd36 AK	339	if (err < 0) {
	340	pr_err("TWL4030 failed to program devgroup\n");
	341	return err;
	342	}
	343	}
	344
	345	/* Set resource types */
4850f124	346	err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &type,
ebf0bd36 AK	347	rconfig_addr + TYPE_OFFSET);
	348	if (err < 0) {
	349	pr_err("TWL4030 Resource %d type could not be read\n",
	350	rconfig->resource);
	351	return err;
	352	}
	353
56baa667	354	if (rconfig->type != TWL4030_RESCONFIG_UNDEF) {
ebf0bd36 AK	355	type &= ~TYPE_MASK;
	356	type \|= rconfig->type << TYPE_SHIFT;
	357	}
	358
56baa667	359	if (rconfig->type2 != TWL4030_RESCONFIG_UNDEF) {
ebf0bd36 AK	360	type &= ~TYPE2_MASK;
	361	type \|= rconfig->type2 << TYPE2_SHIFT;
	362	}
	363
4850f124	364	err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
ebf0bd36 AK	365	type, rconfig_addr + TYPE_OFFSET);
	366	if (err < 0) {
	367	pr_err("TWL4030 failed to program resource type\n");
	368	return err;
	369	}
	370
b4ead61e	371	/* Set remap states */
4850f124	372	err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &remap,
fc7b92fc	373	rconfig_addr + REMAP_OFFSET);
b4ead61e AK	374	if (err < 0) {
	375	pr_err("TWL4030 Resource %d remap could not be read\n",
	376	rconfig->resource);
	377	return err;
	378	}
	379
53cf9a60	380	if (rconfig->remap_off != TWL4030_RESCONFIG_UNDEF) {
b4ead61e AK	381	remap &= ~OFF_STATE_MASK;
	382	remap \|= rconfig->remap_off << OFF_STATE_SHIFT;
	383	}
	384
53cf9a60	385	if (rconfig->remap_sleep != TWL4030_RESCONFIG_UNDEF) {
b4ead61e	386	remap &= ~SLEEP_STATE_MASK;
1ea933f4	387	remap \|= rconfig->remap_sleep << SLEEP_STATE_SHIFT;
b4ead61e AK	388	}
b4ead61e AK	389
4850f124	390	err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
fc7b92fc B	391	remap,
fc7b92fc B	392	rconfig_addr + REMAP_OFFSET);
b4ead61e AK	393	if (err < 0) {
	394	pr_err("TWL4030 failed to program remap\n");
	395	return err;
	396	}
	397
ebf0bd36 AK	398	return 0;
	399	}
	400
f791be49	401	static int load_twl4030_script(struct twl4030_script *tscript,
ebf0bd36 AK	402	u8 address)
	403	{
	404	int err;
75a74565	405	static int order;
ebf0bd36 AK	406
	407	/* Make sure the script isn't going beyond last valid address (0x3f) */
	408	if ((address + tscript->size) > END_OF_SCRIPT) {
	409	pr_err("TWL4030 scripts too big error\n");
	410	return -EINVAL;
	411	}
	412
	413	err = twl4030_write_script(address, tscript->script, tscript->size);
	414	if (err)
	415	goto out;
	416
	417	if (tscript->flags & TWL4030_WRST_SCRIPT) {
	418	err = twl4030_config_warmreset_sequence(address);
	419	if (err)
	420	goto out;
	421	}
	422	if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) {
	423	err = twl4030_config_wakeup12_sequence(address);
	424	if (err)
	425	goto out;
75a74565	426	order = 1;
ebf0bd36 AK	427	}
	428	if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) {
	429	err = twl4030_config_wakeup3_sequence(address);
	430	if (err)
	431	goto out;
	432	}
c62dd365	433	if (tscript->flags & TWL4030_SLEEP_SCRIPT) {
1f968ff6	434	if (!order)
75a74565 AK	435	pr_warning("TWL4030: Bad order of scripts (sleep "\
	436	"script before wakeup) Leads to boot"\
	437	"failure on some boards\n");
ebf0bd36	438	err = twl4030_config_sleep_sequence(address);
c62dd365	439	}
ebf0bd36 AK	440	out:
	441	return err;
	442	}
	443
11a441ce MT	444	int twl4030_remove_script(u8 flags)
	445	{
	446	int err = 0;
	447
4850f124 PU	448	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
4850f124 PU	449	TWL4030_PM_MASTER_PROTECT_KEY);
11a441ce MT	450	if (err) {
	451	pr_err("twl4030: unable to unlock PROTECT_KEY\n");
	452	return err;
	453	}
	454
4850f124 PU	455	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
4850f124 PU	456	TWL4030_PM_MASTER_PROTECT_KEY);
11a441ce MT	457	if (err) {
	458	pr_err("twl4030: unable to unlock PROTECT_KEY\n");
	459	return err;
	460	}
	461
	462	if (flags & TWL4030_WRST_SCRIPT) {
4850f124 PU	463	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
4850f124 PU	464	R_SEQ_ADD_WARM);
11a441ce MT	465	if (err)
	466	return err;
	467	}
	468	if (flags & TWL4030_WAKEUP12_SCRIPT) {
4850f124 PU	469	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
4850f124 PU	470	R_SEQ_ADD_S2A12);
eac78a21	471	if (err)
11a441ce MT	472	return err;
	473	}
	474	if (flags & TWL4030_WAKEUP3_SCRIPT) {
4850f124 PU	475	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
4850f124 PU	476	R_SEQ_ADD_S2A3);
11a441ce MT	477	if (err)
	478	return err;
	479	}
	480	if (flags & TWL4030_SLEEP_SCRIPT) {
4850f124 PU	481	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
4850f124 PU	482	R_SEQ_ADD_A2S);
11a441ce MT	483	if (err)
	484	return err;
	485	}
	486
4850f124 PU	487	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
4850f124 PU	488	TWL4030_PM_MASTER_PROTECT_KEY);
11a441ce MT	489	if (err)
	490	pr_err("TWL4030 Unable to relock registers\n");
	491
	492	return err;
	493	}
	494
26cc3ab9 IG	495	/*
	496	* In master mode, start the power off sequence.
	497	* After a successful execution, TWL shuts down the power to the SoC
	498	* and all peripherals connected to it.
	499	*/
	500	void twl4030_power_off(void)
	501	{
	502	int err;
	503
4850f124	504	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, PWR_DEVOFF,
26cc3ab9 IG	505	TWL4030_PM_MASTER_P1_SW_EVENTS);
	506	if (err)
	507	pr_err("TWL4030 Unable to power off\n");
	508	}
	509
f791be49	510	void twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
ebf0bd36 AK	511	{
	512	int err = 0;
	513	int i;
	514	struct twl4030_resconfig *resconfig;
26cc3ab9	515	u8 val, address = twl4030_start_script_address;
ebf0bd36	516
4850f124 PU	517	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
4850f124 PU	518	TWL4030_PM_MASTER_PROTECT_KEY);
ebf0bd36 AK	519	if (err)
	520	goto unlock;
	521
4850f124 PU	522	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
4850f124 PU	523	TWL4030_PM_MASTER_PROTECT_KEY);
ebf0bd36 AK	524	if (err)
	525	goto unlock;
	526
	527	for (i = 0; i < twl4030_scripts->num; i++) {
	528	err = load_twl4030_script(twl4030_scripts->scripts[i], address);
	529	if (err)
	530	goto load;
	531	address += twl4030_scripts->scripts[i]->size;
	532	}
	533
	534	resconfig = twl4030_scripts->resource_config;
	535	if (resconfig) {
	536	while (resconfig->resource) {
	537	err = twl4030_configure_resource(resconfig);
	538	if (err)
	539	goto resource;
	540	resconfig++;
	541
	542	}
	543	}
	544
26cc3ab9 IG	545	/* Board has to be wired properly to use this feature */
	546	if (twl4030_scripts->use_poweroff && !pm_power_off) {
	547	/* Default for SEQ_OFFSYNC is set, lets ensure this */
4850f124	548	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
26cc3ab9 IG	549	TWL4030_PM_MASTER_CFG_P123_TRANSITION);
	550	if (err) {
	551	pr_warning("TWL4030 Unable to read registers\n");
	552
	553	} else if (!(val & SEQ_OFFSYNC)) {
	554	val \|= SEQ_OFFSYNC;
4850f124	555	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val,
26cc3ab9 IG	556	TWL4030_PM_MASTER_CFG_P123_TRANSITION);
	557	if (err) {
	558	pr_err("TWL4030 Unable to setup SEQ_OFFSYNC\n");
	559	goto relock;
	560	}
	561	}
	562
	563	pm_power_off = twl4030_power_off;
	564	}
	565
	566	relock:
4850f124 PU	567	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
4850f124 PU	568	TWL4030_PM_MASTER_PROTECT_KEY);
ebf0bd36 AK	569	if (err)
	570	pr_err("TWL4030 Unable to relock registers\n");
	571	return;
	572
	573	unlock:
	574	if (err)
	575	pr_err("TWL4030 Unable to unlock registers\n");
	576	return;
	577	load:
	578	if (err)
	579	pr_err("TWL4030 failed to load scripts\n");
	580	return;
	581	resource:
	582	if (err)
	583	pr_err("TWL4030 failed to configure resource\n");
	584	return;
	585	}