[mirror_ubuntu-zesty-kernel.git] / drivers / mfd / twl6030-irq.c

/*
 * twl6030-irq.c - TWL6030 irq support
 *
 * Copyright (C) 2005-2009 Texas Instruments, Inc.
 *
 * Modifications to defer interrupt handling to a kernel thread:
 * Copyright (C) 2006 MontaVista Software, Inc.
 *
 * Based on tlv320aic23.c:
 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
 *
 * Code cleanup and modifications to IRQ handler.
 * by syed khasim <x0khasim@ti.com>
 *
 * TWL6030 specific code and IRQ handling changes by
 * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
 * Balaji T K <balajitk@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kthread.h>
#include <linux/i2c/twl.h>
#include <linux/platform_device.h>
#include <linux/suspend.h>
#include <linux/of.h>
#include <linux/irqdomain.h>
#include <linux/of_device.h>

#include "twl-core.h"

/*
 * TWL6030 (unlike its predecessors, which had two level interrupt handling)
 * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
 * It exposes status bits saying who has raised an interrupt. There are
 * three mask registers that corresponds to these status registers, that
 * enables/disables these interrupts.
 *
 * We set up IRQs starting at a platform-specified base. An interrupt map table,
 * specifies mapping between interrupt number and the associated module.
 */
#define TWL6030_NR_IRQS    20

static int twl6030_interrupt_mapping[24] = {
	PWR_INTR_OFFSET,	/* Bit 0	PWRON			*/
	PWR_INTR_OFFSET,	/* Bit 1	RPWRON			*/
	PWR_INTR_OFFSET,	/* Bit 2	BAT_VLOW		*/
	RTC_INTR_OFFSET,	/* Bit 3	RTC_ALARM		*/
	RTC_INTR_OFFSET,	/* Bit 4	RTC_PERIOD		*/
	HOTDIE_INTR_OFFSET,	/* Bit 5	HOT_DIE			*/
	SMPSLDO_INTR_OFFSET,	/* Bit 6	VXXX_SHORT		*/
	SMPSLDO_INTR_OFFSET,	/* Bit 7	VMMC_SHORT		*/

	SMPSLDO_INTR_OFFSET,	/* Bit 8	VUSIM_SHORT		*/
	BATDETECT_INTR_OFFSET,	/* Bit 9	BAT			*/
	SIMDETECT_INTR_OFFSET,	/* Bit 10	SIM			*/
	MMCDETECT_INTR_OFFSET,	/* Bit 11	MMC			*/
	RSV_INTR_OFFSET,	/* Bit 12	Reserved		*/
	MADC_INTR_OFFSET,	/* Bit 13	GPADC_RT_EOC		*/
	MADC_INTR_OFFSET,	/* Bit 14	GPADC_SW_EOC		*/
	GASGAUGE_INTR_OFFSET,	/* Bit 15	CC_AUTOCAL		*/

	USBOTG_INTR_OFFSET,	/* Bit 16	ID_WKUP			*/
	USBOTG_INTR_OFFSET,	/* Bit 17	VBUS_WKUP		*/
	USBOTG_INTR_OFFSET,	/* Bit 18	ID			*/
	USB_PRES_INTR_OFFSET,	/* Bit 19	VBUS			*/
	CHARGER_INTR_OFFSET,	/* Bit 20	CHRG_CTRL		*/
	CHARGERFAULT_INTR_OFFSET,	/* Bit 21	EXT_CHRG	*/
	CHARGERFAULT_INTR_OFFSET,	/* Bit 22	INT_CHRG	*/
	RSV_INTR_OFFSET,	/* Bit 23	Reserved		*/
};

static int twl6032_interrupt_mapping[24] = {
	PWR_INTR_OFFSET,	/* Bit 0	PWRON			*/
	PWR_INTR_OFFSET,	/* Bit 1	RPWRON			*/
	PWR_INTR_OFFSET,	/* Bit 2	SYS_VLOW		*/
	RTC_INTR_OFFSET,	/* Bit 3	RTC_ALARM		*/
	RTC_INTR_OFFSET,	/* Bit 4	RTC_PERIOD		*/
	HOTDIE_INTR_OFFSET,	/* Bit 5	HOT_DIE			*/
	SMPSLDO_INTR_OFFSET,	/* Bit 6	VXXX_SHORT		*/
	PWR_INTR_OFFSET,	/* Bit 7	SPDURATION		*/

	PWR_INTR_OFFSET,	/* Bit 8	WATCHDOG		*/
	BATDETECT_INTR_OFFSET,	/* Bit 9	BAT			*/
	SIMDETECT_INTR_OFFSET,	/* Bit 10	SIM			*/
	MMCDETECT_INTR_OFFSET,	/* Bit 11	MMC			*/
	MADC_INTR_OFFSET,	/* Bit 12	GPADC_RT_EOC		*/
	MADC_INTR_OFFSET,	/* Bit 13	GPADC_SW_EOC		*/
	GASGAUGE_INTR_OFFSET,	/* Bit 14	CC_EOC			*/
	GASGAUGE_INTR_OFFSET,	/* Bit 15	CC_AUTOCAL		*/

	USBOTG_INTR_OFFSET,	/* Bit 16	ID_WKUP			*/
	USBOTG_INTR_OFFSET,	/* Bit 17	VBUS_WKUP		*/
	USBOTG_INTR_OFFSET,	/* Bit 18	ID			*/
	USB_PRES_INTR_OFFSET,	/* Bit 19	VBUS			*/
	CHARGER_INTR_OFFSET,	/* Bit 20	CHRG_CTRL		*/
	CHARGERFAULT_INTR_OFFSET,	/* Bit 21	EXT_CHRG	*/
	CHARGERFAULT_INTR_OFFSET,	/* Bit 22	INT_CHRG	*/
	RSV_INTR_OFFSET,	/* Bit 23	Reserved		*/
};

/*----------------------------------------------------------------------*/

struct twl6030_irq {
	unsigned int		irq_base;
	int			twl_irq;
	bool			irq_wake_enabled;
	atomic_t		wakeirqs;
	struct notifier_block	pm_nb;
	struct irq_chip		irq_chip;
	struct irq_domain	*irq_domain;
	const int		*irq_mapping_tbl;
};

static struct twl6030_irq *twl6030_irq;

static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
				   unsigned long pm_event, void *unused)
{
	int chained_wakeups;
	struct twl6030_irq *pdata = container_of(notifier, struct twl6030_irq,
						  pm_nb);

	switch (pm_event) {
	case PM_SUSPEND_PREPARE:
		chained_wakeups = atomic_read(&pdata->wakeirqs);

		if (chained_wakeups && !pdata->irq_wake_enabled) {
			if (enable_irq_wake(pdata->twl_irq))
				pr_err("twl6030 IRQ wake enable failed\n");
			else
				pdata->irq_wake_enabled = true;
		} else if (!chained_wakeups && pdata->irq_wake_enabled) {
			disable_irq_wake(pdata->twl_irq);
			pdata->irq_wake_enabled = false;
		}

		disable_irq(pdata->twl_irq);
		break;

	case PM_POST_SUSPEND:
		enable_irq(pdata->twl_irq);
		break;

	default:
		break;
	}

	return NOTIFY_DONE;
}

/*
* Threaded irq handler for the twl6030 interrupt.
* We query the interrupt controller in the twl6030 to determine
* which module is generating the interrupt request and call
* handle_nested_irq for that module.
*/
static irqreturn_t twl6030_irq_thread(int irq, void *data)
{
	int i, ret;
	union {
		u8 bytes[4];
		__le32 int_sts;
	} sts;
	u32 int_sts; /* sts.int_sts converted to CPU endianness */
	struct twl6030_irq *pdata = data;

	/* read INT_STS_A, B and C in one shot using a burst read */
	ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, REG_INT_STS_A, 3);
	if (ret) {
		pr_warn("twl6030_irq: I2C error %d reading PIH ISR\n", ret);
		return IRQ_HANDLED;
	}

	sts.bytes[3] = 0; /* Only 24 bits are valid*/

	/*
	 * Since VBUS status bit is not reliable for VBUS disconnect
	 * use CHARGER VBUS detection status bit instead.
	 */
	if (sts.bytes[2] & 0x10)
		sts.bytes[2] |= 0x08;

	int_sts = le32_to_cpu(sts.int_sts);
	for (i = 0; int_sts; int_sts >>= 1, i++)
		if (int_sts & 0x1) {
			int module_irq =
				irq_find_mapping(pdata->irq_domain,
						 pdata->irq_mapping_tbl[i]);
			if (module_irq)
				handle_nested_irq(module_irq);
			else
				pr_err("twl6030_irq: Unmapped PIH ISR %u detected\n",
				       i);
			pr_debug("twl6030_irq: PIH ISR %u, virq%u\n",
				 i, module_irq);
		}

	/*
	 * NOTE:
	 * Simulation confirms that documentation is wrong w.r.t the
	 * interrupt status clear operation. A single *byte* write to
	 * any one of STS_A to STS_C register results in all three
	 * STS registers being reset. Since it does not matter which
	 * value is written, all three registers are cleared on a
	 * single byte write, so we just use 0x0 to clear.
	 */
	ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
	if (ret)
		pr_warn("twl6030_irq: I2C error in clearing PIH ISR\n");

	return IRQ_HANDLED;
}

/*----------------------------------------------------------------------*/

static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct twl6030_irq *pdata = irq_data_get_irq_chip_data(d);

	if (on)
		atomic_inc(&pdata->wakeirqs);
	else
		atomic_dec(&pdata->wakeirqs);

	return 0;
}

int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
{
	int ret;
	u8 unmask_value;

	ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
			REG_INT_STS_A + offset);
	unmask_value &= (~(bit_mask));
	ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
			REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
	return ret;
}
EXPORT_SYMBOL(twl6030_interrupt_unmask);

int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
{
	int ret;
	u8 mask_value;

	ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
			REG_INT_STS_A + offset);
	mask_value |= (bit_mask);
	ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
			REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
	return ret;
}
EXPORT_SYMBOL(twl6030_interrupt_mask);

int twl6030_mmc_card_detect_config(void)
{
	int ret;
	u8 reg_val = 0;

	/* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
	twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
						REG_INT_MSK_LINE_B);
	twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
						REG_INT_MSK_STS_B);
	/*
	 * Initially Configuring MMC_CTRL for receiving interrupts &
	 * Card status on TWL6030 for MMC1
	 */
	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL);
	if (ret < 0) {
		pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
		return ret;
	}
	reg_val &= ~VMMC_AUTO_OFF;
	reg_val |= SW_FC;
	ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
	if (ret < 0) {
		pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
		return ret;
	}

	/* Configuring PullUp-PullDown register */
	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val,
						TWL6030_CFG_INPUT_PUPD3);
	if (ret < 0) {
		pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
									ret);
		return ret;
	}
	reg_val &= ~(MMC_PU | MMC_PD);
	ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
						TWL6030_CFG_INPUT_PUPD3);
	if (ret < 0) {
		pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
									ret);
		return ret;
	}

	return irq_find_mapping(twl6030_irq->irq_domain,
				 MMCDETECT_INTR_OFFSET);
}
EXPORT_SYMBOL(twl6030_mmc_card_detect_config);

int twl6030_mmc_card_detect(struct device *dev, int slot)
{
	int ret = -EIO;
	u8 read_reg = 0;
	struct platform_device *pdev = to_platform_device(dev);

	if (pdev->id) {
		/* TWL6030 provide's Card detect support for
		 * only MMC1 controller.
		 */
		pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
		return ret;
	}
	/*
	 * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
	 * 0 - Card not present ,1 - Card present
	 */
	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
						TWL6030_MMCCTRL);
	if (ret >= 0)
		ret = read_reg & STS_MMC;
	return ret;
}
EXPORT_SYMBOL(twl6030_mmc_card_detect);

static int twl6030_irq_map(struct irq_domain *d, unsigned int virq,
			      irq_hw_number_t hwirq)
{
	struct twl6030_irq *pdata = d->host_data;

	irq_set_chip_data(virq, pdata);
	irq_set_chip_and_handler(virq,  &pdata->irq_chip, handle_simple_irq);
	irq_set_nested_thread(virq, true);
	irq_set_parent(virq, pdata->twl_irq);
	irq_set_noprobe(virq);

	return 0;
}

static void twl6030_irq_unmap(struct irq_domain *d, unsigned int virq)
{
	irq_set_chip_and_handler(virq, NULL, NULL);
	irq_set_chip_data(virq, NULL);
}

static const struct irq_domain_ops twl6030_irq_domain_ops = {
	.map	= twl6030_irq_map,
	.unmap	= twl6030_irq_unmap,
	.xlate	= irq_domain_xlate_onetwocell,
};

static const struct of_device_id twl6030_of_match[] = {
	{.compatible = "ti,twl6030", &twl6030_interrupt_mapping},
	{.compatible = "ti,twl6032", &twl6032_interrupt_mapping},
	{ },
};

int twl6030_init_irq(struct device *dev, int irq_num)
{
	struct			device_node *node = dev->of_node;
	int			nr_irqs;
	int			status;
	u8			mask[3];
	const struct of_device_id *of_id;

	of_id = of_match_device(twl6030_of_match, dev);
	if (!of_id || !of_id->data) {
		dev_err(dev, "Unknown TWL device model\n");
		return -EINVAL;
	}

	nr_irqs = TWL6030_NR_IRQS;

	twl6030_irq = devm_kzalloc(dev, sizeof(*twl6030_irq), GFP_KERNEL);
	if (!twl6030_irq) {
		dev_err(dev, "twl6030_irq: Memory allocation failed\n");
		return -ENOMEM;
	}

	mask[0] = 0xFF;
	mask[1] = 0xFF;
	mask[2] = 0xFF;

	/* mask all int lines */
	status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
	/* mask all int sts */
	status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
	/* clear INT_STS_A,B,C */
	status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);

	if (status < 0) {
		dev_err(dev, "I2C err writing TWL_MODULE_PIH: %d\n", status);
		return status;
	}

	/*
	 * install an irq handler for each of the modules;
	 * clone dummy irq_chip since PIH can't *do* anything
	 */
	twl6030_irq->irq_chip = dummy_irq_chip;
	twl6030_irq->irq_chip.name = "twl6030";
	twl6030_irq->irq_chip.irq_set_type = NULL;
	twl6030_irq->irq_chip.irq_set_wake = twl6030_irq_set_wake;

	twl6030_irq->pm_nb.notifier_call = twl6030_irq_pm_notifier;
	atomic_set(&twl6030_irq->wakeirqs, 0);
	twl6030_irq->irq_mapping_tbl = of_id->data;

	twl6030_irq->irq_domain =
		irq_domain_add_linear(node, nr_irqs,
				      &twl6030_irq_domain_ops, twl6030_irq);
	if (!twl6030_irq->irq_domain) {
		dev_err(dev, "Can't add irq_domain\n");
		return -ENOMEM;
	}

	dev_info(dev, "PIH (irq %d) nested IRQs\n", irq_num);

	/* install an irq handler to demultiplex the TWL6030 interrupt */
	status = request_threaded_irq(irq_num, NULL, twl6030_irq_thread,
				      IRQF_ONESHOT, "TWL6030-PIH", twl6030_irq);
	if (status < 0) {
		dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
		goto fail_irq;
	}

	twl6030_irq->twl_irq = irq_num;
	register_pm_notifier(&twl6030_irq->pm_nb);
	return 0;

fail_irq:
	irq_domain_remove(twl6030_irq->irq_domain);
	return status;
}

int twl6030_exit_irq(void)
{
	if (twl6030_irq && twl6030_irq->twl_irq) {
		unregister_pm_notifier(&twl6030_irq->pm_nb);
		free_irq(twl6030_irq->twl_irq, NULL);
		/*
		 * TODO: IRQ domain and allocated nested IRQ descriptors
		 * should be freed somehow here. Now It can't be done, because
		 * child devices will not be deleted during removing of
		 * TWL Core driver and they will still contain allocated
		 * virt IRQs in their Resources tables.
		 * The same prevents us from using devm_request_threaded_irq()
		 * in this module.
		 */
	}
	return 0;
}
Commit	Line	Data
e8deb28c B	1	/*
	2	* twl6030-irq.c - TWL6030 irq support
	3	*
	4	* Copyright (C) 2005-2009 Texas Instruments, Inc.
	5	*
	6	* Modifications to defer interrupt handling to a kernel thread:
	7	* Copyright (C) 2006 MontaVista Software, Inc.
	8	*
	9	* Based on tlv320aic23.c:
	10	* Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
	11	*
	12	* Code cleanup and modifications to IRQ handler.
	13	* by syed khasim <x0khasim@ti.com>
	14	*
	15	* TWL6030 specific code and IRQ handling changes by
	16	* Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
	17	* Balaji T K <balajitk@ti.com>
	18	*
	19	* This program is free software; you can redistribute it and/or modify
	20	* it under the terms of the GNU General Public License as published by
	21	* the Free Software Foundation; either version 2 of the License, or
	22	* (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	32	*/
	33
5d4a357d	34	#include <linux/export.h>
e8deb28c B	35	#include <linux/interrupt.h>
	36	#include <linux/irq.h>
	37	#include <linux/kthread.h>
	38	#include <linux/i2c/twl.h>
72f2e2c7	39	#include <linux/platform_device.h>
ab2b9260	40	#include <linux/suspend.h>
78518ffa BC	41	#include <linux/of.h>
78518ffa BC	42	#include <linux/irqdomain.h>
74d85e47	43	#include <linux/of_device.h>
e8deb28c	44
b0b4a7c2 MK	45	#include "twl-core.h"
b0b4a7c2 MK	46
e8deb28c B	47	/*
	48	* TWL6030 (unlike its predecessors, which had two level interrupt handling)
	49	* three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
	50	* It exposes status bits saying who has raised an interrupt. There are
	51	* three mask registers that corresponds to these status registers, that
	52	* enables/disables these interrupts.
	53	*
	54	* We set up IRQs starting at a platform-specified base. An interrupt map table,
	55	* specifies mapping between interrupt number and the associated module.
e8deb28c	56	*/
78518ffa	57	#define TWL6030_NR_IRQS 20
e8deb28c B	58
	59	static int twl6030_interrupt_mapping[24] = {
	60	PWR_INTR_OFFSET, /* Bit 0 PWRON */
	61	PWR_INTR_OFFSET, /* Bit 1 RPWRON */
	62	PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
	63	RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
	64	RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
	65	HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
	66	SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
	67	SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
	68
	69	SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
	70	BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
	71	SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
	72	MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
3103de8c	73	RSV_INTR_OFFSET, /* Bit 12 Reserved */
e8deb28c B	74	MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
	75	MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
	76	GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
	77
	78	USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
	79	USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
	80	USBOTG_INTR_OFFSET, /* Bit 18 ID */
77b1d3fa	81	USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
e8deb28c	82	CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
6523b148 GG	83	CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
6523b148 GG	84	CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
e8deb28c B	85	RSV_INTR_OFFSET, /* Bit 23 Reserved */
e8deb28c B	86	};
74d85e47 OD	87
	88	static int twl6032_interrupt_mapping[24] = {
	89	PWR_INTR_OFFSET, /* Bit 0 PWRON */
	90	PWR_INTR_OFFSET, /* Bit 1 RPWRON */
	91	PWR_INTR_OFFSET, /* Bit 2 SYS_VLOW */
	92	RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
	93	RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
	94	HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
	95	SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
	96	PWR_INTR_OFFSET, /* Bit 7 SPDURATION */
	97
	98	PWR_INTR_OFFSET, /* Bit 8 WATCHDOG */
	99	BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
	100	SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
	101	MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
	102	MADC_INTR_OFFSET, /* Bit 12 GPADC_RT_EOC */
	103	MADC_INTR_OFFSET, /* Bit 13 GPADC_SW_EOC */
	104	GASGAUGE_INTR_OFFSET, /* Bit 14 CC_EOC */
	105	GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
	106
	107	USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
	108	USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
	109	USBOTG_INTR_OFFSET, /* Bit 18 ID */
	110	USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
	111	CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
	112	CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
	113	CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
	114	RSV_INTR_OFFSET, /* Bit 23 Reserved */
	115	};
	116
e8deb28c B	117	/----------------------------------------------------------------------/
e8deb28c B	118
0aa8c685 GS	119	struct twl6030_irq {
	120	unsigned int irq_base;
	121	int twl_irq;
	122	bool irq_wake_enabled;
	123	atomic_t wakeirqs;
	124	struct notifier_block pm_nb;
	125	struct irq_chip irq_chip;
	126	struct irq_domain *irq_domain;
74d85e47	127	const int *irq_mapping_tbl;
0aa8c685	128	};
e8deb28c	129
0aa8c685	130	static struct twl6030_irq *twl6030_irq;
ab2b9260 TP	131
	132	static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
	133	unsigned long pm_event, void *unused)
	134	{
	135	int chained_wakeups;
0aa8c685 GS	136	struct twl6030_irq *pdata = container_of(notifier, struct twl6030_irq,
0aa8c685 GS	137	pm_nb);
ab2b9260 TP	138
	139	switch (pm_event) {
	140	case PM_SUSPEND_PREPARE:
0aa8c685	141	chained_wakeups = atomic_read(&pdata->wakeirqs);
ab2b9260	142
0aa8c685 GS	143	if (chained_wakeups && !pdata->irq_wake_enabled) {
0aa8c685 GS	144	if (enable_irq_wake(pdata->twl_irq))
ab2b9260 TP	145	pr_err("twl6030 IRQ wake enable failed\n");
ab2b9260 TP	146	else
0aa8c685 GS	147	pdata->irq_wake_enabled = true;
	148	} else if (!chained_wakeups && pdata->irq_wake_enabled) {
	149	disable_irq_wake(pdata->twl_irq);
	150	pdata->irq_wake_enabled = false;
ab2b9260 TP	151	}
ab2b9260 TP	152
0aa8c685	153	disable_irq(pdata->twl_irq);
ab2b9260	154	break;
782baa20 TP	155
782baa20 TP	156	case PM_POST_SUSPEND:
0aa8c685	157	enable_irq(pdata->twl_irq);
782baa20 TP	158	break;
782baa20 TP	159
ab2b9260 TP	160	default:
	161	break;
	162	}
	163
	164	return NOTIFY_DONE;
	165	}
	166
e8deb28c	167	/*
87343e53 NVS	168	* Threaded irq handler for the twl6030 interrupt.
	169	* We query the interrupt controller in the twl6030 to determine
	170	* which module is generating the interrupt request and call
	171	* handle_nested_irq for that module.
	172	*/
	173	static irqreturn_t twl6030_irq_thread(int irq, void *data)
e8deb28c	174	{
87343e53 NVS	175	int i, ret;
87343e53 NVS	176	union {
e8deb28c	177	u8 bytes[4];
754fa7bc	178	__le32 int_sts;
87343e53	179	} sts;
754fa7bc	180	u32 int_sts; /* sts.int_sts converted to CPU endianness */
0aa8c685	181	struct twl6030_irq *pdata = data;
e8deb28c	182
87343e53 NVS	183	/* read INT_STS_A, B and C in one shot using a burst read */
	184	ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, REG_INT_STS_A, 3);
	185	if (ret) {
	186	pr_warn("twl6030_irq: I2C error %d reading PIH ISR\n", ret);
	187	return IRQ_HANDLED;
	188	}
e8deb28c	189
87343e53	190	sts.bytes[3] = 0; /* Only 24 bits are valid*/
e8deb28c	191
87343e53 NVS	192	/*
	193	* Since VBUS status bit is not reliable for VBUS disconnect
	194	* use CHARGER VBUS detection status bit instead.
	195	*/
	196	if (sts.bytes[2] & 0x10)
	197	sts.bytes[2] \|= 0x08;
77b1d3fa	198
754fa7bc DX	199	int_sts = le32_to_cpu(sts.int_sts);
	200	for (i = 0; int_sts; int_sts >>= 1, i++)
	201	if (int_sts & 0x1) {
b32408f6	202	int module_irq =
0aa8c685	203	irq_find_mapping(pdata->irq_domain,
74d85e47	204	pdata->irq_mapping_tbl[i]);
b32408f6 GS	205	if (module_irq)
	206	handle_nested_irq(module_irq);
	207	else
	208	pr_err("twl6030_irq: Unmapped PIH ISR %u detected\n",
	209	i);
87343e53 NVS	210	pr_debug("twl6030_irq: PIH ISR %u, virq%u\n",
87343e53 NVS	211	i, module_irq);
e8deb28c	212	}
3f8349e6	213
87343e53 NVS	214	/*
	215	* NOTE:
	216	* Simulation confirms that documentation is wrong w.r.t the
	217	* interrupt status clear operation. A single byte write to
	218	* any one of STS_A to STS_C register results in all three
	219	* STS registers being reset. Since it does not matter which
	220	* value is written, all three registers are cleared on a
	221	* single byte write, so we just use 0x0 to clear.
	222	*/
	223	ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
	224	if (ret)
	225	pr_warn("twl6030_irq: I2C error in clearing PIH ISR\n");
e8deb28c	226
e8deb28c B	227	return IRQ_HANDLED;
	228	}
	229
	230	/----------------------------------------------------------------------/
	231
b8b8d793	232	static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
49dcd070	233	{
1e84aa44	234	struct twl6030_irq *pdata = irq_data_get_irq_chip_data(d);
0aa8c685	235
ab2b9260	236	if (on)
0aa8c685	237	atomic_inc(&pdata->wakeirqs);
ab2b9260	238	else
0aa8c685	239	atomic_dec(&pdata->wakeirqs);
49dcd070	240
ab2b9260	241	return 0;
49dcd070 SS	242	}
49dcd070 SS	243
e8deb28c B	244	int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
	245	{
	246	int ret;
	247	u8 unmask_value;
3103de8c	248
e8deb28c B	249	ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
	250	REG_INT_STS_A + offset);
	251	unmask_value &= (~(bit_mask));
	252	ret \|= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
	253	REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
	254	return ret;
	255	}
	256	EXPORT_SYMBOL(twl6030_interrupt_unmask);
	257
	258	int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
	259	{
	260	int ret;
	261	u8 mask_value;
3103de8c	262
e8deb28c B	263	ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
	264	REG_INT_STS_A + offset);
	265	mask_value \|= (bit_mask);
	266	ret \|= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
	267	REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
	268	return ret;
	269	}
	270	EXPORT_SYMBOL(twl6030_interrupt_mask);
	271
72f2e2c7	272	int twl6030_mmc_card_detect_config(void)
	273	{
	274	int ret;
	275	u8 reg_val = 0;
	276
	277	/* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
	278	twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
	279	REG_INT_MSK_LINE_B);
	280	twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
	281	REG_INT_MSK_STS_B);
	282	/*
25985edc	283	* Initially Configuring MMC_CTRL for receiving interrupts &
72f2e2c7	284	* Card status on TWL6030 for MMC1
	285	*/
	286	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL);
	287	if (ret < 0) {
	288	pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
	289	return ret;
	290	}
	291	reg_val &= ~VMMC_AUTO_OFF;
	292	reg_val \|= SW_FC;
	293	ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
	294	if (ret < 0) {
	295	pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
	296	return ret;
	297	}
	298
	299	/* Configuring PullUp-PullDown register */
	300	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val,
	301	TWL6030_CFG_INPUT_PUPD3);
	302	if (ret < 0) {
	303	pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
	304	ret);
	305	return ret;
	306	}
	307	reg_val &= ~(MMC_PU \| MMC_PD);
	308	ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
	309	TWL6030_CFG_INPUT_PUPD3);
	310	if (ret < 0) {
	311	pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
	312	ret);
	313	return ret;
	314	}
bdd61bc6	315
0aa8c685 GS	316	return irq_find_mapping(twl6030_irq->irq_domain,
0aa8c685 GS	317	MMCDETECT_INTR_OFFSET);
72f2e2c7	318	}
	319	EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
	320
	321	int twl6030_mmc_card_detect(struct device *dev, int slot)
	322	{
	323	int ret = -EIO;
	324	u8 read_reg = 0;
	325	struct platform_device *pdev = to_platform_device(dev);
	326
	327	if (pdev->id) {
	328	/* TWL6030 provide's Card detect support for
	329	* only MMC1 controller.
	330	*/
25985edc	331	pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
72f2e2c7	332	return ret;
	333	}
	334	/*
	335	* BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
	336	* 0 - Card not present ,1 - Card present
	337	*/
	338	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
	339	TWL6030_MMCCTRL);
	340	if (ret >= 0)
	341	ret = read_reg & STS_MMC;
	342	return ret;
	343	}
	344	EXPORT_SYMBOL(twl6030_mmc_card_detect);
	345
b32408f6 GS	346	static int twl6030_irq_map(struct irq_domain *d, unsigned int virq,
	347	irq_hw_number_t hwirq)
	348	{
0aa8c685 GS	349	struct twl6030_irq *pdata = d->host_data;
	350
	351	irq_set_chip_data(virq, pdata);
	352	irq_set_chip_and_handler(virq, &pdata->irq_chip, handle_simple_irq);
b32408f6	353	irq_set_nested_thread(virq, true);
0aa8c685	354	irq_set_parent(virq, pdata->twl_irq);
b32408f6	355	irq_set_noprobe(virq);
b32408f6 GS	356
	357	return 0;
	358	}
	359
	360	static void twl6030_irq_unmap(struct irq_domain *d, unsigned int virq)
	361	{
b32408f6 GS	362	irq_set_chip_and_handler(virq, NULL, NULL);
	363	irq_set_chip_data(virq, NULL);
	364	}
	365
7ce7b26f	366	static const struct irq_domain_ops twl6030_irq_domain_ops = {
b32408f6 GS	367	.map = twl6030_irq_map,
	368	.unmap = twl6030_irq_unmap,
	369	.xlate = irq_domain_xlate_onetwocell,
	370	};
	371
74d85e47 OD	372	static const struct of_device_id twl6030_of_match[] = {
	373	{.compatible = "ti,twl6030", &twl6030_interrupt_mapping},
	374	{.compatible = "ti,twl6032", &twl6032_interrupt_mapping},
	375	{ },
	376	};
	377
78518ffa	378	int twl6030_init_irq(struct device *dev, int irq_num)
e8deb28c	379	{
78518ffa	380	struct device_node *node = dev->of_node;
b32408f6	381	int nr_irqs;
a820e568	382	int status;
14591d88	383	u8 mask[3];
74d85e47 OD	384	const struct of_device_id *of_id;
	385
	386	of_id = of_match_device(twl6030_of_match, dev);
	387	if (!of_id \|\| !of_id->data) {
	388	dev_err(dev, "Unknown TWL device model\n");
	389	return -EINVAL;
	390	}
78518ffa BC	391
	392	nr_irqs = TWL6030_NR_IRQS;
	393
0aa8c685 GS	394	twl6030_irq = devm_kzalloc(dev, sizeof(*twl6030_irq), GFP_KERNEL);
	395	if (!twl6030_irq) {
	396	dev_err(dev, "twl6030_irq: Memory allocation failed\n");
	397	return -ENOMEM;
	398	}
	399
14591d88	400	mask[0] = 0xFF;
e8deb28c B	401	mask[1] = 0xFF;
e8deb28c B	402	mask[2] = 0xFF;
ec1a07b3 BC	403
ec1a07b3 BC	404	/* mask all int lines */
a820e568	405	status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
ec1a07b3	406	/* mask all int sts */
a820e568	407	status \|= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
ec1a07b3	408	/* clear INT_STS_A,B,C */
a820e568 GS	409	status \|= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
	410
	411	if (status < 0) {
	412	dev_err(dev, "I2C err writing TWL_MODULE_PIH: %d\n", status);
	413	return status;
	414	}
e8deb28c	415
ec1a07b3 BC	416	/*
ec1a07b3 BC	417	* install an irq handler for each of the modules;
e8deb28c B	418	* clone dummy irq_chip since PIH can't do anything
e8deb28c B	419	*/
0aa8c685 GS	420	twl6030_irq->irq_chip = dummy_irq_chip;
	421	twl6030_irq->irq_chip.name = "twl6030";
	422	twl6030_irq->irq_chip.irq_set_type = NULL;
	423	twl6030_irq->irq_chip.irq_set_wake = twl6030_irq_set_wake;
	424
	425	twl6030_irq->pm_nb.notifier_call = twl6030_irq_pm_notifier;
	426	atomic_set(&twl6030_irq->wakeirqs, 0);
74d85e47	427	twl6030_irq->irq_mapping_tbl = of_id->data;
0aa8c685 GS	428
	429	twl6030_irq->irq_domain =
	430	irq_domain_add_linear(node, nr_irqs,
	431	&twl6030_irq_domain_ops, twl6030_irq);
	432	if (!twl6030_irq->irq_domain) {
b32408f6 GS	433	dev_err(dev, "Can't add irq_domain\n");
b32408f6 GS	434	return -ENOMEM;
e8deb28c B	435	}
e8deb28c B	436
b32408f6	437	dev_info(dev, "PIH (irq %d) nested IRQs\n", irq_num);
e8deb28c B	438
e8deb28c B	439	/* install an irq handler to demultiplex the TWL6030 interrupt */
87343e53	440	status = request_threaded_irq(irq_num, NULL, twl6030_irq_thread,
0aa8c685	441	IRQF_ONESHOT, "TWL6030-PIH", twl6030_irq);
e8deb28c	442	if (status < 0) {
ec1a07b3	443	dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
e8deb28c B	444	goto fail_irq;
e8deb28c B	445	}
862de70c	446
0aa8c685 GS	447	twl6030_irq->twl_irq = irq_num;
0aa8c685 GS	448	register_pm_notifier(&twl6030_irq->pm_nb);
b32408f6	449	return 0;
e8deb28c	450
862de70c	451	fail_irq:
0aa8c685	452	irq_domain_remove(twl6030_irq->irq_domain);
e8deb28c B	453	return status;
	454	}
	455
	456	int twl6030_exit_irq(void)
	457	{
0aa8c685 GS	458	if (twl6030_irq && twl6030_irq->twl_irq) {
	459	unregister_pm_notifier(&twl6030_irq->pm_nb);
	460	free_irq(twl6030_irq->twl_irq, NULL);
b32408f6 GS	461	/*
	462	* TODO: IRQ domain and allocated nested IRQ descriptors
	463	* should be freed somehow here. Now It can't be done, because
	464	* child devices will not be deleted during removing of
	465	* TWL Core driver and they will still contain allocated
	466	* virt IRQs in their Resources tables.
	467	* The same prevents us from using devm_request_threaded_irq()
	468	* in this module.
	469	*/
e8deb28c B	470	}
	471	return 0;
	472	}
	473