[mirror_ubuntu-jammy-kernel.git] / drivers / mfd / twl6030-irq.c

/*
 * twl6030-irq.c - TWL6030 irq support
 *
 * Copyright (C) 2005-2009 Texas Instruments, Inc.
 *
 * Modifications to defer interrupt handling to a kernel thread:
 * Copyright (C) 2006 MontaVista Software, Inc.
 *
 * Based on tlv320aic23.c:
 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
 *
 * Code cleanup and modifications to IRQ handler.
 * by syed khasim <x0khasim@ti.com>
 *
 * TWL6030 specific code and IRQ handling changes by
 * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
 * Balaji T K <balajitk@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/init.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kthread.h>
#include <linux/i2c/twl.h>
#include <linux/platform_device.h>
#include <linux/suspend.h>
#include <linux/of.h>
#include <linux/irqdomain.h>

#include "twl-core.h"

/*
 * TWL6030 (unlike its predecessors, which had two level interrupt handling)
 * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
 * It exposes status bits saying who has raised an interrupt. There are
 * three mask registers that corresponds to these status registers, that
 * enables/disables these interrupts.
 *
 * We set up IRQs starting at a platform-specified base. An interrupt map table,
 * specifies mapping between interrupt number and the associated module.
 */
#define TWL6030_NR_IRQS    20

static int twl6030_interrupt_mapping[24] = {
	PWR_INTR_OFFSET,	/* Bit 0	PWRON			*/
	PWR_INTR_OFFSET,	/* Bit 1	RPWRON			*/
	PWR_INTR_OFFSET,	/* Bit 2	BAT_VLOW		*/
	RTC_INTR_OFFSET,	/* Bit 3	RTC_ALARM		*/
	RTC_INTR_OFFSET,	/* Bit 4	RTC_PERIOD		*/
	HOTDIE_INTR_OFFSET,	/* Bit 5	HOT_DIE			*/
	SMPSLDO_INTR_OFFSET,	/* Bit 6	VXXX_SHORT		*/
	SMPSLDO_INTR_OFFSET,	/* Bit 7	VMMC_SHORT		*/

	SMPSLDO_INTR_OFFSET,	/* Bit 8	VUSIM_SHORT		*/
	BATDETECT_INTR_OFFSET,	/* Bit 9	BAT			*/
	SIMDETECT_INTR_OFFSET,	/* Bit 10	SIM			*/
	MMCDETECT_INTR_OFFSET,	/* Bit 11	MMC			*/
	RSV_INTR_OFFSET,  	/* Bit 12	Reserved		*/
	MADC_INTR_OFFSET,	/* Bit 13	GPADC_RT_EOC		*/
	MADC_INTR_OFFSET,	/* Bit 14	GPADC_SW_EOC		*/
	GASGAUGE_INTR_OFFSET,	/* Bit 15	CC_AUTOCAL		*/

	USBOTG_INTR_OFFSET,	/* Bit 16	ID_WKUP			*/
	USBOTG_INTR_OFFSET,	/* Bit 17	VBUS_WKUP		*/
	USBOTG_INTR_OFFSET,	/* Bit 18	ID			*/
	USB_PRES_INTR_OFFSET,	/* Bit 19	VBUS			*/
	CHARGER_INTR_OFFSET,	/* Bit 20	CHRG_CTRL		*/
	CHARGERFAULT_INTR_OFFSET,	/* Bit 21	EXT_CHRG	*/
	CHARGERFAULT_INTR_OFFSET,	/* Bit 22	INT_CHRG	*/
	RSV_INTR_OFFSET,	/* Bit 23	Reserved		*/
};
/*----------------------------------------------------------------------*/

static unsigned twl6030_irq_base;
static int twl_irq;
static bool twl_irq_wake_enabled;

static atomic_t twl6030_wakeirqs = ATOMIC_INIT(0);

static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
				   unsigned long pm_event, void *unused)
{
	int chained_wakeups;

	switch (pm_event) {
	case PM_SUSPEND_PREPARE:
		chained_wakeups = atomic_read(&twl6030_wakeirqs);

		if (chained_wakeups && !twl_irq_wake_enabled) {
			if (enable_irq_wake(twl_irq))
				pr_err("twl6030 IRQ wake enable failed\n");
			else
				twl_irq_wake_enabled = true;
		} else if (!chained_wakeups && twl_irq_wake_enabled) {
			disable_irq_wake(twl_irq);
			twl_irq_wake_enabled = false;
		}

		disable_irq(twl_irq);
		break;

	case PM_POST_SUSPEND:
		enable_irq(twl_irq);
		break;

	default:
		break;
	}

	return NOTIFY_DONE;
}

static struct notifier_block twl6030_irq_pm_notifier_block = {
	.notifier_call = twl6030_irq_pm_notifier,
};

/*
* Threaded irq handler for the twl6030 interrupt.
* We query the interrupt controller in the twl6030 to determine
* which module is generating the interrupt request and call
* handle_nested_irq for that module.
*/
static irqreturn_t twl6030_irq_thread(int irq, void *data)
{
	int i, ret;
	union {
		u8 bytes[4];
		u32 int_sts;
	} sts;

	/* read INT_STS_A, B and C in one shot using a burst read */
	ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, REG_INT_STS_A, 3);
	if (ret) {
		pr_warn("twl6030_irq: I2C error %d reading PIH ISR\n", ret);
		return IRQ_HANDLED;
	}

	sts.bytes[3] = 0; /* Only 24 bits are valid*/

	/*
	 * Since VBUS status bit is not reliable for VBUS disconnect
	 * use CHARGER VBUS detection status bit instead.
	 */
	if (sts.bytes[2] & 0x10)
		sts.bytes[2] |= 0x08;

	for (i = 0; sts.int_sts; sts.int_sts >>= 1, i++)
		if (sts.int_sts & 0x1) {
			int module_irq = twl6030_irq_base +
					twl6030_interrupt_mapping[i];
			handle_nested_irq(module_irq);
			pr_debug("twl6030_irq: PIH ISR %u, virq%u\n",
				 i, module_irq);
		}

	/*
	 * NOTE:
	 * Simulation confirms that documentation is wrong w.r.t the
	 * interrupt status clear operation. A single *byte* write to
	 * any one of STS_A to STS_C register results in all three
	 * STS registers being reset. Since it does not matter which
	 * value is written, all three registers are cleared on a
	 * single byte write, so we just use 0x0 to clear.
	 */
	ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
	if (ret)
		pr_warn("twl6030_irq: I2C error in clearing PIH ISR\n");

	return IRQ_HANDLED;
}

/*----------------------------------------------------------------------*/

static inline void activate_irq(int irq)
{
#ifdef CONFIG_ARM
	/* ARM requires an extra step to clear IRQ_NOREQUEST, which it
	 * sets on behalf of every irq_chip.  Also sets IRQ_NOPROBE.
	 */
	set_irq_flags(irq, IRQF_VALID);
#else
	/* same effect on other architectures */
	irq_set_noprobe(irq);
#endif
}

static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
{
	if (on)
		atomic_inc(&twl6030_wakeirqs);
	else
		atomic_dec(&twl6030_wakeirqs);

	return 0;
}

int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
{
	int ret;
	u8 unmask_value;
	ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
			REG_INT_STS_A + offset);
	unmask_value &= (~(bit_mask));
	ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
			REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
	return ret;
}
EXPORT_SYMBOL(twl6030_interrupt_unmask);

int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
{
	int ret;
	u8 mask_value;
	ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
			REG_INT_STS_A + offset);
	mask_value |= (bit_mask);
	ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
			REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
	return ret;
}
EXPORT_SYMBOL(twl6030_interrupt_mask);

int twl6030_mmc_card_detect_config(void)
{
	int ret;
	u8 reg_val = 0;

	/* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
	twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
						REG_INT_MSK_LINE_B);
	twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
						REG_INT_MSK_STS_B);
	/*
	 * Initially Configuring MMC_CTRL for receiving interrupts &
	 * Card status on TWL6030 for MMC1
	 */
	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL);
	if (ret < 0) {
		pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
		return ret;
	}
	reg_val &= ~VMMC_AUTO_OFF;
	reg_val |= SW_FC;
	ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
	if (ret < 0) {
		pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
		return ret;
	}

	/* Configuring PullUp-PullDown register */
	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val,
						TWL6030_CFG_INPUT_PUPD3);
	if (ret < 0) {
		pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
									ret);
		return ret;
	}
	reg_val &= ~(MMC_PU | MMC_PD);
	ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
						TWL6030_CFG_INPUT_PUPD3);
	if (ret < 0) {
		pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
									ret);
		return ret;
	}

	return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
}
EXPORT_SYMBOL(twl6030_mmc_card_detect_config);

int twl6030_mmc_card_detect(struct device *dev, int slot)
{
	int ret = -EIO;
	u8 read_reg = 0;
	struct platform_device *pdev = to_platform_device(dev);

	if (pdev->id) {
		/* TWL6030 provide's Card detect support for
		 * only MMC1 controller.
		 */
		pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
		return ret;
	}
	/*
	 * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
	 * 0 - Card not present ,1 - Card present
	 */
	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
						TWL6030_MMCCTRL);
	if (ret >= 0)
		ret = read_reg & STS_MMC;
	return ret;
}
EXPORT_SYMBOL(twl6030_mmc_card_detect);

int twl6030_init_irq(struct device *dev, int irq_num)
{
	struct			device_node *node = dev->of_node;
	int			nr_irqs, irq_base, irq_end;
	static struct irq_chip  twl6030_irq_chip;
	int			status;
	int			i;
	u8			mask[3];

	nr_irqs = TWL6030_NR_IRQS;

	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
	if (IS_ERR_VALUE(irq_base)) {
		dev_err(dev, "Fail to allocate IRQ descs\n");
		return irq_base;
	}

	irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
			      &irq_domain_simple_ops, NULL);

	irq_end = irq_base + nr_irqs;

	mask[0] = 0xFF;
	mask[1] = 0xFF;
	mask[2] = 0xFF;

	/* mask all int lines */
	status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
	/* mask all int sts */
	status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
	/* clear INT_STS_A,B,C */
	status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);

	if (status < 0) {
		dev_err(dev, "I2C err writing TWL_MODULE_PIH: %d\n", status);
		return status;
	}

	twl6030_irq_base = irq_base;

	/*
	 * install an irq handler for each of the modules;
	 * clone dummy irq_chip since PIH can't *do* anything
	 */
	twl6030_irq_chip = dummy_irq_chip;
	twl6030_irq_chip.name = "twl6030";
	twl6030_irq_chip.irq_set_type = NULL;
	twl6030_irq_chip.irq_set_wake = twl6030_irq_set_wake;

	for (i = irq_base; i < irq_end; i++) {
		irq_set_chip_and_handler(i, &twl6030_irq_chip,
					 handle_simple_irq);
		irq_set_chip_data(i, (void *)irq_num);
		irq_set_nested_thread(i, true);
		irq_set_parent(i, irq_num);
		activate_irq(i);
	}

	dev_info(dev, "PIH (irq %d) nested IRQs %d..%d\n",
		 irq_num, irq_base, irq_end);

	/* install an irq handler to demultiplex the TWL6030 interrupt */
	status = request_threaded_irq(irq_num, NULL, twl6030_irq_thread,
				      IRQF_ONESHOT, "TWL6030-PIH", NULL);
	if (status < 0) {
		dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
		goto fail_irq;
	}

	twl_irq = irq_num;
	register_pm_notifier(&twl6030_irq_pm_notifier_block);
	return irq_base;

fail_irq:
	for (i = irq_base; i < irq_end; i++)
		irq_set_chip_and_handler(i, NULL, NULL);

	return status;
}

int twl6030_exit_irq(void)
{

	if (twl_irq) {
		unregister_pm_notifier(&twl6030_irq_pm_notifier_block);
		free_irq(twl_irq, NULL);
	}

	return 0;
}
Commit	Line	Data
e8deb28c B	1	/*
	2	* twl6030-irq.c - TWL6030 irq support
	3	*
	4	* Copyright (C) 2005-2009 Texas Instruments, Inc.
	5	*
	6	* Modifications to defer interrupt handling to a kernel thread:
	7	* Copyright (C) 2006 MontaVista Software, Inc.
	8	*
	9	* Based on tlv320aic23.c:
	10	* Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
	11	*
	12	* Code cleanup and modifications to IRQ handler.
	13	* by syed khasim <x0khasim@ti.com>
	14	*
	15	* TWL6030 specific code and IRQ handling changes by
	16	* Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
	17	* Balaji T K <balajitk@ti.com>
	18	*
	19	* This program is free software; you can redistribute it and/or modify
	20	* it under the terms of the GNU General Public License as published by
	21	* the Free Software Foundation; either version 2 of the License, or
	22	* (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	32	*/
	33
	34	#include <linux/init.h>
5d4a357d	35	#include <linux/export.h>
e8deb28c B	36	#include <linux/interrupt.h>
	37	#include <linux/irq.h>
	38	#include <linux/kthread.h>
	39	#include <linux/i2c/twl.h>
72f2e2c7	40	#include <linux/platform_device.h>
ab2b9260	41	#include <linux/suspend.h>
78518ffa BC	42	#include <linux/of.h>
78518ffa BC	43	#include <linux/irqdomain.h>
e8deb28c	44
b0b4a7c2 MK	45	#include "twl-core.h"
b0b4a7c2 MK	46
e8deb28c B	47	/*
	48	* TWL6030 (unlike its predecessors, which had two level interrupt handling)
	49	* three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
	50	* It exposes status bits saying who has raised an interrupt. There are
	51	* three mask registers that corresponds to these status registers, that
	52	* enables/disables these interrupts.
	53	*
	54	* We set up IRQs starting at a platform-specified base. An interrupt map table,
	55	* specifies mapping between interrupt number and the associated module.
e8deb28c	56	*/
78518ffa	57	#define TWL6030_NR_IRQS 20
e8deb28c B	58
	59	static int twl6030_interrupt_mapping[24] = {
	60	PWR_INTR_OFFSET, /* Bit 0 PWRON */
	61	PWR_INTR_OFFSET, /* Bit 1 RPWRON */
	62	PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
	63	RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
	64	RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
	65	HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
	66	SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
	67	SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
	68
	69	SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
	70	BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
	71	SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
	72	MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
	73	RSV_INTR_OFFSET, /* Bit 12 Reserved */
	74	MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
	75	MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
	76	GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
	77
	78	USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
	79	USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
	80	USBOTG_INTR_OFFSET, /* Bit 18 ID */
77b1d3fa	81	USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
e8deb28c	82	CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
6523b148 GG	83	CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
6523b148 GG	84	CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
e8deb28c B	85	RSV_INTR_OFFSET, /* Bit 23 Reserved */
	86	};
	87	/----------------------------------------------------------------------/
	88
	89	static unsigned twl6030_irq_base;
ab2b9260 TP	90	static int twl_irq;
ab2b9260 TP	91	static bool twl_irq_wake_enabled;
e8deb28c	92
ab2b9260 TP	93	static atomic_t twl6030_wakeirqs = ATOMIC_INIT(0);
	94
	95	static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
	96	unsigned long pm_event, void *unused)
	97	{
	98	int chained_wakeups;
	99
	100	switch (pm_event) {
	101	case PM_SUSPEND_PREPARE:
	102	chained_wakeups = atomic_read(&twl6030_wakeirqs);
	103
	104	if (chained_wakeups && !twl_irq_wake_enabled) {
	105	if (enable_irq_wake(twl_irq))
	106	pr_err("twl6030 IRQ wake enable failed\n");
	107	else
	108	twl_irq_wake_enabled = true;
	109	} else if (!chained_wakeups && twl_irq_wake_enabled) {
	110	disable_irq_wake(twl_irq);
	111	twl_irq_wake_enabled = false;
	112	}
	113
782baa20	114	disable_irq(twl_irq);
ab2b9260	115	break;
782baa20 TP	116
	117	case PM_POST_SUSPEND:
	118	enable_irq(twl_irq);
	119	break;
	120
ab2b9260 TP	121	default:
	122	break;
	123	}
	124
	125	return NOTIFY_DONE;
	126	}
	127
	128	static struct notifier_block twl6030_irq_pm_notifier_block = {
	129	.notifier_call = twl6030_irq_pm_notifier,
	130	};
e8deb28c B	131
e8deb28c B	132	/*
87343e53 NVS	133	* Threaded irq handler for the twl6030 interrupt.
	134	* We query the interrupt controller in the twl6030 to determine
	135	* which module is generating the interrupt request and call
	136	* handle_nested_irq for that module.
	137	*/
	138	static irqreturn_t twl6030_irq_thread(int irq, void *data)
e8deb28c	139	{
87343e53 NVS	140	int i, ret;
87343e53 NVS	141	union {
e8deb28c B	142	u8 bytes[4];
e8deb28c B	143	u32 int_sts;
87343e53	144	} sts;
e8deb28c	145
87343e53 NVS	146	/* read INT_STS_A, B and C in one shot using a burst read */
	147	ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, REG_INT_STS_A, 3);
	148	if (ret) {
	149	pr_warn("twl6030_irq: I2C error %d reading PIH ISR\n", ret);
	150	return IRQ_HANDLED;
	151	}
e8deb28c	152
87343e53	153	sts.bytes[3] = 0; /* Only 24 bits are valid*/
e8deb28c	154
87343e53 NVS	155	/*
	156	* Since VBUS status bit is not reliable for VBUS disconnect
	157	* use CHARGER VBUS detection status bit instead.
	158	*/
	159	if (sts.bytes[2] & 0x10)
	160	sts.bytes[2] \|= 0x08;
77b1d3fa	161
87343e53 NVS	162	for (i = 0; sts.int_sts; sts.int_sts >>= 1, i++)
	163	if (sts.int_sts & 0x1) {
	164	int module_irq = twl6030_irq_base +
e8deb28c	165	twl6030_interrupt_mapping[i];
87343e53 NVS	166	handle_nested_irq(module_irq);
	167	pr_debug("twl6030_irq: PIH ISR %u, virq%u\n",
	168	i, module_irq);
e8deb28c	169	}
3f8349e6	170
87343e53 NVS	171	/*
	172	* NOTE:
	173	* Simulation confirms that documentation is wrong w.r.t the
	174	* interrupt status clear operation. A single byte write to
	175	* any one of STS_A to STS_C register results in all three
	176	* STS registers being reset. Since it does not matter which
	177	* value is written, all three registers are cleared on a
	178	* single byte write, so we just use 0x0 to clear.
	179	*/
	180	ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
	181	if (ret)
	182	pr_warn("twl6030_irq: I2C error in clearing PIH ISR\n");
e8deb28c	183
e8deb28c B	184	return IRQ_HANDLED;
	185	}
	186
	187	/----------------------------------------------------------------------/
	188
	189	static inline void activate_irq(int irq)
	190	{
	191	#ifdef CONFIG_ARM
	192	/* ARM requires an extra step to clear IRQ_NOREQUEST, which it
	193	* sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
	194	*/
	195	set_irq_flags(irq, IRQF_VALID);
	196	#else
	197	/* same effect on other architectures */
d5bb1221	198	irq_set_noprobe(irq);
e8deb28c B	199	#endif
	200	}
	201
b8b8d793	202	static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
49dcd070	203	{
ab2b9260 TP	204	if (on)
	205	atomic_inc(&twl6030_wakeirqs);
	206	else
	207	atomic_dec(&twl6030_wakeirqs);
49dcd070	208
ab2b9260	209	return 0;
49dcd070 SS	210	}
49dcd070 SS	211
e8deb28c B	212	int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
	213	{
	214	int ret;
	215	u8 unmask_value;
	216	ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
	217	REG_INT_STS_A + offset);
	218	unmask_value &= (~(bit_mask));
	219	ret \|= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
	220	REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
	221	return ret;
	222	}
	223	EXPORT_SYMBOL(twl6030_interrupt_unmask);
	224
	225	int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
	226	{
	227	int ret;
	228	u8 mask_value;
	229	ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
	230	REG_INT_STS_A + offset);
	231	mask_value \|= (bit_mask);
	232	ret \|= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
	233	REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
	234	return ret;
	235	}
	236	EXPORT_SYMBOL(twl6030_interrupt_mask);
	237
72f2e2c7	238	int twl6030_mmc_card_detect_config(void)
	239	{
	240	int ret;
	241	u8 reg_val = 0;
	242
	243	/* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
	244	twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
	245	REG_INT_MSK_LINE_B);
	246	twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
	247	REG_INT_MSK_STS_B);
	248	/*
25985edc	249	* Initially Configuring MMC_CTRL for receiving interrupts &
72f2e2c7	250	* Card status on TWL6030 for MMC1
	251	*/
	252	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL);
	253	if (ret < 0) {
	254	pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
	255	return ret;
	256	}
	257	reg_val &= ~VMMC_AUTO_OFF;
	258	reg_val \|= SW_FC;
	259	ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
	260	if (ret < 0) {
	261	pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
	262	return ret;
	263	}
	264
	265	/* Configuring PullUp-PullDown register */
	266	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val,
	267	TWL6030_CFG_INPUT_PUPD3);
	268	if (ret < 0) {
	269	pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
	270	ret);
	271	return ret;
	272	}
	273	reg_val &= ~(MMC_PU \| MMC_PD);
	274	ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
	275	TWL6030_CFG_INPUT_PUPD3);
	276	if (ret < 0) {
	277	pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
	278	ret);
	279	return ret;
	280	}
bdd61bc6 BC	281
bdd61bc6 BC	282	return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
72f2e2c7	283	}
	284	EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
	285
	286	int twl6030_mmc_card_detect(struct device *dev, int slot)
	287	{
	288	int ret = -EIO;
	289	u8 read_reg = 0;
	290	struct platform_device *pdev = to_platform_device(dev);
	291
	292	if (pdev->id) {
	293	/* TWL6030 provide's Card detect support for
	294	* only MMC1 controller.
	295	*/
25985edc	296	pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
72f2e2c7	297	return ret;
	298	}
	299	/*
	300	* BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
	301	* 0 - Card not present ,1 - Card present
	302	*/
	303	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
	304	TWL6030_MMCCTRL);
	305	if (ret >= 0)
	306	ret = read_reg & STS_MMC;
	307	return ret;
	308	}
	309	EXPORT_SYMBOL(twl6030_mmc_card_detect);
	310
78518ffa	311	int twl6030_init_irq(struct device *dev, int irq_num)
e8deb28c	312	{
78518ffa BC	313	struct device_node *node = dev->of_node;
78518ffa BC	314	int nr_irqs, irq_base, irq_end;
ec1a07b3	315	static struct irq_chip twl6030_irq_chip;
a820e568	316	int status;
ec1a07b3	317	int i;
14591d88	318	u8 mask[3];
78518ffa BC	319
	320	nr_irqs = TWL6030_NR_IRQS;
	321
	322	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
	323	if (IS_ERR_VALUE(irq_base)) {
	324	dev_err(dev, "Fail to allocate IRQ descs\n");
	325	return irq_base;
	326	}
	327
	328	irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
	329	&irq_domain_simple_ops, NULL);
	330
	331	irq_end = irq_base + nr_irqs;
	332
14591d88	333	mask[0] = 0xFF;
e8deb28c B	334	mask[1] = 0xFF;
e8deb28c B	335	mask[2] = 0xFF;
ec1a07b3 BC	336
ec1a07b3 BC	337	/* mask all int lines */
a820e568	338	status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
ec1a07b3	339	/* mask all int sts */
a820e568	340	status \|= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
ec1a07b3	341	/* clear INT_STS_A,B,C */
a820e568 GS	342	status \|= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
	343
	344	if (status < 0) {
	345	dev_err(dev, "I2C err writing TWL_MODULE_PIH: %d\n", status);
	346	return status;
	347	}
e8deb28c B	348
	349	twl6030_irq_base = irq_base;
	350
ec1a07b3 BC	351	/*
ec1a07b3 BC	352	* install an irq handler for each of the modules;
e8deb28c B	353	* clone dummy irq_chip since PIH can't do anything
	354	*/
	355	twl6030_irq_chip = dummy_irq_chip;
	356	twl6030_irq_chip.name = "twl6030";
c45c685c	357	twl6030_irq_chip.irq_set_type = NULL;
49dcd070	358	twl6030_irq_chip.irq_set_wake = twl6030_irq_set_wake;
e8deb28c B	359
e8deb28c B	360	for (i = irq_base; i < irq_end; i++) {
d5bb1221 TG	361	irq_set_chip_and_handler(i, &twl6030_irq_chip,
d5bb1221 TG	362	handle_simple_irq);
49dcd070	363	irq_set_chip_data(i, (void *)irq_num);
87343e53 NVS	364	irq_set_nested_thread(i, true);
87343e53 NVS	365	irq_set_parent(i, irq_num);
e8deb28c B	366	activate_irq(i);
	367	}
	368
87343e53 NVS	369	dev_info(dev, "PIH (irq %d) nested IRQs %d..%d\n",
87343e53 NVS	370	irq_num, irq_base, irq_end);
e8deb28c B	371
e8deb28c B	372	/* install an irq handler to demultiplex the TWL6030 interrupt */
87343e53 NVS	373	status = request_threaded_irq(irq_num, NULL, twl6030_irq_thread,
87343e53 NVS	374	IRQF_ONESHOT, "TWL6030-PIH", NULL);
e8deb28c	375	if (status < 0) {
ec1a07b3	376	dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
e8deb28c B	377	goto fail_irq;
e8deb28c B	378	}
862de70c	379
ab2b9260 TP	380	twl_irq = irq_num;
ab2b9260 TP	381	register_pm_notifier(&twl6030_irq_pm_notifier_block);
78518ffa	382	return irq_base;
e8deb28c	383
862de70c	384	fail_irq:
e8deb28c	385	for (i = irq_base; i < irq_end; i++)
d5bb1221	386	irq_set_chip_and_handler(i, NULL, NULL);
ec1a07b3	387
e8deb28c B	388	return status;
	389	}
	390
	391	int twl6030_exit_irq(void)
	392	{
	393
87343e53 NVS	394	if (twl_irq) {
	395	unregister_pm_notifier(&twl6030_irq_pm_notifier_block);
	396	free_irq(twl_irq, NULL);
e8deb28c	397	}
87343e53	398
e8deb28c B	399	return 0;
	400	}
	401