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05c45ca9 RK |
1 | /* |
2 | * linux/drivers/mfd/ucb1x00-core.c | |
3 | * | |
4 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | * | |
10 | * The UCB1x00 core driver provides basic services for handling IO, | |
11 | * the ADC, interrupts, and accessing registers. It is designed | |
12 | * such that everything goes through this layer, thereby providing | |
13 | * a consistent locking methodology, as well as allowing the drivers | |
14 | * to be used on other non-MCP-enabled hardware platforms. | |
15 | * | |
16 | * Note that all locks are private to this file. Nothing else may | |
17 | * touch them. | |
18 | */ | |
05c45ca9 RK |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
d43c36dc | 21 | #include <linux/sched.h> |
05c45ca9 RK |
22 | #include <linux/slab.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/device.h> | |
a621aaed | 27 | #include <linux/mutex.h> |
c8602edf | 28 | #include <linux/mfd/ucb1x00.h> |
9ca3dc80 | 29 | #include <linux/gpio.h> |
2c08583c | 30 | #include <linux/semaphore.h> |
05c45ca9 | 31 | |
dcea83ad | 32 | #include <mach/dma.h> |
a09e64fb | 33 | #include <mach/hardware.h> |
05c45ca9 | 34 | |
a621aaed | 35 | static DEFINE_MUTEX(ucb1x00_mutex); |
05c45ca9 RK |
36 | static LIST_HEAD(ucb1x00_drivers); |
37 | static LIST_HEAD(ucb1x00_devices); | |
38 | ||
5dd7bf59 JF |
39 | static struct mcp_device_id ucb1x00_id[] = { |
40 | { "ucb1x00", 0 }, /* auto-detection */ | |
41 | { "ucb1200", UCB_ID_1200 }, | |
42 | { "ucb1300", UCB_ID_1300 }, | |
43 | { "tc35143", UCB_ID_TC35143 }, | |
44 | { } | |
45 | }; | |
46 | MODULE_DEVICE_TABLE(mcp, ucb1x00_id); | |
47 | ||
05c45ca9 RK |
48 | /** |
49 | * ucb1x00_io_set_dir - set IO direction | |
50 | * @ucb: UCB1x00 structure describing chip | |
51 | * @in: bitfield of IO pins to be set as inputs | |
52 | * @out: bitfield of IO pins to be set as outputs | |
53 | * | |
54 | * Set the IO direction of the ten general purpose IO pins on | |
55 | * the UCB1x00 chip. The @in bitfield has priority over the | |
56 | * @out bitfield, in that if you specify a pin as both input | |
57 | * and output, it will end up as an input. | |
58 | * | |
59 | * ucb1x00_enable must have been called to enable the comms | |
60 | * before using this function. | |
61 | * | |
62 | * This function takes a spinlock, disabling interrupts. | |
63 | */ | |
64 | void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out) | |
65 | { | |
66 | unsigned long flags; | |
67 | ||
68 | spin_lock_irqsave(&ucb->io_lock, flags); | |
69 | ucb->io_dir |= out; | |
70 | ucb->io_dir &= ~in; | |
71 | ||
72 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
73 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
74 | } | |
75 | ||
76 | /** | |
77 | * ucb1x00_io_write - set or clear IO outputs | |
78 | * @ucb: UCB1x00 structure describing chip | |
79 | * @set: bitfield of IO pins to set to logic '1' | |
80 | * @clear: bitfield of IO pins to set to logic '0' | |
81 | * | |
82 | * Set the IO output state of the specified IO pins. The value | |
83 | * is retained if the pins are subsequently configured as inputs. | |
84 | * The @clear bitfield has priority over the @set bitfield - | |
85 | * outputs will be cleared. | |
86 | * | |
87 | * ucb1x00_enable must have been called to enable the comms | |
88 | * before using this function. | |
89 | * | |
90 | * This function takes a spinlock, disabling interrupts. | |
91 | */ | |
92 | void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear) | |
93 | { | |
94 | unsigned long flags; | |
95 | ||
96 | spin_lock_irqsave(&ucb->io_lock, flags); | |
97 | ucb->io_out |= set; | |
98 | ucb->io_out &= ~clear; | |
99 | ||
100 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
101 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
102 | } | |
103 | ||
104 | /** | |
105 | * ucb1x00_io_read - read the current state of the IO pins | |
106 | * @ucb: UCB1x00 structure describing chip | |
107 | * | |
108 | * Return a bitfield describing the logic state of the ten | |
109 | * general purpose IO pins. | |
110 | * | |
111 | * ucb1x00_enable must have been called to enable the comms | |
112 | * before using this function. | |
113 | * | |
114 | * This function does not take any semaphores or spinlocks. | |
115 | */ | |
116 | unsigned int ucb1x00_io_read(struct ucb1x00 *ucb) | |
117 | { | |
118 | return ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
119 | } | |
120 | ||
9ca3dc80 TK |
121 | static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
122 | { | |
123 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
124 | unsigned long flags; | |
125 | ||
126 | spin_lock_irqsave(&ucb->io_lock, flags); | |
127 | if (value) | |
128 | ucb->io_out |= 1 << offset; | |
129 | else | |
130 | ucb->io_out &= ~(1 << offset); | |
131 | ||
132 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
133 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
134 | } | |
135 | ||
136 | static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset) | |
137 | { | |
138 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
139 | return ucb1x00_reg_read(ucb, UCB_IO_DATA) & (1 << offset); | |
140 | } | |
141 | ||
142 | static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
143 | { | |
144 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
145 | unsigned long flags; | |
146 | ||
147 | spin_lock_irqsave(&ucb->io_lock, flags); | |
148 | ucb->io_dir &= ~(1 << offset); | |
149 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
150 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
151 | ||
152 | return 0; | |
153 | } | |
154 | ||
155 | static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset | |
156 | , int value) | |
157 | { | |
158 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
159 | unsigned long flags; | |
160 | ||
161 | spin_lock_irqsave(&ucb->io_lock, flags); | |
162 | ucb->io_dir |= (1 << offset); | |
163 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
164 | ||
165 | if (value) | |
166 | ucb->io_out |= 1 << offset; | |
167 | else | |
168 | ucb->io_out &= ~(1 << offset); | |
169 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
170 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
05c45ca9 RK |
175 | /* |
176 | * UCB1300 data sheet says we must: | |
177 | * 1. enable ADC => 5us (including reference startup time) | |
178 | * 2. select input => 51*tsibclk => 4.3us | |
179 | * 3. start conversion => 102*tsibclk => 8.5us | |
180 | * (tsibclk = 1/11981000) | |
181 | * Period between SIB 128-bit frames = 10.7us | |
182 | */ | |
183 | ||
184 | /** | |
185 | * ucb1x00_adc_enable - enable the ADC converter | |
186 | * @ucb: UCB1x00 structure describing chip | |
187 | * | |
188 | * Enable the ucb1x00 and ADC converter on the UCB1x00 for use. | |
189 | * Any code wishing to use the ADC converter must call this | |
190 | * function prior to using it. | |
191 | * | |
192 | * This function takes the ADC semaphore to prevent two or more | |
193 | * concurrent uses, and therefore may sleep. As a result, it | |
194 | * can only be called from process context, not interrupt | |
195 | * context. | |
196 | * | |
197 | * You should release the ADC as soon as possible using | |
198 | * ucb1x00_adc_disable. | |
199 | */ | |
200 | void ucb1x00_adc_enable(struct ucb1x00 *ucb) | |
201 | { | |
202 | down(&ucb->adc_sem); | |
203 | ||
204 | ucb->adc_cr |= UCB_ADC_ENA; | |
205 | ||
206 | ucb1x00_enable(ucb); | |
207 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
208 | } | |
209 | ||
210 | /** | |
211 | * ucb1x00_adc_read - read the specified ADC channel | |
212 | * @ucb: UCB1x00 structure describing chip | |
213 | * @adc_channel: ADC channel mask | |
214 | * @sync: wait for syncronisation pulse. | |
215 | * | |
216 | * Start an ADC conversion and wait for the result. Note that | |
217 | * synchronised ADC conversions (via the ADCSYNC pin) must wait | |
218 | * until the trigger is asserted and the conversion is finished. | |
219 | * | |
220 | * This function currently spins waiting for the conversion to | |
221 | * complete (2 frames max without sync). | |
222 | * | |
223 | * If called for a synchronised ADC conversion, it may sleep | |
224 | * with the ADC semaphore held. | |
225 | */ | |
226 | unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync) | |
227 | { | |
228 | unsigned int val; | |
229 | ||
230 | if (sync) | |
231 | adc_channel |= UCB_ADC_SYNC_ENA; | |
232 | ||
233 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel); | |
234 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START); | |
235 | ||
236 | for (;;) { | |
237 | val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); | |
238 | if (val & UCB_ADC_DAT_VAL) | |
239 | break; | |
240 | /* yield to other processes */ | |
241 | set_current_state(TASK_INTERRUPTIBLE); | |
242 | schedule_timeout(1); | |
243 | } | |
244 | ||
245 | return UCB_ADC_DAT(val); | |
246 | } | |
247 | ||
248 | /** | |
249 | * ucb1x00_adc_disable - disable the ADC converter | |
250 | * @ucb: UCB1x00 structure describing chip | |
251 | * | |
252 | * Disable the ADC converter and release the ADC semaphore. | |
253 | */ | |
254 | void ucb1x00_adc_disable(struct ucb1x00 *ucb) | |
255 | { | |
256 | ucb->adc_cr &= ~UCB_ADC_ENA; | |
257 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
258 | ucb1x00_disable(ucb); | |
259 | ||
260 | up(&ucb->adc_sem); | |
261 | } | |
262 | ||
263 | /* | |
264 | * UCB1x00 Interrupt handling. | |
265 | * | |
266 | * The UCB1x00 can generate interrupts when the SIBCLK is stopped. | |
267 | * Since we need to read an internal register, we must re-enable | |
268 | * SIBCLK to talk to the chip. We leave the clock running until | |
269 | * we have finished processing all interrupts from the chip. | |
270 | */ | |
7d12e780 | 271 | static irqreturn_t ucb1x00_irq(int irqnr, void *devid) |
05c45ca9 RK |
272 | { |
273 | struct ucb1x00 *ucb = devid; | |
274 | struct ucb1x00_irq *irq; | |
275 | unsigned int isr, i; | |
276 | ||
277 | ucb1x00_enable(ucb); | |
278 | isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS); | |
279 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr); | |
280 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
281 | ||
282 | for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++) | |
283 | if (isr & 1 && irq->fn) | |
284 | irq->fn(i, irq->devid); | |
285 | ucb1x00_disable(ucb); | |
286 | ||
287 | return IRQ_HANDLED; | |
288 | } | |
289 | ||
290 | /** | |
291 | * ucb1x00_hook_irq - hook a UCB1x00 interrupt | |
292 | * @ucb: UCB1x00 structure describing chip | |
293 | * @idx: interrupt index | |
294 | * @fn: function to call when interrupt is triggered | |
295 | * @devid: device id to pass to interrupt handler | |
296 | * | |
297 | * Hook the specified interrupt. You can only register one handler | |
298 | * for each interrupt source. The interrupt source is not enabled | |
299 | * by this function; use ucb1x00_enable_irq instead. | |
300 | * | |
301 | * Interrupt handlers will be called with other interrupts enabled. | |
302 | * | |
303 | * Returns zero on success, or one of the following errors: | |
304 | * -EINVAL if the interrupt index is invalid | |
305 | * -EBUSY if the interrupt has already been hooked | |
306 | */ | |
307 | int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid) | |
308 | { | |
309 | struct ucb1x00_irq *irq; | |
310 | int ret = -EINVAL; | |
311 | ||
312 | if (idx < 16) { | |
313 | irq = ucb->irq_handler + idx; | |
314 | ret = -EBUSY; | |
315 | ||
316 | spin_lock_irq(&ucb->lock); | |
317 | if (irq->fn == NULL) { | |
318 | irq->devid = devid; | |
319 | irq->fn = fn; | |
320 | ret = 0; | |
321 | } | |
322 | spin_unlock_irq(&ucb->lock); | |
323 | } | |
324 | return ret; | |
325 | } | |
326 | ||
327 | /** | |
328 | * ucb1x00_enable_irq - enable an UCB1x00 interrupt source | |
329 | * @ucb: UCB1x00 structure describing chip | |
330 | * @idx: interrupt index | |
331 | * @edges: interrupt edges to enable | |
332 | * | |
333 | * Enable the specified interrupt to trigger on %UCB_RISING, | |
334 | * %UCB_FALLING or both edges. The interrupt should have been | |
335 | * hooked by ucb1x00_hook_irq. | |
336 | */ | |
337 | void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
338 | { | |
339 | unsigned long flags; | |
340 | ||
341 | if (idx < 16) { | |
342 | spin_lock_irqsave(&ucb->lock, flags); | |
343 | ||
344 | ucb1x00_enable(ucb); | |
345 | if (edges & UCB_RISING) { | |
346 | ucb->irq_ris_enbl |= 1 << idx; | |
347 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
348 | } | |
349 | if (edges & UCB_FALLING) { | |
350 | ucb->irq_fal_enbl |= 1 << idx; | |
351 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
352 | } | |
353 | ucb1x00_disable(ucb); | |
354 | spin_unlock_irqrestore(&ucb->lock, flags); | |
355 | } | |
356 | } | |
357 | ||
358 | /** | |
359 | * ucb1x00_disable_irq - disable an UCB1x00 interrupt source | |
360 | * @ucb: UCB1x00 structure describing chip | |
361 | * @edges: interrupt edges to disable | |
362 | * | |
363 | * Disable the specified interrupt triggering on the specified | |
364 | * (%UCB_RISING, %UCB_FALLING or both) edges. | |
365 | */ | |
366 | void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
367 | { | |
368 | unsigned long flags; | |
369 | ||
370 | if (idx < 16) { | |
371 | spin_lock_irqsave(&ucb->lock, flags); | |
372 | ||
373 | ucb1x00_enable(ucb); | |
374 | if (edges & UCB_RISING) { | |
375 | ucb->irq_ris_enbl &= ~(1 << idx); | |
376 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
377 | } | |
378 | if (edges & UCB_FALLING) { | |
379 | ucb->irq_fal_enbl &= ~(1 << idx); | |
380 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
381 | } | |
382 | ucb1x00_disable(ucb); | |
383 | spin_unlock_irqrestore(&ucb->lock, flags); | |
384 | } | |
385 | } | |
386 | ||
387 | /** | |
388 | * ucb1x00_free_irq - disable and free the specified UCB1x00 interrupt | |
389 | * @ucb: UCB1x00 structure describing chip | |
390 | * @idx: interrupt index | |
391 | * @devid: device id. | |
392 | * | |
393 | * Disable the interrupt source and remove the handler. devid must | |
394 | * match the devid passed when hooking the interrupt. | |
395 | * | |
396 | * Returns zero on success, or one of the following errors: | |
397 | * -EINVAL if the interrupt index is invalid | |
398 | * -ENOENT if devid does not match | |
399 | */ | |
400 | int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid) | |
401 | { | |
402 | struct ucb1x00_irq *irq; | |
403 | int ret; | |
404 | ||
405 | if (idx >= 16) | |
406 | goto bad; | |
407 | ||
408 | irq = ucb->irq_handler + idx; | |
409 | ret = -ENOENT; | |
410 | ||
411 | spin_lock_irq(&ucb->lock); | |
412 | if (irq->devid == devid) { | |
413 | ucb->irq_ris_enbl &= ~(1 << idx); | |
414 | ucb->irq_fal_enbl &= ~(1 << idx); | |
415 | ||
416 | ucb1x00_enable(ucb); | |
417 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
418 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
419 | ucb1x00_disable(ucb); | |
420 | ||
421 | irq->fn = NULL; | |
422 | irq->devid = NULL; | |
423 | ret = 0; | |
424 | } | |
425 | spin_unlock_irq(&ucb->lock); | |
426 | return ret; | |
427 | ||
428 | bad: | |
429 | printk(KERN_ERR "Freeing bad UCB1x00 irq %d\n", idx); | |
430 | return -EINVAL; | |
431 | } | |
432 | ||
433 | static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv) | |
434 | { | |
435 | struct ucb1x00_dev *dev; | |
436 | int ret = -ENOMEM; | |
437 | ||
438 | dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL); | |
439 | if (dev) { | |
440 | dev->ucb = ucb; | |
441 | dev->drv = drv; | |
442 | ||
443 | ret = drv->add(dev); | |
444 | ||
445 | if (ret == 0) { | |
446 | list_add(&dev->dev_node, &ucb->devs); | |
447 | list_add(&dev->drv_node, &drv->devs); | |
448 | } else { | |
449 | kfree(dev); | |
450 | } | |
451 | } | |
452 | return ret; | |
453 | } | |
454 | ||
455 | static void ucb1x00_remove_dev(struct ucb1x00_dev *dev) | |
456 | { | |
457 | dev->drv->remove(dev); | |
458 | list_del(&dev->dev_node); | |
459 | list_del(&dev->drv_node); | |
460 | kfree(dev); | |
461 | } | |
462 | ||
463 | /* | |
464 | * Try to probe our interrupt, rather than relying on lots of | |
465 | * hard-coded machine dependencies. For reference, the expected | |
466 | * IRQ mappings are: | |
467 | * | |
468 | * Machine Default IRQ | |
469 | * adsbitsy IRQ_GPCIN4 | |
470 | * cerf IRQ_GPIO_UCB1200_IRQ | |
471 | * flexanet IRQ_GPIO_GUI | |
472 | * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ | |
473 | * graphicsclient ADS_EXT_IRQ(8) | |
474 | * graphicsmaster ADS_EXT_IRQ(8) | |
475 | * lart LART_IRQ_UCB1200 | |
476 | * omnimeter IRQ_GPIO23 | |
477 | * pfs168 IRQ_GPIO_UCB1300_IRQ | |
478 | * simpad IRQ_GPIO_UCB1300_IRQ | |
479 | * shannon SHANNON_IRQ_GPIO_IRQ_CODEC | |
480 | * yopy IRQ_GPIO_UCB1200_IRQ | |
481 | */ | |
482 | static int ucb1x00_detect_irq(struct ucb1x00 *ucb) | |
483 | { | |
484 | unsigned long mask; | |
485 | ||
486 | mask = probe_irq_on(); | |
cfc73656 IM |
487 | if (!mask) { |
488 | probe_irq_off(mask); | |
05c45ca9 | 489 | return NO_IRQ; |
cfc73656 | 490 | } |
05c45ca9 RK |
491 | |
492 | /* | |
493 | * Enable the ADC interrupt. | |
494 | */ | |
495 | ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); | |
496 | ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); | |
497 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
498 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
499 | ||
500 | /* | |
501 | * Cause an ADC interrupt. | |
502 | */ | |
503 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); | |
504 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); | |
505 | ||
506 | /* | |
507 | * Wait for the conversion to complete. | |
508 | */ | |
509 | while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0); | |
510 | ucb1x00_reg_write(ucb, UCB_ADC_CR, 0); | |
511 | ||
512 | /* | |
513 | * Disable and clear interrupt. | |
514 | */ | |
515 | ucb1x00_reg_write(ucb, UCB_IE_RIS, 0); | |
516 | ucb1x00_reg_write(ucb, UCB_IE_FAL, 0); | |
517 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
518 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
519 | ||
520 | /* | |
521 | * Read triggered interrupt. | |
522 | */ | |
523 | return probe_irq_off(mask); | |
524 | } | |
525 | ||
0c55445f | 526 | static void ucb1x00_release(struct device *dev) |
585f5457 NP |
527 | { |
528 | struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); | |
529 | kfree(ucb); | |
530 | } | |
531 | ||
532 | static struct class ucb1x00_class = { | |
533 | .name = "ucb1x00", | |
0c55445f | 534 | .dev_release = ucb1x00_release, |
585f5457 NP |
535 | }; |
536 | ||
05c45ca9 RK |
537 | static int ucb1x00_probe(struct mcp *mcp) |
538 | { | |
5dd7bf59 | 539 | const struct mcp_device_id *mid; |
05c45ca9 RK |
540 | struct ucb1x00 *ucb; |
541 | struct ucb1x00_driver *drv; | |
5dd7bf59 | 542 | struct ucb1x00_plat_data *pdata; |
05c45ca9 RK |
543 | unsigned int id; |
544 | int ret = -ENODEV; | |
9ca3dc80 | 545 | int temp; |
05c45ca9 RK |
546 | |
547 | mcp_enable(mcp); | |
548 | id = mcp_reg_read(mcp, UCB_ID); | |
5dd7bf59 | 549 | mid = mcp_get_device_id(mcp); |
05c45ca9 | 550 | |
5dd7bf59 JF |
551 | if (mid && mid->driver_data) { |
552 | if (id != mid->driver_data) { | |
553 | printk(KERN_WARNING "%s wrong ID %04x found: %04x\n", | |
554 | mid->name, (unsigned int) mid->driver_data, id); | |
555 | goto err_disable; | |
556 | } | |
557 | } else { | |
558 | mid = &ucb1x00_id[1]; | |
559 | while (mid->driver_data) { | |
560 | if (id == mid->driver_data) | |
561 | break; | |
562 | mid++; | |
563 | } | |
564 | printk(KERN_WARNING "%s ID not found: %04x\n", | |
565 | ucb1x00_id[0].name, id); | |
05c45ca9 RK |
566 | goto err_disable; |
567 | } | |
568 | ||
dd00cc48 | 569 | ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL); |
05c45ca9 RK |
570 | ret = -ENOMEM; |
571 | if (!ucb) | |
572 | goto err_disable; | |
573 | ||
5dd7bf59 | 574 | pdata = mcp->attached_device.platform_data; |
0c55445f TJ |
575 | ucb->dev.class = &ucb1x00_class; |
576 | ucb->dev.parent = &mcp->attached_device; | |
5dd7bf59 | 577 | dev_set_name(&ucb->dev, mid->name); |
05c45ca9 RK |
578 | |
579 | spin_lock_init(&ucb->lock); | |
580 | spin_lock_init(&ucb->io_lock); | |
581 | sema_init(&ucb->adc_sem, 1); | |
582 | ||
5dd7bf59 | 583 | ucb->id = mid; |
05c45ca9 RK |
584 | ucb->mcp = mcp; |
585 | ucb->irq = ucb1x00_detect_irq(ucb); | |
586 | if (ucb->irq == NO_IRQ) { | |
5dd7bf59 | 587 | printk(KERN_ERR "%s: IRQ probe failed\n", mid->name); |
05c45ca9 RK |
588 | ret = -ENODEV; |
589 | goto err_free; | |
590 | } | |
591 | ||
9ca3dc80 | 592 | ucb->gpio.base = -1; |
5dd7bf59 | 593 | if (pdata && (pdata->gpio_base >= 0)) { |
9ca3dc80 | 594 | ucb->gpio.label = dev_name(&ucb->dev); |
5dd7bf59 | 595 | ucb->gpio.base = pdata->gpio_base; |
9ca3dc80 TK |
596 | ucb->gpio.ngpio = 10; |
597 | ucb->gpio.set = ucb1x00_gpio_set; | |
598 | ucb->gpio.get = ucb1x00_gpio_get; | |
599 | ucb->gpio.direction_input = ucb1x00_gpio_direction_input; | |
600 | ucb->gpio.direction_output = ucb1x00_gpio_direction_output; | |
601 | ret = gpiochip_add(&ucb->gpio); | |
602 | if (ret) | |
603 | goto err_free; | |
604 | } else | |
605 | dev_info(&ucb->dev, "gpio_base not set so no gpiolib support"); | |
606 | ||
dace1453 | 607 | ret = request_irq(ucb->irq, ucb1x00_irq, IRQF_TRIGGER_RISING, |
5dd7bf59 | 608 | mid->name, ucb); |
05c45ca9 | 609 | if (ret) { |
5dd7bf59 JF |
610 | printk(KERN_ERR "%s: unable to grab irq%d: %d\n", |
611 | mid->name, ucb->irq, ret); | |
9ca3dc80 | 612 | goto err_gpio; |
05c45ca9 RK |
613 | } |
614 | ||
05c45ca9 RK |
615 | mcp_set_drvdata(mcp, ucb); |
616 | ||
0c55445f | 617 | ret = device_register(&ucb->dev); |
05c45ca9 RK |
618 | if (ret) |
619 | goto err_irq; | |
620 | ||
9ca3dc80 | 621 | |
05c45ca9 | 622 | INIT_LIST_HEAD(&ucb->devs); |
a621aaed | 623 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
624 | list_add(&ucb->node, &ucb1x00_devices); |
625 | list_for_each_entry(drv, &ucb1x00_drivers, node) { | |
626 | ucb1x00_add_dev(ucb, drv); | |
627 | } | |
a621aaed | 628 | mutex_unlock(&ucb1x00_mutex); |
9ca3dc80 | 629 | |
05c45ca9 RK |
630 | goto out; |
631 | ||
632 | err_irq: | |
633 | free_irq(ucb->irq, ucb); | |
9ca3dc80 TK |
634 | err_gpio: |
635 | if (ucb->gpio.base != -1) | |
636 | temp = gpiochip_remove(&ucb->gpio); | |
05c45ca9 RK |
637 | err_free: |
638 | kfree(ucb); | |
639 | err_disable: | |
640 | mcp_disable(mcp); | |
641 | out: | |
642 | return ret; | |
643 | } | |
644 | ||
645 | static void ucb1x00_remove(struct mcp *mcp) | |
646 | { | |
647 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
648 | struct list_head *l, *n; | |
9ca3dc80 | 649 | int ret; |
05c45ca9 | 650 | |
a621aaed | 651 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
652 | list_del(&ucb->node); |
653 | list_for_each_safe(l, n, &ucb->devs) { | |
654 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node); | |
655 | ucb1x00_remove_dev(dev); | |
656 | } | |
a621aaed | 657 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 | 658 | |
9ca3dc80 TK |
659 | if (ucb->gpio.base != -1) { |
660 | ret = gpiochip_remove(&ucb->gpio); | |
661 | if (ret) | |
662 | dev_err(&ucb->dev, "Can't remove gpio chip: %d\n", ret); | |
663 | } | |
664 | ||
05c45ca9 | 665 | free_irq(ucb->irq, ucb); |
0c55445f | 666 | device_unregister(&ucb->dev); |
05c45ca9 RK |
667 | } |
668 | ||
05c45ca9 RK |
669 | int ucb1x00_register_driver(struct ucb1x00_driver *drv) |
670 | { | |
671 | struct ucb1x00 *ucb; | |
672 | ||
673 | INIT_LIST_HEAD(&drv->devs); | |
a621aaed | 674 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
675 | list_add(&drv->node, &ucb1x00_drivers); |
676 | list_for_each_entry(ucb, &ucb1x00_devices, node) { | |
677 | ucb1x00_add_dev(ucb, drv); | |
678 | } | |
a621aaed | 679 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
680 | return 0; |
681 | } | |
682 | ||
683 | void ucb1x00_unregister_driver(struct ucb1x00_driver *drv) | |
684 | { | |
685 | struct list_head *n, *l; | |
686 | ||
a621aaed | 687 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
688 | list_del(&drv->node); |
689 | list_for_each_safe(l, n, &drv->devs) { | |
690 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node); | |
691 | ucb1x00_remove_dev(dev); | |
692 | } | |
a621aaed | 693 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
694 | } |
695 | ||
696 | static int ucb1x00_suspend(struct mcp *mcp, pm_message_t state) | |
697 | { | |
698 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
699 | struct ucb1x00_dev *dev; | |
700 | ||
a621aaed | 701 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
702 | list_for_each_entry(dev, &ucb->devs, dev_node) { |
703 | if (dev->drv->suspend) | |
704 | dev->drv->suspend(dev, state); | |
705 | } | |
a621aaed | 706 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
707 | return 0; |
708 | } | |
709 | ||
710 | static int ucb1x00_resume(struct mcp *mcp) | |
711 | { | |
712 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
713 | struct ucb1x00_dev *dev; | |
714 | ||
9ca3dc80 | 715 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
a621aaed | 716 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
717 | list_for_each_entry(dev, &ucb->devs, dev_node) { |
718 | if (dev->drv->resume) | |
719 | dev->drv->resume(dev); | |
720 | } | |
a621aaed | 721 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
722 | return 0; |
723 | } | |
724 | ||
725 | static struct mcp_driver ucb1x00_driver = { | |
726 | .drv = { | |
727 | .name = "ucb1x00", | |
728 | }, | |
729 | .probe = ucb1x00_probe, | |
730 | .remove = ucb1x00_remove, | |
731 | .suspend = ucb1x00_suspend, | |
732 | .resume = ucb1x00_resume, | |
5dd7bf59 | 733 | .id_table = ucb1x00_id, |
05c45ca9 RK |
734 | }; |
735 | ||
736 | static int __init ucb1x00_init(void) | |
737 | { | |
738 | int ret = class_register(&ucb1x00_class); | |
739 | if (ret == 0) { | |
740 | ret = mcp_driver_register(&ucb1x00_driver); | |
741 | if (ret) | |
742 | class_unregister(&ucb1x00_class); | |
743 | } | |
744 | return ret; | |
745 | } | |
746 | ||
747 | static void __exit ucb1x00_exit(void) | |
748 | { | |
749 | mcp_driver_unregister(&ucb1x00_driver); | |
750 | class_unregister(&ucb1x00_class); | |
751 | } | |
752 | ||
753 | module_init(ucb1x00_init); | |
754 | module_exit(ucb1x00_exit); | |
755 | ||
05c45ca9 RK |
756 | EXPORT_SYMBOL(ucb1x00_io_set_dir); |
757 | EXPORT_SYMBOL(ucb1x00_io_write); | |
758 | EXPORT_SYMBOL(ucb1x00_io_read); | |
759 | ||
760 | EXPORT_SYMBOL(ucb1x00_adc_enable); | |
761 | EXPORT_SYMBOL(ucb1x00_adc_read); | |
762 | EXPORT_SYMBOL(ucb1x00_adc_disable); | |
763 | ||
764 | EXPORT_SYMBOL(ucb1x00_hook_irq); | |
765 | EXPORT_SYMBOL(ucb1x00_free_irq); | |
766 | EXPORT_SYMBOL(ucb1x00_enable_irq); | |
767 | EXPORT_SYMBOL(ucb1x00_disable_irq); | |
768 | ||
769 | EXPORT_SYMBOL(ucb1x00_register_driver); | |
770 | EXPORT_SYMBOL(ucb1x00_unregister_driver); | |
771 | ||
772 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); | |
773 | MODULE_DESCRIPTION("UCB1x00 core driver"); | |
774 | MODULE_LICENSE("GPL"); |