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05c45ca9 RK |
1 | /* |
2 | * linux/drivers/mfd/ucb1x00-core.c | |
3 | * | |
4 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | * | |
10 | * The UCB1x00 core driver provides basic services for handling IO, | |
11 | * the ADC, interrupts, and accessing registers. It is designed | |
12 | * such that everything goes through this layer, thereby providing | |
13 | * a consistent locking methodology, as well as allowing the drivers | |
14 | * to be used on other non-MCP-enabled hardware platforms. | |
15 | * | |
16 | * Note that all locks are private to this file. Nothing else may | |
17 | * touch them. | |
18 | */ | |
05c45ca9 RK |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/device.h> | |
a621aaed | 26 | #include <linux/mutex.h> |
05c45ca9 RK |
27 | |
28 | #include <asm/dma.h> | |
a09e64fb | 29 | #include <mach/hardware.h> |
05c45ca9 RK |
30 | |
31 | #include "ucb1x00.h" | |
32 | ||
a621aaed | 33 | static DEFINE_MUTEX(ucb1x00_mutex); |
05c45ca9 RK |
34 | static LIST_HEAD(ucb1x00_drivers); |
35 | static LIST_HEAD(ucb1x00_devices); | |
36 | ||
37 | /** | |
38 | * ucb1x00_io_set_dir - set IO direction | |
39 | * @ucb: UCB1x00 structure describing chip | |
40 | * @in: bitfield of IO pins to be set as inputs | |
41 | * @out: bitfield of IO pins to be set as outputs | |
42 | * | |
43 | * Set the IO direction of the ten general purpose IO pins on | |
44 | * the UCB1x00 chip. The @in bitfield has priority over the | |
45 | * @out bitfield, in that if you specify a pin as both input | |
46 | * and output, it will end up as an input. | |
47 | * | |
48 | * ucb1x00_enable must have been called to enable the comms | |
49 | * before using this function. | |
50 | * | |
51 | * This function takes a spinlock, disabling interrupts. | |
52 | */ | |
53 | void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out) | |
54 | { | |
55 | unsigned long flags; | |
56 | ||
57 | spin_lock_irqsave(&ucb->io_lock, flags); | |
58 | ucb->io_dir |= out; | |
59 | ucb->io_dir &= ~in; | |
60 | ||
61 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
62 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
63 | } | |
64 | ||
65 | /** | |
66 | * ucb1x00_io_write - set or clear IO outputs | |
67 | * @ucb: UCB1x00 structure describing chip | |
68 | * @set: bitfield of IO pins to set to logic '1' | |
69 | * @clear: bitfield of IO pins to set to logic '0' | |
70 | * | |
71 | * Set the IO output state of the specified IO pins. The value | |
72 | * is retained if the pins are subsequently configured as inputs. | |
73 | * The @clear bitfield has priority over the @set bitfield - | |
74 | * outputs will be cleared. | |
75 | * | |
76 | * ucb1x00_enable must have been called to enable the comms | |
77 | * before using this function. | |
78 | * | |
79 | * This function takes a spinlock, disabling interrupts. | |
80 | */ | |
81 | void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear) | |
82 | { | |
83 | unsigned long flags; | |
84 | ||
85 | spin_lock_irqsave(&ucb->io_lock, flags); | |
86 | ucb->io_out |= set; | |
87 | ucb->io_out &= ~clear; | |
88 | ||
89 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
90 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
91 | } | |
92 | ||
93 | /** | |
94 | * ucb1x00_io_read - read the current state of the IO pins | |
95 | * @ucb: UCB1x00 structure describing chip | |
96 | * | |
97 | * Return a bitfield describing the logic state of the ten | |
98 | * general purpose IO pins. | |
99 | * | |
100 | * ucb1x00_enable must have been called to enable the comms | |
101 | * before using this function. | |
102 | * | |
103 | * This function does not take any semaphores or spinlocks. | |
104 | */ | |
105 | unsigned int ucb1x00_io_read(struct ucb1x00 *ucb) | |
106 | { | |
107 | return ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
108 | } | |
109 | ||
110 | /* | |
111 | * UCB1300 data sheet says we must: | |
112 | * 1. enable ADC => 5us (including reference startup time) | |
113 | * 2. select input => 51*tsibclk => 4.3us | |
114 | * 3. start conversion => 102*tsibclk => 8.5us | |
115 | * (tsibclk = 1/11981000) | |
116 | * Period between SIB 128-bit frames = 10.7us | |
117 | */ | |
118 | ||
119 | /** | |
120 | * ucb1x00_adc_enable - enable the ADC converter | |
121 | * @ucb: UCB1x00 structure describing chip | |
122 | * | |
123 | * Enable the ucb1x00 and ADC converter on the UCB1x00 for use. | |
124 | * Any code wishing to use the ADC converter must call this | |
125 | * function prior to using it. | |
126 | * | |
127 | * This function takes the ADC semaphore to prevent two or more | |
128 | * concurrent uses, and therefore may sleep. As a result, it | |
129 | * can only be called from process context, not interrupt | |
130 | * context. | |
131 | * | |
132 | * You should release the ADC as soon as possible using | |
133 | * ucb1x00_adc_disable. | |
134 | */ | |
135 | void ucb1x00_adc_enable(struct ucb1x00 *ucb) | |
136 | { | |
137 | down(&ucb->adc_sem); | |
138 | ||
139 | ucb->adc_cr |= UCB_ADC_ENA; | |
140 | ||
141 | ucb1x00_enable(ucb); | |
142 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
143 | } | |
144 | ||
145 | /** | |
146 | * ucb1x00_adc_read - read the specified ADC channel | |
147 | * @ucb: UCB1x00 structure describing chip | |
148 | * @adc_channel: ADC channel mask | |
149 | * @sync: wait for syncronisation pulse. | |
150 | * | |
151 | * Start an ADC conversion and wait for the result. Note that | |
152 | * synchronised ADC conversions (via the ADCSYNC pin) must wait | |
153 | * until the trigger is asserted and the conversion is finished. | |
154 | * | |
155 | * This function currently spins waiting for the conversion to | |
156 | * complete (2 frames max without sync). | |
157 | * | |
158 | * If called for a synchronised ADC conversion, it may sleep | |
159 | * with the ADC semaphore held. | |
160 | */ | |
161 | unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync) | |
162 | { | |
163 | unsigned int val; | |
164 | ||
165 | if (sync) | |
166 | adc_channel |= UCB_ADC_SYNC_ENA; | |
167 | ||
168 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel); | |
169 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START); | |
170 | ||
171 | for (;;) { | |
172 | val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); | |
173 | if (val & UCB_ADC_DAT_VAL) | |
174 | break; | |
175 | /* yield to other processes */ | |
176 | set_current_state(TASK_INTERRUPTIBLE); | |
177 | schedule_timeout(1); | |
178 | } | |
179 | ||
180 | return UCB_ADC_DAT(val); | |
181 | } | |
182 | ||
183 | /** | |
184 | * ucb1x00_adc_disable - disable the ADC converter | |
185 | * @ucb: UCB1x00 structure describing chip | |
186 | * | |
187 | * Disable the ADC converter and release the ADC semaphore. | |
188 | */ | |
189 | void ucb1x00_adc_disable(struct ucb1x00 *ucb) | |
190 | { | |
191 | ucb->adc_cr &= ~UCB_ADC_ENA; | |
192 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
193 | ucb1x00_disable(ucb); | |
194 | ||
195 | up(&ucb->adc_sem); | |
196 | } | |
197 | ||
198 | /* | |
199 | * UCB1x00 Interrupt handling. | |
200 | * | |
201 | * The UCB1x00 can generate interrupts when the SIBCLK is stopped. | |
202 | * Since we need to read an internal register, we must re-enable | |
203 | * SIBCLK to talk to the chip. We leave the clock running until | |
204 | * we have finished processing all interrupts from the chip. | |
205 | */ | |
7d12e780 | 206 | static irqreturn_t ucb1x00_irq(int irqnr, void *devid) |
05c45ca9 RK |
207 | { |
208 | struct ucb1x00 *ucb = devid; | |
209 | struct ucb1x00_irq *irq; | |
210 | unsigned int isr, i; | |
211 | ||
212 | ucb1x00_enable(ucb); | |
213 | isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS); | |
214 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr); | |
215 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
216 | ||
217 | for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++) | |
218 | if (isr & 1 && irq->fn) | |
219 | irq->fn(i, irq->devid); | |
220 | ucb1x00_disable(ucb); | |
221 | ||
222 | return IRQ_HANDLED; | |
223 | } | |
224 | ||
225 | /** | |
226 | * ucb1x00_hook_irq - hook a UCB1x00 interrupt | |
227 | * @ucb: UCB1x00 structure describing chip | |
228 | * @idx: interrupt index | |
229 | * @fn: function to call when interrupt is triggered | |
230 | * @devid: device id to pass to interrupt handler | |
231 | * | |
232 | * Hook the specified interrupt. You can only register one handler | |
233 | * for each interrupt source. The interrupt source is not enabled | |
234 | * by this function; use ucb1x00_enable_irq instead. | |
235 | * | |
236 | * Interrupt handlers will be called with other interrupts enabled. | |
237 | * | |
238 | * Returns zero on success, or one of the following errors: | |
239 | * -EINVAL if the interrupt index is invalid | |
240 | * -EBUSY if the interrupt has already been hooked | |
241 | */ | |
242 | int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid) | |
243 | { | |
244 | struct ucb1x00_irq *irq; | |
245 | int ret = -EINVAL; | |
246 | ||
247 | if (idx < 16) { | |
248 | irq = ucb->irq_handler + idx; | |
249 | ret = -EBUSY; | |
250 | ||
251 | spin_lock_irq(&ucb->lock); | |
252 | if (irq->fn == NULL) { | |
253 | irq->devid = devid; | |
254 | irq->fn = fn; | |
255 | ret = 0; | |
256 | } | |
257 | spin_unlock_irq(&ucb->lock); | |
258 | } | |
259 | return ret; | |
260 | } | |
261 | ||
262 | /** | |
263 | * ucb1x00_enable_irq - enable an UCB1x00 interrupt source | |
264 | * @ucb: UCB1x00 structure describing chip | |
265 | * @idx: interrupt index | |
266 | * @edges: interrupt edges to enable | |
267 | * | |
268 | * Enable the specified interrupt to trigger on %UCB_RISING, | |
269 | * %UCB_FALLING or both edges. The interrupt should have been | |
270 | * hooked by ucb1x00_hook_irq. | |
271 | */ | |
272 | void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
273 | { | |
274 | unsigned long flags; | |
275 | ||
276 | if (idx < 16) { | |
277 | spin_lock_irqsave(&ucb->lock, flags); | |
278 | ||
279 | ucb1x00_enable(ucb); | |
280 | if (edges & UCB_RISING) { | |
281 | ucb->irq_ris_enbl |= 1 << idx; | |
282 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
283 | } | |
284 | if (edges & UCB_FALLING) { | |
285 | ucb->irq_fal_enbl |= 1 << idx; | |
286 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
287 | } | |
288 | ucb1x00_disable(ucb); | |
289 | spin_unlock_irqrestore(&ucb->lock, flags); | |
290 | } | |
291 | } | |
292 | ||
293 | /** | |
294 | * ucb1x00_disable_irq - disable an UCB1x00 interrupt source | |
295 | * @ucb: UCB1x00 structure describing chip | |
296 | * @edges: interrupt edges to disable | |
297 | * | |
298 | * Disable the specified interrupt triggering on the specified | |
299 | * (%UCB_RISING, %UCB_FALLING or both) edges. | |
300 | */ | |
301 | void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
302 | { | |
303 | unsigned long flags; | |
304 | ||
305 | if (idx < 16) { | |
306 | spin_lock_irqsave(&ucb->lock, flags); | |
307 | ||
308 | ucb1x00_enable(ucb); | |
309 | if (edges & UCB_RISING) { | |
310 | ucb->irq_ris_enbl &= ~(1 << idx); | |
311 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
312 | } | |
313 | if (edges & UCB_FALLING) { | |
314 | ucb->irq_fal_enbl &= ~(1 << idx); | |
315 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
316 | } | |
317 | ucb1x00_disable(ucb); | |
318 | spin_unlock_irqrestore(&ucb->lock, flags); | |
319 | } | |
320 | } | |
321 | ||
322 | /** | |
323 | * ucb1x00_free_irq - disable and free the specified UCB1x00 interrupt | |
324 | * @ucb: UCB1x00 structure describing chip | |
325 | * @idx: interrupt index | |
326 | * @devid: device id. | |
327 | * | |
328 | * Disable the interrupt source and remove the handler. devid must | |
329 | * match the devid passed when hooking the interrupt. | |
330 | * | |
331 | * Returns zero on success, or one of the following errors: | |
332 | * -EINVAL if the interrupt index is invalid | |
333 | * -ENOENT if devid does not match | |
334 | */ | |
335 | int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid) | |
336 | { | |
337 | struct ucb1x00_irq *irq; | |
338 | int ret; | |
339 | ||
340 | if (idx >= 16) | |
341 | goto bad; | |
342 | ||
343 | irq = ucb->irq_handler + idx; | |
344 | ret = -ENOENT; | |
345 | ||
346 | spin_lock_irq(&ucb->lock); | |
347 | if (irq->devid == devid) { | |
348 | ucb->irq_ris_enbl &= ~(1 << idx); | |
349 | ucb->irq_fal_enbl &= ~(1 << idx); | |
350 | ||
351 | ucb1x00_enable(ucb); | |
352 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
353 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
354 | ucb1x00_disable(ucb); | |
355 | ||
356 | irq->fn = NULL; | |
357 | irq->devid = NULL; | |
358 | ret = 0; | |
359 | } | |
360 | spin_unlock_irq(&ucb->lock); | |
361 | return ret; | |
362 | ||
363 | bad: | |
364 | printk(KERN_ERR "Freeing bad UCB1x00 irq %d\n", idx); | |
365 | return -EINVAL; | |
366 | } | |
367 | ||
368 | static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv) | |
369 | { | |
370 | struct ucb1x00_dev *dev; | |
371 | int ret = -ENOMEM; | |
372 | ||
373 | dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL); | |
374 | if (dev) { | |
375 | dev->ucb = ucb; | |
376 | dev->drv = drv; | |
377 | ||
378 | ret = drv->add(dev); | |
379 | ||
380 | if (ret == 0) { | |
381 | list_add(&dev->dev_node, &ucb->devs); | |
382 | list_add(&dev->drv_node, &drv->devs); | |
383 | } else { | |
384 | kfree(dev); | |
385 | } | |
386 | } | |
387 | return ret; | |
388 | } | |
389 | ||
390 | static void ucb1x00_remove_dev(struct ucb1x00_dev *dev) | |
391 | { | |
392 | dev->drv->remove(dev); | |
393 | list_del(&dev->dev_node); | |
394 | list_del(&dev->drv_node); | |
395 | kfree(dev); | |
396 | } | |
397 | ||
398 | /* | |
399 | * Try to probe our interrupt, rather than relying on lots of | |
400 | * hard-coded machine dependencies. For reference, the expected | |
401 | * IRQ mappings are: | |
402 | * | |
403 | * Machine Default IRQ | |
404 | * adsbitsy IRQ_GPCIN4 | |
405 | * cerf IRQ_GPIO_UCB1200_IRQ | |
406 | * flexanet IRQ_GPIO_GUI | |
407 | * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ | |
408 | * graphicsclient ADS_EXT_IRQ(8) | |
409 | * graphicsmaster ADS_EXT_IRQ(8) | |
410 | * lart LART_IRQ_UCB1200 | |
411 | * omnimeter IRQ_GPIO23 | |
412 | * pfs168 IRQ_GPIO_UCB1300_IRQ | |
413 | * simpad IRQ_GPIO_UCB1300_IRQ | |
414 | * shannon SHANNON_IRQ_GPIO_IRQ_CODEC | |
415 | * yopy IRQ_GPIO_UCB1200_IRQ | |
416 | */ | |
417 | static int ucb1x00_detect_irq(struct ucb1x00 *ucb) | |
418 | { | |
419 | unsigned long mask; | |
420 | ||
421 | mask = probe_irq_on(); | |
cfc73656 IM |
422 | if (!mask) { |
423 | probe_irq_off(mask); | |
05c45ca9 | 424 | return NO_IRQ; |
cfc73656 | 425 | } |
05c45ca9 RK |
426 | |
427 | /* | |
428 | * Enable the ADC interrupt. | |
429 | */ | |
430 | ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); | |
431 | ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); | |
432 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
433 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
434 | ||
435 | /* | |
436 | * Cause an ADC interrupt. | |
437 | */ | |
438 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); | |
439 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); | |
440 | ||
441 | /* | |
442 | * Wait for the conversion to complete. | |
443 | */ | |
444 | while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0); | |
445 | ucb1x00_reg_write(ucb, UCB_ADC_CR, 0); | |
446 | ||
447 | /* | |
448 | * Disable and clear interrupt. | |
449 | */ | |
450 | ucb1x00_reg_write(ucb, UCB_IE_RIS, 0); | |
451 | ucb1x00_reg_write(ucb, UCB_IE_FAL, 0); | |
452 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
453 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
454 | ||
455 | /* | |
456 | * Read triggered interrupt. | |
457 | */ | |
458 | return probe_irq_off(mask); | |
459 | } | |
460 | ||
0c55445f | 461 | static void ucb1x00_release(struct device *dev) |
585f5457 NP |
462 | { |
463 | struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); | |
464 | kfree(ucb); | |
465 | } | |
466 | ||
467 | static struct class ucb1x00_class = { | |
468 | .name = "ucb1x00", | |
0c55445f | 469 | .dev_release = ucb1x00_release, |
585f5457 NP |
470 | }; |
471 | ||
05c45ca9 RK |
472 | static int ucb1x00_probe(struct mcp *mcp) |
473 | { | |
474 | struct ucb1x00 *ucb; | |
475 | struct ucb1x00_driver *drv; | |
476 | unsigned int id; | |
477 | int ret = -ENODEV; | |
478 | ||
479 | mcp_enable(mcp); | |
480 | id = mcp_reg_read(mcp, UCB_ID); | |
481 | ||
b94ea6c0 | 482 | if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) { |
05c45ca9 RK |
483 | printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id); |
484 | goto err_disable; | |
485 | } | |
486 | ||
dd00cc48 | 487 | ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL); |
05c45ca9 RK |
488 | ret = -ENOMEM; |
489 | if (!ucb) | |
490 | goto err_disable; | |
491 | ||
05c45ca9 | 492 | |
0c55445f TJ |
493 | ucb->dev.class = &ucb1x00_class; |
494 | ucb->dev.parent = &mcp->attached_device; | |
495 | strlcpy(ucb->dev.bus_id, "ucb1x00", sizeof(ucb->dev.bus_id)); | |
05c45ca9 RK |
496 | |
497 | spin_lock_init(&ucb->lock); | |
498 | spin_lock_init(&ucb->io_lock); | |
499 | sema_init(&ucb->adc_sem, 1); | |
500 | ||
501 | ucb->id = id; | |
502 | ucb->mcp = mcp; | |
503 | ucb->irq = ucb1x00_detect_irq(ucb); | |
504 | if (ucb->irq == NO_IRQ) { | |
505 | printk(KERN_ERR "UCB1x00: IRQ probe failed\n"); | |
506 | ret = -ENODEV; | |
507 | goto err_free; | |
508 | } | |
509 | ||
dace1453 | 510 | ret = request_irq(ucb->irq, ucb1x00_irq, IRQF_TRIGGER_RISING, |
9ded96f2 | 511 | "UCB1x00", ucb); |
05c45ca9 RK |
512 | if (ret) { |
513 | printk(KERN_ERR "ucb1x00: unable to grab irq%d: %d\n", | |
514 | ucb->irq, ret); | |
515 | goto err_free; | |
516 | } | |
517 | ||
05c45ca9 RK |
518 | mcp_set_drvdata(mcp, ucb); |
519 | ||
0c55445f | 520 | ret = device_register(&ucb->dev); |
05c45ca9 RK |
521 | if (ret) |
522 | goto err_irq; | |
523 | ||
524 | INIT_LIST_HEAD(&ucb->devs); | |
a621aaed | 525 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
526 | list_add(&ucb->node, &ucb1x00_devices); |
527 | list_for_each_entry(drv, &ucb1x00_drivers, node) { | |
528 | ucb1x00_add_dev(ucb, drv); | |
529 | } | |
a621aaed | 530 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
531 | goto out; |
532 | ||
533 | err_irq: | |
534 | free_irq(ucb->irq, ucb); | |
535 | err_free: | |
536 | kfree(ucb); | |
537 | err_disable: | |
538 | mcp_disable(mcp); | |
539 | out: | |
540 | return ret; | |
541 | } | |
542 | ||
543 | static void ucb1x00_remove(struct mcp *mcp) | |
544 | { | |
545 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
546 | struct list_head *l, *n; | |
547 | ||
a621aaed | 548 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
549 | list_del(&ucb->node); |
550 | list_for_each_safe(l, n, &ucb->devs) { | |
551 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node); | |
552 | ucb1x00_remove_dev(dev); | |
553 | } | |
a621aaed | 554 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
555 | |
556 | free_irq(ucb->irq, ucb); | |
0c55445f | 557 | device_unregister(&ucb->dev); |
05c45ca9 RK |
558 | } |
559 | ||
05c45ca9 RK |
560 | int ucb1x00_register_driver(struct ucb1x00_driver *drv) |
561 | { | |
562 | struct ucb1x00 *ucb; | |
563 | ||
564 | INIT_LIST_HEAD(&drv->devs); | |
a621aaed | 565 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
566 | list_add(&drv->node, &ucb1x00_drivers); |
567 | list_for_each_entry(ucb, &ucb1x00_devices, node) { | |
568 | ucb1x00_add_dev(ucb, drv); | |
569 | } | |
a621aaed | 570 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
571 | return 0; |
572 | } | |
573 | ||
574 | void ucb1x00_unregister_driver(struct ucb1x00_driver *drv) | |
575 | { | |
576 | struct list_head *n, *l; | |
577 | ||
a621aaed | 578 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
579 | list_del(&drv->node); |
580 | list_for_each_safe(l, n, &drv->devs) { | |
581 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node); | |
582 | ucb1x00_remove_dev(dev); | |
583 | } | |
a621aaed | 584 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
585 | } |
586 | ||
587 | static int ucb1x00_suspend(struct mcp *mcp, pm_message_t state) | |
588 | { | |
589 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
590 | struct ucb1x00_dev *dev; | |
591 | ||
a621aaed | 592 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
593 | list_for_each_entry(dev, &ucb->devs, dev_node) { |
594 | if (dev->drv->suspend) | |
595 | dev->drv->suspend(dev, state); | |
596 | } | |
a621aaed | 597 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
598 | return 0; |
599 | } | |
600 | ||
601 | static int ucb1x00_resume(struct mcp *mcp) | |
602 | { | |
603 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
604 | struct ucb1x00_dev *dev; | |
605 | ||
a621aaed | 606 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
607 | list_for_each_entry(dev, &ucb->devs, dev_node) { |
608 | if (dev->drv->resume) | |
609 | dev->drv->resume(dev); | |
610 | } | |
a621aaed | 611 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
612 | return 0; |
613 | } | |
614 | ||
615 | static struct mcp_driver ucb1x00_driver = { | |
616 | .drv = { | |
617 | .name = "ucb1x00", | |
618 | }, | |
619 | .probe = ucb1x00_probe, | |
620 | .remove = ucb1x00_remove, | |
621 | .suspend = ucb1x00_suspend, | |
622 | .resume = ucb1x00_resume, | |
623 | }; | |
624 | ||
625 | static int __init ucb1x00_init(void) | |
626 | { | |
627 | int ret = class_register(&ucb1x00_class); | |
628 | if (ret == 0) { | |
629 | ret = mcp_driver_register(&ucb1x00_driver); | |
630 | if (ret) | |
631 | class_unregister(&ucb1x00_class); | |
632 | } | |
633 | return ret; | |
634 | } | |
635 | ||
636 | static void __exit ucb1x00_exit(void) | |
637 | { | |
638 | mcp_driver_unregister(&ucb1x00_driver); | |
639 | class_unregister(&ucb1x00_class); | |
640 | } | |
641 | ||
642 | module_init(ucb1x00_init); | |
643 | module_exit(ucb1x00_exit); | |
644 | ||
05c45ca9 RK |
645 | EXPORT_SYMBOL(ucb1x00_io_set_dir); |
646 | EXPORT_SYMBOL(ucb1x00_io_write); | |
647 | EXPORT_SYMBOL(ucb1x00_io_read); | |
648 | ||
649 | EXPORT_SYMBOL(ucb1x00_adc_enable); | |
650 | EXPORT_SYMBOL(ucb1x00_adc_read); | |
651 | EXPORT_SYMBOL(ucb1x00_adc_disable); | |
652 | ||
653 | EXPORT_SYMBOL(ucb1x00_hook_irq); | |
654 | EXPORT_SYMBOL(ucb1x00_free_irq); | |
655 | EXPORT_SYMBOL(ucb1x00_enable_irq); | |
656 | EXPORT_SYMBOL(ucb1x00_disable_irq); | |
657 | ||
658 | EXPORT_SYMBOL(ucb1x00_register_driver); | |
659 | EXPORT_SYMBOL(ucb1x00_unregister_driver); | |
660 | ||
661 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); | |
662 | MODULE_DESCRIPTION("UCB1x00 core driver"); | |
663 | MODULE_LICENSE("GPL"); |