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05c45ca9 RK |
1 | /* |
2 | * linux/drivers/mfd/ucb1x00-core.c | |
3 | * | |
4 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | * | |
10 | * The UCB1x00 core driver provides basic services for handling IO, | |
11 | * the ADC, interrupts, and accessing registers. It is designed | |
12 | * such that everything goes through this layer, thereby providing | |
13 | * a consistent locking methodology, as well as allowing the drivers | |
14 | * to be used on other non-MCP-enabled hardware platforms. | |
15 | * | |
16 | * Note that all locks are private to this file. Nothing else may | |
17 | * touch them. | |
18 | */ | |
05c45ca9 RK |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
d43c36dc | 21 | #include <linux/sched.h> |
05c45ca9 RK |
22 | #include <linux/slab.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/interrupt.h> | |
a3364409 | 26 | #include <linux/irq.h> |
05c45ca9 | 27 | #include <linux/device.h> |
a621aaed | 28 | #include <linux/mutex.h> |
c8602edf | 29 | #include <linux/mfd/ucb1x00.h> |
5a09b712 | 30 | #include <linux/pm.h> |
7d94352e | 31 | #include <linux/gpio/driver.h> |
05c45ca9 | 32 | |
a621aaed | 33 | static DEFINE_MUTEX(ucb1x00_mutex); |
05c45ca9 RK |
34 | static LIST_HEAD(ucb1x00_drivers); |
35 | static LIST_HEAD(ucb1x00_devices); | |
36 | ||
37 | /** | |
38 | * ucb1x00_io_set_dir - set IO direction | |
39 | * @ucb: UCB1x00 structure describing chip | |
40 | * @in: bitfield of IO pins to be set as inputs | |
41 | * @out: bitfield of IO pins to be set as outputs | |
42 | * | |
43 | * Set the IO direction of the ten general purpose IO pins on | |
44 | * the UCB1x00 chip. The @in bitfield has priority over the | |
45 | * @out bitfield, in that if you specify a pin as both input | |
46 | * and output, it will end up as an input. | |
47 | * | |
48 | * ucb1x00_enable must have been called to enable the comms | |
49 | * before using this function. | |
50 | * | |
51 | * This function takes a spinlock, disabling interrupts. | |
52 | */ | |
53 | void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out) | |
54 | { | |
55 | unsigned long flags; | |
56 | ||
57 | spin_lock_irqsave(&ucb->io_lock, flags); | |
58 | ucb->io_dir |= out; | |
59 | ucb->io_dir &= ~in; | |
60 | ||
61 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
62 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
63 | } | |
64 | ||
65 | /** | |
66 | * ucb1x00_io_write - set or clear IO outputs | |
67 | * @ucb: UCB1x00 structure describing chip | |
68 | * @set: bitfield of IO pins to set to logic '1' | |
69 | * @clear: bitfield of IO pins to set to logic '0' | |
70 | * | |
71 | * Set the IO output state of the specified IO pins. The value | |
72 | * is retained if the pins are subsequently configured as inputs. | |
73 | * The @clear bitfield has priority over the @set bitfield - | |
74 | * outputs will be cleared. | |
75 | * | |
76 | * ucb1x00_enable must have been called to enable the comms | |
77 | * before using this function. | |
78 | * | |
79 | * This function takes a spinlock, disabling interrupts. | |
80 | */ | |
81 | void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear) | |
82 | { | |
83 | unsigned long flags; | |
84 | ||
85 | spin_lock_irqsave(&ucb->io_lock, flags); | |
86 | ucb->io_out |= set; | |
87 | ucb->io_out &= ~clear; | |
88 | ||
89 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
90 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
91 | } | |
92 | ||
93 | /** | |
94 | * ucb1x00_io_read - read the current state of the IO pins | |
95 | * @ucb: UCB1x00 structure describing chip | |
96 | * | |
97 | * Return a bitfield describing the logic state of the ten | |
98 | * general purpose IO pins. | |
99 | * | |
100 | * ucb1x00_enable must have been called to enable the comms | |
101 | * before using this function. | |
102 | * | |
cae15476 | 103 | * This function does not take any mutexes or spinlocks. |
05c45ca9 RK |
104 | */ |
105 | unsigned int ucb1x00_io_read(struct ucb1x00 *ucb) | |
106 | { | |
107 | return ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
108 | } | |
109 | ||
9ca3dc80 TK |
110 | static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
111 | { | |
7d94352e | 112 | struct ucb1x00 *ucb = gpiochip_get_data(chip); |
9ca3dc80 TK |
113 | unsigned long flags; |
114 | ||
115 | spin_lock_irqsave(&ucb->io_lock, flags); | |
116 | if (value) | |
117 | ucb->io_out |= 1 << offset; | |
118 | else | |
119 | ucb->io_out &= ~(1 << offset); | |
120 | ||
ed442b67 | 121 | ucb1x00_enable(ucb); |
9ca3dc80 | 122 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
ed442b67 | 123 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
124 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
125 | } | |
126 | ||
127 | static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset) | |
128 | { | |
7d94352e | 129 | struct ucb1x00 *ucb = gpiochip_get_data(chip); |
ed442b67 RK |
130 | unsigned val; |
131 | ||
132 | ucb1x00_enable(ucb); | |
133 | val = ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
134 | ucb1x00_disable(ucb); | |
135 | ||
0c7f3f92 | 136 | return !!(val & (1 << offset)); |
9ca3dc80 TK |
137 | } |
138 | ||
139 | static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
140 | { | |
7d94352e | 141 | struct ucb1x00 *ucb = gpiochip_get_data(chip); |
9ca3dc80 TK |
142 | unsigned long flags; |
143 | ||
144 | spin_lock_irqsave(&ucb->io_lock, flags); | |
145 | ucb->io_dir &= ~(1 << offset); | |
ed442b67 | 146 | ucb1x00_enable(ucb); |
9ca3dc80 | 147 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
ed442b67 | 148 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
149 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
154 | static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset | |
155 | , int value) | |
156 | { | |
7d94352e | 157 | struct ucb1x00 *ucb = gpiochip_get_data(chip); |
9ca3dc80 | 158 | unsigned long flags; |
c23bb602 | 159 | unsigned old, mask = 1 << offset; |
9ca3dc80 TK |
160 | |
161 | spin_lock_irqsave(&ucb->io_lock, flags); | |
c23bb602 | 162 | old = ucb->io_out; |
9ca3dc80 | 163 | if (value) |
c23bb602 | 164 | ucb->io_out |= mask; |
9ca3dc80 | 165 | else |
c23bb602 RK |
166 | ucb->io_out &= ~mask; |
167 | ||
ed442b67 | 168 | ucb1x00_enable(ucb); |
c23bb602 RK |
169 | if (old != ucb->io_out) |
170 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
171 | ||
172 | if (!(ucb->io_dir & mask)) { | |
173 | ucb->io_dir |= mask; | |
174 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
175 | } | |
ed442b67 | 176 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
177 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
a3364409 RK |
182 | static int ucb1x00_to_irq(struct gpio_chip *chip, unsigned offset) |
183 | { | |
7d94352e | 184 | struct ucb1x00 *ucb = gpiochip_get_data(chip); |
a3364409 RK |
185 | |
186 | return ucb->irq_base > 0 ? ucb->irq_base + offset : -ENXIO; | |
187 | } | |
188 | ||
05c45ca9 RK |
189 | /* |
190 | * UCB1300 data sheet says we must: | |
191 | * 1. enable ADC => 5us (including reference startup time) | |
192 | * 2. select input => 51*tsibclk => 4.3us | |
193 | * 3. start conversion => 102*tsibclk => 8.5us | |
194 | * (tsibclk = 1/11981000) | |
195 | * Period between SIB 128-bit frames = 10.7us | |
196 | */ | |
197 | ||
198 | /** | |
199 | * ucb1x00_adc_enable - enable the ADC converter | |
200 | * @ucb: UCB1x00 structure describing chip | |
201 | * | |
202 | * Enable the ucb1x00 and ADC converter on the UCB1x00 for use. | |
203 | * Any code wishing to use the ADC converter must call this | |
204 | * function prior to using it. | |
205 | * | |
cae15476 | 206 | * This function takes the ADC mutex to prevent two or more |
05c45ca9 RK |
207 | * concurrent uses, and therefore may sleep. As a result, it |
208 | * can only be called from process context, not interrupt | |
209 | * context. | |
210 | * | |
211 | * You should release the ADC as soon as possible using | |
212 | * ucb1x00_adc_disable. | |
213 | */ | |
214 | void ucb1x00_adc_enable(struct ucb1x00 *ucb) | |
215 | { | |
cae15476 | 216 | mutex_lock(&ucb->adc_mutex); |
05c45ca9 RK |
217 | |
218 | ucb->adc_cr |= UCB_ADC_ENA; | |
219 | ||
220 | ucb1x00_enable(ucb); | |
221 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
222 | } | |
223 | ||
224 | /** | |
225 | * ucb1x00_adc_read - read the specified ADC channel | |
226 | * @ucb: UCB1x00 structure describing chip | |
227 | * @adc_channel: ADC channel mask | |
228 | * @sync: wait for syncronisation pulse. | |
229 | * | |
230 | * Start an ADC conversion and wait for the result. Note that | |
231 | * synchronised ADC conversions (via the ADCSYNC pin) must wait | |
232 | * until the trigger is asserted and the conversion is finished. | |
233 | * | |
234 | * This function currently spins waiting for the conversion to | |
235 | * complete (2 frames max without sync). | |
236 | * | |
237 | * If called for a synchronised ADC conversion, it may sleep | |
cae15476 | 238 | * with the ADC mutex held. |
05c45ca9 RK |
239 | */ |
240 | unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync) | |
241 | { | |
242 | unsigned int val; | |
243 | ||
244 | if (sync) | |
245 | adc_channel |= UCB_ADC_SYNC_ENA; | |
246 | ||
247 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel); | |
248 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START); | |
249 | ||
250 | for (;;) { | |
251 | val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); | |
252 | if (val & UCB_ADC_DAT_VAL) | |
253 | break; | |
254 | /* yield to other processes */ | |
255 | set_current_state(TASK_INTERRUPTIBLE); | |
256 | schedule_timeout(1); | |
257 | } | |
258 | ||
259 | return UCB_ADC_DAT(val); | |
260 | } | |
261 | ||
262 | /** | |
263 | * ucb1x00_adc_disable - disable the ADC converter | |
264 | * @ucb: UCB1x00 structure describing chip | |
265 | * | |
cae15476 | 266 | * Disable the ADC converter and release the ADC mutex. |
05c45ca9 RK |
267 | */ |
268 | void ucb1x00_adc_disable(struct ucb1x00 *ucb) | |
269 | { | |
270 | ucb->adc_cr &= ~UCB_ADC_ENA; | |
271 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
272 | ucb1x00_disable(ucb); | |
273 | ||
cae15476 | 274 | mutex_unlock(&ucb->adc_mutex); |
05c45ca9 RK |
275 | } |
276 | ||
277 | /* | |
278 | * UCB1x00 Interrupt handling. | |
279 | * | |
280 | * The UCB1x00 can generate interrupts when the SIBCLK is stopped. | |
281 | * Since we need to read an internal register, we must re-enable | |
282 | * SIBCLK to talk to the chip. We leave the clock running until | |
283 | * we have finished processing all interrupts from the chip. | |
284 | */ | |
bd0b9ac4 | 285 | static void ucb1x00_irq(struct irq_desc *desc) |
05c45ca9 | 286 | { |
a3364409 | 287 | struct ucb1x00 *ucb = irq_desc_get_handler_data(desc); |
05c45ca9 RK |
288 | unsigned int isr, i; |
289 | ||
290 | ucb1x00_enable(ucb); | |
291 | isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS); | |
292 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr); | |
293 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
294 | ||
0d674d93 | 295 | for (i = 0; i < 16 && isr; i++, isr >>= 1) |
a3364409 RK |
296 | if (isr & 1) |
297 | generic_handle_irq(ucb->irq_base + i); | |
05c45ca9 | 298 | ucb1x00_disable(ucb); |
05c45ca9 RK |
299 | } |
300 | ||
a3364409 | 301 | static void ucb1x00_irq_update(struct ucb1x00 *ucb, unsigned mask) |
05c45ca9 | 302 | { |
a3364409 RK |
303 | ucb1x00_enable(ucb); |
304 | if (ucb->irq_ris_enbl & mask) | |
305 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & | |
306 | ucb->irq_mask); | |
307 | if (ucb->irq_fal_enbl & mask) | |
308 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & | |
309 | ucb->irq_mask); | |
310 | ucb1x00_disable(ucb); | |
05c45ca9 RK |
311 | } |
312 | ||
a3364409 | 313 | static void ucb1x00_irq_noop(struct irq_data *data) |
05c45ca9 | 314 | { |
05c45ca9 RK |
315 | } |
316 | ||
a3364409 | 317 | static void ucb1x00_irq_mask(struct irq_data *data) |
05c45ca9 | 318 | { |
a3364409 RK |
319 | struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); |
320 | unsigned mask = 1 << (data->irq - ucb->irq_base); | |
05c45ca9 | 321 | |
a3364409 RK |
322 | raw_spin_lock(&ucb->irq_lock); |
323 | ucb->irq_mask &= ~mask; | |
324 | ucb1x00_irq_update(ucb, mask); | |
325 | raw_spin_unlock(&ucb->irq_lock); | |
05c45ca9 RK |
326 | } |
327 | ||
a3364409 | 328 | static void ucb1x00_irq_unmask(struct irq_data *data) |
05c45ca9 | 329 | { |
a3364409 RK |
330 | struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); |
331 | unsigned mask = 1 << (data->irq - ucb->irq_base); | |
05c45ca9 | 332 | |
a3364409 RK |
333 | raw_spin_lock(&ucb->irq_lock); |
334 | ucb->irq_mask |= mask; | |
335 | ucb1x00_irq_update(ucb, mask); | |
336 | raw_spin_unlock(&ucb->irq_lock); | |
337 | } | |
05c45ca9 | 338 | |
a3364409 RK |
339 | static int ucb1x00_irq_set_type(struct irq_data *data, unsigned int type) |
340 | { | |
341 | struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); | |
342 | unsigned mask = 1 << (data->irq - ucb->irq_base); | |
05c45ca9 | 343 | |
a3364409 RK |
344 | raw_spin_lock(&ucb->irq_lock); |
345 | if (type & IRQ_TYPE_EDGE_RISING) | |
346 | ucb->irq_ris_enbl |= mask; | |
347 | else | |
348 | ucb->irq_ris_enbl &= ~mask; | |
05c45ca9 | 349 | |
a3364409 RK |
350 | if (type & IRQ_TYPE_EDGE_FALLING) |
351 | ucb->irq_fal_enbl |= mask; | |
352 | else | |
353 | ucb->irq_fal_enbl &= ~mask; | |
354 | if (ucb->irq_mask & mask) { | |
355 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & | |
356 | ucb->irq_mask); | |
357 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & | |
358 | ucb->irq_mask); | |
05c45ca9 | 359 | } |
a3364409 | 360 | raw_spin_unlock(&ucb->irq_lock); |
05c45ca9 | 361 | |
a3364409 | 362 | return 0; |
05c45ca9 RK |
363 | } |
364 | ||
33237616 RK |
365 | static int ucb1x00_irq_set_wake(struct irq_data *data, unsigned int on) |
366 | { | |
367 | struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); | |
368 | struct ucb1x00_plat_data *pdata = ucb->mcp->attached_device.platform_data; | |
369 | unsigned mask = 1 << (data->irq - ucb->irq_base); | |
370 | ||
371 | if (!pdata || !pdata->can_wakeup) | |
372 | return -EINVAL; | |
373 | ||
374 | raw_spin_lock(&ucb->irq_lock); | |
375 | if (on) | |
376 | ucb->irq_wake |= mask; | |
377 | else | |
378 | ucb->irq_wake &= ~mask; | |
379 | raw_spin_unlock(&ucb->irq_lock); | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
a3364409 RK |
384 | static struct irq_chip ucb1x00_irqchip = { |
385 | .name = "ucb1x00", | |
386 | .irq_ack = ucb1x00_irq_noop, | |
387 | .irq_mask = ucb1x00_irq_mask, | |
388 | .irq_unmask = ucb1x00_irq_unmask, | |
389 | .irq_set_type = ucb1x00_irq_set_type, | |
33237616 | 390 | .irq_set_wake = ucb1x00_irq_set_wake, |
a3364409 RK |
391 | }; |
392 | ||
05c45ca9 RK |
393 | static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv) |
394 | { | |
395 | struct ucb1x00_dev *dev; | |
02a0bf6e | 396 | int ret; |
05c45ca9 RK |
397 | |
398 | dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL); | |
02a0bf6e LJ |
399 | if (!dev) |
400 | return -ENOMEM; | |
401 | ||
402 | dev->ucb = ucb; | |
403 | dev->drv = drv; | |
404 | ||
405 | ret = drv->add(dev); | |
406 | if (ret) { | |
407 | kfree(dev); | |
408 | return ret; | |
05c45ca9 | 409 | } |
02a0bf6e LJ |
410 | |
411 | list_add_tail(&dev->dev_node, &ucb->devs); | |
412 | list_add_tail(&dev->drv_node, &drv->devs); | |
413 | ||
05c45ca9 RK |
414 | return ret; |
415 | } | |
416 | ||
417 | static void ucb1x00_remove_dev(struct ucb1x00_dev *dev) | |
418 | { | |
419 | dev->drv->remove(dev); | |
420 | list_del(&dev->dev_node); | |
421 | list_del(&dev->drv_node); | |
422 | kfree(dev); | |
423 | } | |
424 | ||
425 | /* | |
426 | * Try to probe our interrupt, rather than relying on lots of | |
427 | * hard-coded machine dependencies. For reference, the expected | |
428 | * IRQ mappings are: | |
429 | * | |
430 | * Machine Default IRQ | |
431 | * adsbitsy IRQ_GPCIN4 | |
432 | * cerf IRQ_GPIO_UCB1200_IRQ | |
433 | * flexanet IRQ_GPIO_GUI | |
434 | * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ | |
435 | * graphicsclient ADS_EXT_IRQ(8) | |
436 | * graphicsmaster ADS_EXT_IRQ(8) | |
437 | * lart LART_IRQ_UCB1200 | |
438 | * omnimeter IRQ_GPIO23 | |
439 | * pfs168 IRQ_GPIO_UCB1300_IRQ | |
440 | * simpad IRQ_GPIO_UCB1300_IRQ | |
441 | * shannon SHANNON_IRQ_GPIO_IRQ_CODEC | |
442 | * yopy IRQ_GPIO_UCB1200_IRQ | |
443 | */ | |
444 | static int ucb1x00_detect_irq(struct ucb1x00 *ucb) | |
445 | { | |
446 | unsigned long mask; | |
447 | ||
448 | mask = probe_irq_on(); | |
05c45ca9 RK |
449 | |
450 | /* | |
451 | * Enable the ADC interrupt. | |
452 | */ | |
453 | ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); | |
454 | ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); | |
455 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
456 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
457 | ||
458 | /* | |
459 | * Cause an ADC interrupt. | |
460 | */ | |
461 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); | |
462 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); | |
463 | ||
464 | /* | |
465 | * Wait for the conversion to complete. | |
466 | */ | |
467 | while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0); | |
468 | ucb1x00_reg_write(ucb, UCB_ADC_CR, 0); | |
469 | ||
470 | /* | |
471 | * Disable and clear interrupt. | |
472 | */ | |
473 | ucb1x00_reg_write(ucb, UCB_IE_RIS, 0); | |
474 | ucb1x00_reg_write(ucb, UCB_IE_FAL, 0); | |
475 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
476 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
477 | ||
478 | /* | |
479 | * Read triggered interrupt. | |
480 | */ | |
481 | return probe_irq_off(mask); | |
482 | } | |
483 | ||
0c55445f | 484 | static void ucb1x00_release(struct device *dev) |
585f5457 NP |
485 | { |
486 | struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); | |
487 | kfree(ucb); | |
488 | } | |
489 | ||
490 | static struct class ucb1x00_class = { | |
491 | .name = "ucb1x00", | |
0c55445f | 492 | .dev_release = ucb1x00_release, |
585f5457 NP |
493 | }; |
494 | ||
05c45ca9 RK |
495 | static int ucb1x00_probe(struct mcp *mcp) |
496 | { | |
2f7510c6 | 497 | struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
05c45ca9 | 498 | struct ucb1x00_driver *drv; |
2f7510c6 | 499 | struct ucb1x00 *ucb; |
a3364409 | 500 | unsigned id, i, irq_base; |
05c45ca9 RK |
501 | int ret = -ENODEV; |
502 | ||
2f7510c6 RK |
503 | /* Tell the platform to deassert the UCB1x00 reset */ |
504 | if (pdata && pdata->reset) | |
505 | pdata->reset(UCB_RST_PROBE); | |
506 | ||
05c45ca9 RK |
507 | mcp_enable(mcp); |
508 | id = mcp_reg_read(mcp, UCB_ID); | |
2b4d9d2b | 509 | mcp_disable(mcp); |
05c45ca9 | 510 | |
65f2e753 RK |
511 | if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) { |
512 | printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id); | |
2b4d9d2b | 513 | goto out; |
05c45ca9 RK |
514 | } |
515 | ||
dd00cc48 | 516 | ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL); |
05c45ca9 RK |
517 | ret = -ENOMEM; |
518 | if (!ucb) | |
2b4d9d2b | 519 | goto out; |
05c45ca9 | 520 | |
f5ae587f | 521 | device_initialize(&ucb->dev); |
0c55445f TJ |
522 | ucb->dev.class = &ucb1x00_class; |
523 | ucb->dev.parent = &mcp->attached_device; | |
65f2e753 | 524 | dev_set_name(&ucb->dev, "ucb1x00"); |
05c45ca9 | 525 | |
a3364409 | 526 | raw_spin_lock_init(&ucb->irq_lock); |
05c45ca9 | 527 | spin_lock_init(&ucb->io_lock); |
cae15476 | 528 | mutex_init(&ucb->adc_mutex); |
05c45ca9 | 529 | |
65f2e753 | 530 | ucb->id = id; |
05c45ca9 | 531 | ucb->mcp = mcp; |
f5ae587f RK |
532 | |
533 | ret = device_add(&ucb->dev); | |
534 | if (ret) | |
535 | goto err_dev_add; | |
536 | ||
2b4d9d2b | 537 | ucb1x00_enable(ucb); |
05c45ca9 | 538 | ucb->irq = ucb1x00_detect_irq(ucb); |
2b4d9d2b | 539 | ucb1x00_disable(ucb); |
b53046cb | 540 | if (!ucb->irq) { |
f5ae587f | 541 | dev_err(&ucb->dev, "IRQ probe failed\n"); |
05c45ca9 | 542 | ret = -ENODEV; |
f5ae587f | 543 | goto err_no_irq; |
05c45ca9 RK |
544 | } |
545 | ||
9ca3dc80 | 546 | ucb->gpio.base = -1; |
a3364409 RK |
547 | irq_base = pdata ? pdata->irq_base : 0; |
548 | ucb->irq_base = irq_alloc_descs(-1, irq_base, 16, -1); | |
549 | if (ucb->irq_base < 0) { | |
550 | dev_err(&ucb->dev, "unable to allocate 16 irqs: %d\n", | |
551 | ucb->irq_base); | |
18fefda9 | 552 | ret = ucb->irq_base; |
a3364409 RK |
553 | goto err_irq_alloc; |
554 | } | |
555 | ||
556 | for (i = 0; i < 16; i++) { | |
557 | unsigned irq = ucb->irq_base + i; | |
558 | ||
559 | irq_set_chip_and_handler(irq, &ucb1x00_irqchip, handle_edge_irq); | |
560 | irq_set_chip_data(irq, ucb); | |
9bd09f34 | 561 | irq_clear_status_flags(irq, IRQ_NOREQUEST); |
a3364409 RK |
562 | } |
563 | ||
564 | irq_set_irq_type(ucb->irq, IRQ_TYPE_EDGE_RISING); | |
056c0acf | 565 | irq_set_chained_handler_and_data(ucb->irq, ucb1x00_irq, ucb); |
a3364409 | 566 | |
abe06082 | 567 | if (pdata && pdata->gpio_base) { |
9ca3dc80 | 568 | ucb->gpio.label = dev_name(&ucb->dev); |
58383c78 | 569 | ucb->gpio.parent = &ucb->dev; |
7655b2ac | 570 | ucb->gpio.owner = THIS_MODULE; |
abe06082 | 571 | ucb->gpio.base = pdata->gpio_base; |
9ca3dc80 TK |
572 | ucb->gpio.ngpio = 10; |
573 | ucb->gpio.set = ucb1x00_gpio_set; | |
574 | ucb->gpio.get = ucb1x00_gpio_get; | |
575 | ucb->gpio.direction_input = ucb1x00_gpio_direction_input; | |
576 | ucb->gpio.direction_output = ucb1x00_gpio_direction_output; | |
a3364409 | 577 | ucb->gpio.to_irq = ucb1x00_to_irq; |
7d94352e | 578 | ret = gpiochip_add_data(&ucb->gpio, ucb); |
9ca3dc80 | 579 | if (ret) |
f5ae587f | 580 | goto err_gpio_add; |
9ca3dc80 TK |
581 | } else |
582 | dev_info(&ucb->dev, "gpio_base not set so no gpiolib support"); | |
583 | ||
05c45ca9 RK |
584 | mcp_set_drvdata(mcp, ucb); |
585 | ||
33237616 RK |
586 | if (pdata) |
587 | device_set_wakeup_capable(&ucb->dev, pdata->can_wakeup); | |
588 | ||
05c45ca9 | 589 | INIT_LIST_HEAD(&ucb->devs); |
a621aaed | 590 | mutex_lock(&ucb1x00_mutex); |
65b539bb | 591 | list_add_tail(&ucb->node, &ucb1x00_devices); |
05c45ca9 RK |
592 | list_for_each_entry(drv, &ucb1x00_drivers, node) { |
593 | ucb1x00_add_dev(ucb, drv); | |
594 | } | |
a621aaed | 595 | mutex_unlock(&ucb1x00_mutex); |
9ca3dc80 | 596 | |
2f7510c6 | 597 | return ret; |
05c45ca9 | 598 | |
f5ae587f | 599 | err_gpio_add: |
a3364409 RK |
600 | irq_set_chained_handler(ucb->irq, NULL); |
601 | err_irq_alloc: | |
602 | if (ucb->irq_base > 0) | |
603 | irq_free_descs(ucb->irq_base, 16); | |
f5ae587f RK |
604 | err_no_irq: |
605 | device_del(&ucb->dev); | |
606 | err_dev_add: | |
607 | put_device(&ucb->dev); | |
05c45ca9 | 608 | out: |
2f7510c6 RK |
609 | if (pdata && pdata->reset) |
610 | pdata->reset(UCB_RST_PROBE_FAIL); | |
05c45ca9 RK |
611 | return ret; |
612 | } | |
613 | ||
614 | static void ucb1x00_remove(struct mcp *mcp) | |
615 | { | |
2f7510c6 | 616 | struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
05c45ca9 RK |
617 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); |
618 | struct list_head *l, *n; | |
619 | ||
a621aaed | 620 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
621 | list_del(&ucb->node); |
622 | list_for_each_safe(l, n, &ucb->devs) { | |
623 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node); | |
624 | ucb1x00_remove_dev(dev); | |
625 | } | |
a621aaed | 626 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 | 627 | |
88d5e520 | 628 | if (ucb->gpio.base != -1) |
629 | gpiochip_remove(&ucb->gpio); | |
9ca3dc80 | 630 | |
a3364409 RK |
631 | irq_set_chained_handler(ucb->irq, NULL); |
632 | irq_free_descs(ucb->irq_base, 16); | |
0c55445f | 633 | device_unregister(&ucb->dev); |
2f7510c6 RK |
634 | |
635 | if (pdata && pdata->reset) | |
636 | pdata->reset(UCB_RST_REMOVE); | |
05c45ca9 RK |
637 | } |
638 | ||
05c45ca9 RK |
639 | int ucb1x00_register_driver(struct ucb1x00_driver *drv) |
640 | { | |
641 | struct ucb1x00 *ucb; | |
642 | ||
643 | INIT_LIST_HEAD(&drv->devs); | |
a621aaed | 644 | mutex_lock(&ucb1x00_mutex); |
65b539bb | 645 | list_add_tail(&drv->node, &ucb1x00_drivers); |
05c45ca9 RK |
646 | list_for_each_entry(ucb, &ucb1x00_devices, node) { |
647 | ucb1x00_add_dev(ucb, drv); | |
648 | } | |
a621aaed | 649 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
650 | return 0; |
651 | } | |
652 | ||
653 | void ucb1x00_unregister_driver(struct ucb1x00_driver *drv) | |
654 | { | |
655 | struct list_head *n, *l; | |
656 | ||
a621aaed | 657 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
658 | list_del(&drv->node); |
659 | list_for_each_safe(l, n, &drv->devs) { | |
660 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node); | |
661 | ucb1x00_remove_dev(dev); | |
662 | } | |
a621aaed | 663 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
664 | } |
665 | ||
9924713a | 666 | #ifdef CONFIG_PM_SLEEP |
5a09b712 | 667 | static int ucb1x00_suspend(struct device *dev) |
05c45ca9 | 668 | { |
334a41ce | 669 | struct ucb1x00_plat_data *pdata = dev_get_platdata(dev); |
5a09b712 RK |
670 | struct ucb1x00 *ucb = dev_get_drvdata(dev); |
671 | struct ucb1x00_dev *udev; | |
05c45ca9 | 672 | |
a621aaed | 673 | mutex_lock(&ucb1x00_mutex); |
5a09b712 RK |
674 | list_for_each_entry(udev, &ucb->devs, dev_node) { |
675 | if (udev->drv->suspend) | |
676 | udev->drv->suspend(udev); | |
05c45ca9 | 677 | } |
a621aaed | 678 | mutex_unlock(&ucb1x00_mutex); |
33237616 RK |
679 | |
680 | if (ucb->irq_wake) { | |
681 | unsigned long flags; | |
682 | ||
683 | raw_spin_lock_irqsave(&ucb->irq_lock, flags); | |
684 | ucb1x00_enable(ucb); | |
685 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & | |
686 | ucb->irq_wake); | |
687 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & | |
688 | ucb->irq_wake); | |
689 | ucb1x00_disable(ucb); | |
690 | raw_spin_unlock_irqrestore(&ucb->irq_lock, flags); | |
691 | ||
692 | enable_irq_wake(ucb->irq); | |
693 | } else if (pdata && pdata->reset) | |
694 | pdata->reset(UCB_RST_SUSPEND); | |
695 | ||
05c45ca9 RK |
696 | return 0; |
697 | } | |
698 | ||
5a09b712 | 699 | static int ucb1x00_resume(struct device *dev) |
05c45ca9 | 700 | { |
334a41ce | 701 | struct ucb1x00_plat_data *pdata = dev_get_platdata(dev); |
5a09b712 RK |
702 | struct ucb1x00 *ucb = dev_get_drvdata(dev); |
703 | struct ucb1x00_dev *udev; | |
05c45ca9 | 704 | |
33237616 RK |
705 | if (!ucb->irq_wake && pdata && pdata->reset) |
706 | pdata->reset(UCB_RST_RESUME); | |
707 | ||
ed442b67 | 708 | ucb1x00_enable(ucb); |
2e95e51e | 709 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
9ca3dc80 | 710 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
33237616 RK |
711 | |
712 | if (ucb->irq_wake) { | |
713 | unsigned long flags; | |
714 | ||
715 | raw_spin_lock_irqsave(&ucb->irq_lock, flags); | |
716 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & | |
717 | ucb->irq_mask); | |
718 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & | |
719 | ucb->irq_mask); | |
720 | raw_spin_unlock_irqrestore(&ucb->irq_lock, flags); | |
721 | ||
722 | disable_irq_wake(ucb->irq); | |
723 | } | |
ed442b67 | 724 | ucb1x00_disable(ucb); |
33237616 | 725 | |
a621aaed | 726 | mutex_lock(&ucb1x00_mutex); |
5a09b712 RK |
727 | list_for_each_entry(udev, &ucb->devs, dev_node) { |
728 | if (udev->drv->resume) | |
729 | udev->drv->resume(udev); | |
05c45ca9 | 730 | } |
a621aaed | 731 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
732 | return 0; |
733 | } | |
9924713a | 734 | #endif |
05c45ca9 | 735 | |
507c133b | 736 | static SIMPLE_DEV_PM_OPS(ucb1x00_pm_ops, ucb1x00_suspend, ucb1x00_resume); |
5a09b712 | 737 | |
05c45ca9 RK |
738 | static struct mcp_driver ucb1x00_driver = { |
739 | .drv = { | |
740 | .name = "ucb1x00", | |
ddb1e04a | 741 | .owner = THIS_MODULE, |
5a09b712 | 742 | .pm = &ucb1x00_pm_ops, |
05c45ca9 RK |
743 | }, |
744 | .probe = ucb1x00_probe, | |
745 | .remove = ucb1x00_remove, | |
05c45ca9 RK |
746 | }; |
747 | ||
748 | static int __init ucb1x00_init(void) | |
749 | { | |
750 | int ret = class_register(&ucb1x00_class); | |
751 | if (ret == 0) { | |
752 | ret = mcp_driver_register(&ucb1x00_driver); | |
753 | if (ret) | |
754 | class_unregister(&ucb1x00_class); | |
755 | } | |
756 | return ret; | |
757 | } | |
758 | ||
759 | static void __exit ucb1x00_exit(void) | |
760 | { | |
761 | mcp_driver_unregister(&ucb1x00_driver); | |
762 | class_unregister(&ucb1x00_class); | |
763 | } | |
764 | ||
765 | module_init(ucb1x00_init); | |
766 | module_exit(ucb1x00_exit); | |
767 | ||
05c45ca9 RK |
768 | EXPORT_SYMBOL(ucb1x00_io_set_dir); |
769 | EXPORT_SYMBOL(ucb1x00_io_write); | |
770 | EXPORT_SYMBOL(ucb1x00_io_read); | |
771 | ||
772 | EXPORT_SYMBOL(ucb1x00_adc_enable); | |
773 | EXPORT_SYMBOL(ucb1x00_adc_read); | |
774 | EXPORT_SYMBOL(ucb1x00_adc_disable); | |
775 | ||
05c45ca9 RK |
776 | EXPORT_SYMBOL(ucb1x00_register_driver); |
777 | EXPORT_SYMBOL(ucb1x00_unregister_driver); | |
778 | ||
ddb1e04a | 779 | MODULE_ALIAS("mcp:ucb1x00"); |
05c45ca9 RK |
780 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); |
781 | MODULE_DESCRIPTION("UCB1x00 core driver"); | |
782 | MODULE_LICENSE("GPL"); |