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05c45ca9 RK |
1 | /* |
2 | * linux/drivers/mfd/ucb1x00-core.c | |
3 | * | |
4 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | * | |
10 | * The UCB1x00 core driver provides basic services for handling IO, | |
11 | * the ADC, interrupts, and accessing registers. It is designed | |
12 | * such that everything goes through this layer, thereby providing | |
13 | * a consistent locking methodology, as well as allowing the drivers | |
14 | * to be used on other non-MCP-enabled hardware platforms. | |
15 | * | |
16 | * Note that all locks are private to this file. Nothing else may | |
17 | * touch them. | |
18 | */ | |
05c45ca9 RK |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
d43c36dc | 21 | #include <linux/sched.h> |
05c45ca9 RK |
22 | #include <linux/slab.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/device.h> | |
a621aaed | 27 | #include <linux/mutex.h> |
c8602edf | 28 | #include <linux/mfd/ucb1x00.h> |
9ca3dc80 | 29 | #include <linux/gpio.h> |
05c45ca9 | 30 | |
a621aaed | 31 | static DEFINE_MUTEX(ucb1x00_mutex); |
05c45ca9 RK |
32 | static LIST_HEAD(ucb1x00_drivers); |
33 | static LIST_HEAD(ucb1x00_devices); | |
34 | ||
35 | /** | |
36 | * ucb1x00_io_set_dir - set IO direction | |
37 | * @ucb: UCB1x00 structure describing chip | |
38 | * @in: bitfield of IO pins to be set as inputs | |
39 | * @out: bitfield of IO pins to be set as outputs | |
40 | * | |
41 | * Set the IO direction of the ten general purpose IO pins on | |
42 | * the UCB1x00 chip. The @in bitfield has priority over the | |
43 | * @out bitfield, in that if you specify a pin as both input | |
44 | * and output, it will end up as an input. | |
45 | * | |
46 | * ucb1x00_enable must have been called to enable the comms | |
47 | * before using this function. | |
48 | * | |
49 | * This function takes a spinlock, disabling interrupts. | |
50 | */ | |
51 | void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out) | |
52 | { | |
53 | unsigned long flags; | |
54 | ||
55 | spin_lock_irqsave(&ucb->io_lock, flags); | |
56 | ucb->io_dir |= out; | |
57 | ucb->io_dir &= ~in; | |
58 | ||
59 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
60 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
61 | } | |
62 | ||
63 | /** | |
64 | * ucb1x00_io_write - set or clear IO outputs | |
65 | * @ucb: UCB1x00 structure describing chip | |
66 | * @set: bitfield of IO pins to set to logic '1' | |
67 | * @clear: bitfield of IO pins to set to logic '0' | |
68 | * | |
69 | * Set the IO output state of the specified IO pins. The value | |
70 | * is retained if the pins are subsequently configured as inputs. | |
71 | * The @clear bitfield has priority over the @set bitfield - | |
72 | * outputs will be cleared. | |
73 | * | |
74 | * ucb1x00_enable must have been called to enable the comms | |
75 | * before using this function. | |
76 | * | |
77 | * This function takes a spinlock, disabling interrupts. | |
78 | */ | |
79 | void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear) | |
80 | { | |
81 | unsigned long flags; | |
82 | ||
83 | spin_lock_irqsave(&ucb->io_lock, flags); | |
84 | ucb->io_out |= set; | |
85 | ucb->io_out &= ~clear; | |
86 | ||
87 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
88 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
89 | } | |
90 | ||
91 | /** | |
92 | * ucb1x00_io_read - read the current state of the IO pins | |
93 | * @ucb: UCB1x00 structure describing chip | |
94 | * | |
95 | * Return a bitfield describing the logic state of the ten | |
96 | * general purpose IO pins. | |
97 | * | |
98 | * ucb1x00_enable must have been called to enable the comms | |
99 | * before using this function. | |
100 | * | |
cae15476 | 101 | * This function does not take any mutexes or spinlocks. |
05c45ca9 RK |
102 | */ |
103 | unsigned int ucb1x00_io_read(struct ucb1x00 *ucb) | |
104 | { | |
105 | return ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
106 | } | |
107 | ||
9ca3dc80 TK |
108 | static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
109 | { | |
110 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
111 | unsigned long flags; | |
112 | ||
113 | spin_lock_irqsave(&ucb->io_lock, flags); | |
114 | if (value) | |
115 | ucb->io_out |= 1 << offset; | |
116 | else | |
117 | ucb->io_out &= ~(1 << offset); | |
118 | ||
119 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
120 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
121 | } | |
122 | ||
123 | static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset) | |
124 | { | |
125 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
126 | return ucb1x00_reg_read(ucb, UCB_IO_DATA) & (1 << offset); | |
127 | } | |
128 | ||
129 | static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
130 | { | |
131 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
132 | unsigned long flags; | |
133 | ||
134 | spin_lock_irqsave(&ucb->io_lock, flags); | |
135 | ucb->io_dir &= ~(1 << offset); | |
136 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
137 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
142 | static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset | |
143 | , int value) | |
144 | { | |
145 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
146 | unsigned long flags; | |
c23bb602 | 147 | unsigned old, mask = 1 << offset; |
9ca3dc80 TK |
148 | |
149 | spin_lock_irqsave(&ucb->io_lock, flags); | |
c23bb602 | 150 | old = ucb->io_out; |
9ca3dc80 | 151 | if (value) |
c23bb602 | 152 | ucb->io_out |= mask; |
9ca3dc80 | 153 | else |
c23bb602 RK |
154 | ucb->io_out &= ~mask; |
155 | ||
156 | if (old != ucb->io_out) | |
157 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
158 | ||
159 | if (!(ucb->io_dir & mask)) { | |
160 | ucb->io_dir |= mask; | |
161 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
162 | } | |
9ca3dc80 TK |
163 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
05c45ca9 RK |
168 | /* |
169 | * UCB1300 data sheet says we must: | |
170 | * 1. enable ADC => 5us (including reference startup time) | |
171 | * 2. select input => 51*tsibclk => 4.3us | |
172 | * 3. start conversion => 102*tsibclk => 8.5us | |
173 | * (tsibclk = 1/11981000) | |
174 | * Period between SIB 128-bit frames = 10.7us | |
175 | */ | |
176 | ||
177 | /** | |
178 | * ucb1x00_adc_enable - enable the ADC converter | |
179 | * @ucb: UCB1x00 structure describing chip | |
180 | * | |
181 | * Enable the ucb1x00 and ADC converter on the UCB1x00 for use. | |
182 | * Any code wishing to use the ADC converter must call this | |
183 | * function prior to using it. | |
184 | * | |
cae15476 | 185 | * This function takes the ADC mutex to prevent two or more |
05c45ca9 RK |
186 | * concurrent uses, and therefore may sleep. As a result, it |
187 | * can only be called from process context, not interrupt | |
188 | * context. | |
189 | * | |
190 | * You should release the ADC as soon as possible using | |
191 | * ucb1x00_adc_disable. | |
192 | */ | |
193 | void ucb1x00_adc_enable(struct ucb1x00 *ucb) | |
194 | { | |
cae15476 | 195 | mutex_lock(&ucb->adc_mutex); |
05c45ca9 RK |
196 | |
197 | ucb->adc_cr |= UCB_ADC_ENA; | |
198 | ||
199 | ucb1x00_enable(ucb); | |
200 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
201 | } | |
202 | ||
203 | /** | |
204 | * ucb1x00_adc_read - read the specified ADC channel | |
205 | * @ucb: UCB1x00 structure describing chip | |
206 | * @adc_channel: ADC channel mask | |
207 | * @sync: wait for syncronisation pulse. | |
208 | * | |
209 | * Start an ADC conversion and wait for the result. Note that | |
210 | * synchronised ADC conversions (via the ADCSYNC pin) must wait | |
211 | * until the trigger is asserted and the conversion is finished. | |
212 | * | |
213 | * This function currently spins waiting for the conversion to | |
214 | * complete (2 frames max without sync). | |
215 | * | |
216 | * If called for a synchronised ADC conversion, it may sleep | |
cae15476 | 217 | * with the ADC mutex held. |
05c45ca9 RK |
218 | */ |
219 | unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync) | |
220 | { | |
221 | unsigned int val; | |
222 | ||
223 | if (sync) | |
224 | adc_channel |= UCB_ADC_SYNC_ENA; | |
225 | ||
226 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel); | |
227 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START); | |
228 | ||
229 | for (;;) { | |
230 | val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); | |
231 | if (val & UCB_ADC_DAT_VAL) | |
232 | break; | |
233 | /* yield to other processes */ | |
234 | set_current_state(TASK_INTERRUPTIBLE); | |
235 | schedule_timeout(1); | |
236 | } | |
237 | ||
238 | return UCB_ADC_DAT(val); | |
239 | } | |
240 | ||
241 | /** | |
242 | * ucb1x00_adc_disable - disable the ADC converter | |
243 | * @ucb: UCB1x00 structure describing chip | |
244 | * | |
cae15476 | 245 | * Disable the ADC converter and release the ADC mutex. |
05c45ca9 RK |
246 | */ |
247 | void ucb1x00_adc_disable(struct ucb1x00 *ucb) | |
248 | { | |
249 | ucb->adc_cr &= ~UCB_ADC_ENA; | |
250 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
251 | ucb1x00_disable(ucb); | |
252 | ||
cae15476 | 253 | mutex_unlock(&ucb->adc_mutex); |
05c45ca9 RK |
254 | } |
255 | ||
256 | /* | |
257 | * UCB1x00 Interrupt handling. | |
258 | * | |
259 | * The UCB1x00 can generate interrupts when the SIBCLK is stopped. | |
260 | * Since we need to read an internal register, we must re-enable | |
261 | * SIBCLK to talk to the chip. We leave the clock running until | |
262 | * we have finished processing all interrupts from the chip. | |
263 | */ | |
7d12e780 | 264 | static irqreturn_t ucb1x00_irq(int irqnr, void *devid) |
05c45ca9 RK |
265 | { |
266 | struct ucb1x00 *ucb = devid; | |
267 | struct ucb1x00_irq *irq; | |
268 | unsigned int isr, i; | |
269 | ||
270 | ucb1x00_enable(ucb); | |
271 | isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS); | |
272 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr); | |
273 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
274 | ||
275 | for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++) | |
276 | if (isr & 1 && irq->fn) | |
277 | irq->fn(i, irq->devid); | |
278 | ucb1x00_disable(ucb); | |
279 | ||
280 | return IRQ_HANDLED; | |
281 | } | |
282 | ||
283 | /** | |
284 | * ucb1x00_hook_irq - hook a UCB1x00 interrupt | |
285 | * @ucb: UCB1x00 structure describing chip | |
286 | * @idx: interrupt index | |
287 | * @fn: function to call when interrupt is triggered | |
288 | * @devid: device id to pass to interrupt handler | |
289 | * | |
290 | * Hook the specified interrupt. You can only register one handler | |
291 | * for each interrupt source. The interrupt source is not enabled | |
292 | * by this function; use ucb1x00_enable_irq instead. | |
293 | * | |
294 | * Interrupt handlers will be called with other interrupts enabled. | |
295 | * | |
296 | * Returns zero on success, or one of the following errors: | |
297 | * -EINVAL if the interrupt index is invalid | |
298 | * -EBUSY if the interrupt has already been hooked | |
299 | */ | |
300 | int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid) | |
301 | { | |
302 | struct ucb1x00_irq *irq; | |
303 | int ret = -EINVAL; | |
304 | ||
305 | if (idx < 16) { | |
306 | irq = ucb->irq_handler + idx; | |
307 | ret = -EBUSY; | |
308 | ||
309 | spin_lock_irq(&ucb->lock); | |
310 | if (irq->fn == NULL) { | |
311 | irq->devid = devid; | |
312 | irq->fn = fn; | |
313 | ret = 0; | |
314 | } | |
315 | spin_unlock_irq(&ucb->lock); | |
316 | } | |
317 | return ret; | |
318 | } | |
319 | ||
320 | /** | |
321 | * ucb1x00_enable_irq - enable an UCB1x00 interrupt source | |
322 | * @ucb: UCB1x00 structure describing chip | |
323 | * @idx: interrupt index | |
324 | * @edges: interrupt edges to enable | |
325 | * | |
326 | * Enable the specified interrupt to trigger on %UCB_RISING, | |
327 | * %UCB_FALLING or both edges. The interrupt should have been | |
328 | * hooked by ucb1x00_hook_irq. | |
329 | */ | |
330 | void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
331 | { | |
332 | unsigned long flags; | |
333 | ||
334 | if (idx < 16) { | |
335 | spin_lock_irqsave(&ucb->lock, flags); | |
336 | ||
337 | ucb1x00_enable(ucb); | |
338 | if (edges & UCB_RISING) { | |
339 | ucb->irq_ris_enbl |= 1 << idx; | |
340 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
341 | } | |
342 | if (edges & UCB_FALLING) { | |
343 | ucb->irq_fal_enbl |= 1 << idx; | |
344 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
345 | } | |
346 | ucb1x00_disable(ucb); | |
347 | spin_unlock_irqrestore(&ucb->lock, flags); | |
348 | } | |
349 | } | |
350 | ||
351 | /** | |
352 | * ucb1x00_disable_irq - disable an UCB1x00 interrupt source | |
353 | * @ucb: UCB1x00 structure describing chip | |
354 | * @edges: interrupt edges to disable | |
355 | * | |
356 | * Disable the specified interrupt triggering on the specified | |
357 | * (%UCB_RISING, %UCB_FALLING or both) edges. | |
358 | */ | |
359 | void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
360 | { | |
361 | unsigned long flags; | |
362 | ||
363 | if (idx < 16) { | |
364 | spin_lock_irqsave(&ucb->lock, flags); | |
365 | ||
366 | ucb1x00_enable(ucb); | |
367 | if (edges & UCB_RISING) { | |
368 | ucb->irq_ris_enbl &= ~(1 << idx); | |
369 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
370 | } | |
371 | if (edges & UCB_FALLING) { | |
372 | ucb->irq_fal_enbl &= ~(1 << idx); | |
373 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
374 | } | |
375 | ucb1x00_disable(ucb); | |
376 | spin_unlock_irqrestore(&ucb->lock, flags); | |
377 | } | |
378 | } | |
379 | ||
380 | /** | |
381 | * ucb1x00_free_irq - disable and free the specified UCB1x00 interrupt | |
382 | * @ucb: UCB1x00 structure describing chip | |
383 | * @idx: interrupt index | |
384 | * @devid: device id. | |
385 | * | |
386 | * Disable the interrupt source and remove the handler. devid must | |
387 | * match the devid passed when hooking the interrupt. | |
388 | * | |
389 | * Returns zero on success, or one of the following errors: | |
390 | * -EINVAL if the interrupt index is invalid | |
391 | * -ENOENT if devid does not match | |
392 | */ | |
393 | int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid) | |
394 | { | |
395 | struct ucb1x00_irq *irq; | |
396 | int ret; | |
397 | ||
398 | if (idx >= 16) | |
399 | goto bad; | |
400 | ||
401 | irq = ucb->irq_handler + idx; | |
402 | ret = -ENOENT; | |
403 | ||
404 | spin_lock_irq(&ucb->lock); | |
405 | if (irq->devid == devid) { | |
406 | ucb->irq_ris_enbl &= ~(1 << idx); | |
407 | ucb->irq_fal_enbl &= ~(1 << idx); | |
408 | ||
409 | ucb1x00_enable(ucb); | |
410 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
411 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
412 | ucb1x00_disable(ucb); | |
413 | ||
414 | irq->fn = NULL; | |
415 | irq->devid = NULL; | |
416 | ret = 0; | |
417 | } | |
418 | spin_unlock_irq(&ucb->lock); | |
419 | return ret; | |
420 | ||
421 | bad: | |
422 | printk(KERN_ERR "Freeing bad UCB1x00 irq %d\n", idx); | |
423 | return -EINVAL; | |
424 | } | |
425 | ||
426 | static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv) | |
427 | { | |
428 | struct ucb1x00_dev *dev; | |
429 | int ret = -ENOMEM; | |
430 | ||
431 | dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL); | |
432 | if (dev) { | |
433 | dev->ucb = ucb; | |
434 | dev->drv = drv; | |
435 | ||
436 | ret = drv->add(dev); | |
437 | ||
438 | if (ret == 0) { | |
65b539bb RK |
439 | list_add_tail(&dev->dev_node, &ucb->devs); |
440 | list_add_tail(&dev->drv_node, &drv->devs); | |
05c45ca9 RK |
441 | } else { |
442 | kfree(dev); | |
443 | } | |
444 | } | |
445 | return ret; | |
446 | } | |
447 | ||
448 | static void ucb1x00_remove_dev(struct ucb1x00_dev *dev) | |
449 | { | |
450 | dev->drv->remove(dev); | |
451 | list_del(&dev->dev_node); | |
452 | list_del(&dev->drv_node); | |
453 | kfree(dev); | |
454 | } | |
455 | ||
456 | /* | |
457 | * Try to probe our interrupt, rather than relying on lots of | |
458 | * hard-coded machine dependencies. For reference, the expected | |
459 | * IRQ mappings are: | |
460 | * | |
461 | * Machine Default IRQ | |
462 | * adsbitsy IRQ_GPCIN4 | |
463 | * cerf IRQ_GPIO_UCB1200_IRQ | |
464 | * flexanet IRQ_GPIO_GUI | |
465 | * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ | |
466 | * graphicsclient ADS_EXT_IRQ(8) | |
467 | * graphicsmaster ADS_EXT_IRQ(8) | |
468 | * lart LART_IRQ_UCB1200 | |
469 | * omnimeter IRQ_GPIO23 | |
470 | * pfs168 IRQ_GPIO_UCB1300_IRQ | |
471 | * simpad IRQ_GPIO_UCB1300_IRQ | |
472 | * shannon SHANNON_IRQ_GPIO_IRQ_CODEC | |
473 | * yopy IRQ_GPIO_UCB1200_IRQ | |
474 | */ | |
475 | static int ucb1x00_detect_irq(struct ucb1x00 *ucb) | |
476 | { | |
477 | unsigned long mask; | |
478 | ||
479 | mask = probe_irq_on(); | |
cfc73656 IM |
480 | if (!mask) { |
481 | probe_irq_off(mask); | |
05c45ca9 | 482 | return NO_IRQ; |
cfc73656 | 483 | } |
05c45ca9 RK |
484 | |
485 | /* | |
486 | * Enable the ADC interrupt. | |
487 | */ | |
488 | ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); | |
489 | ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); | |
490 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
491 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
492 | ||
493 | /* | |
494 | * Cause an ADC interrupt. | |
495 | */ | |
496 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); | |
497 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); | |
498 | ||
499 | /* | |
500 | * Wait for the conversion to complete. | |
501 | */ | |
502 | while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0); | |
503 | ucb1x00_reg_write(ucb, UCB_ADC_CR, 0); | |
504 | ||
505 | /* | |
506 | * Disable and clear interrupt. | |
507 | */ | |
508 | ucb1x00_reg_write(ucb, UCB_IE_RIS, 0); | |
509 | ucb1x00_reg_write(ucb, UCB_IE_FAL, 0); | |
510 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
511 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
512 | ||
513 | /* | |
514 | * Read triggered interrupt. | |
515 | */ | |
516 | return probe_irq_off(mask); | |
517 | } | |
518 | ||
0c55445f | 519 | static void ucb1x00_release(struct device *dev) |
585f5457 NP |
520 | { |
521 | struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); | |
522 | kfree(ucb); | |
523 | } | |
524 | ||
525 | static struct class ucb1x00_class = { | |
526 | .name = "ucb1x00", | |
0c55445f | 527 | .dev_release = ucb1x00_release, |
585f5457 NP |
528 | }; |
529 | ||
05c45ca9 RK |
530 | static int ucb1x00_probe(struct mcp *mcp) |
531 | { | |
2f7510c6 | 532 | struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
05c45ca9 | 533 | struct ucb1x00_driver *drv; |
2f7510c6 | 534 | struct ucb1x00 *ucb; |
05c45ca9 RK |
535 | unsigned int id; |
536 | int ret = -ENODEV; | |
9ca3dc80 | 537 | int temp; |
05c45ca9 | 538 | |
2f7510c6 RK |
539 | /* Tell the platform to deassert the UCB1x00 reset */ |
540 | if (pdata && pdata->reset) | |
541 | pdata->reset(UCB_RST_PROBE); | |
542 | ||
05c45ca9 RK |
543 | mcp_enable(mcp); |
544 | id = mcp_reg_read(mcp, UCB_ID); | |
545 | ||
65f2e753 RK |
546 | if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) { |
547 | printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id); | |
05c45ca9 RK |
548 | goto err_disable; |
549 | } | |
550 | ||
dd00cc48 | 551 | ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL); |
05c45ca9 RK |
552 | ret = -ENOMEM; |
553 | if (!ucb) | |
554 | goto err_disable; | |
555 | ||
f5ae587f | 556 | device_initialize(&ucb->dev); |
0c55445f TJ |
557 | ucb->dev.class = &ucb1x00_class; |
558 | ucb->dev.parent = &mcp->attached_device; | |
65f2e753 | 559 | dev_set_name(&ucb->dev, "ucb1x00"); |
05c45ca9 RK |
560 | |
561 | spin_lock_init(&ucb->lock); | |
562 | spin_lock_init(&ucb->io_lock); | |
cae15476 | 563 | mutex_init(&ucb->adc_mutex); |
05c45ca9 | 564 | |
65f2e753 | 565 | ucb->id = id; |
05c45ca9 | 566 | ucb->mcp = mcp; |
f5ae587f RK |
567 | |
568 | ret = device_add(&ucb->dev); | |
569 | if (ret) | |
570 | goto err_dev_add; | |
571 | ||
05c45ca9 RK |
572 | ucb->irq = ucb1x00_detect_irq(ucb); |
573 | if (ucb->irq == NO_IRQ) { | |
f5ae587f | 574 | dev_err(&ucb->dev, "IRQ probe failed\n"); |
05c45ca9 | 575 | ret = -ENODEV; |
f5ae587f | 576 | goto err_no_irq; |
05c45ca9 RK |
577 | } |
578 | ||
9ca3dc80 | 579 | ucb->gpio.base = -1; |
abe06082 | 580 | if (pdata && pdata->gpio_base) { |
9ca3dc80 | 581 | ucb->gpio.label = dev_name(&ucb->dev); |
7655b2ac RK |
582 | ucb->gpio.dev = &ucb->dev; |
583 | ucb->gpio.owner = THIS_MODULE; | |
abe06082 | 584 | ucb->gpio.base = pdata->gpio_base; |
9ca3dc80 TK |
585 | ucb->gpio.ngpio = 10; |
586 | ucb->gpio.set = ucb1x00_gpio_set; | |
587 | ucb->gpio.get = ucb1x00_gpio_get; | |
588 | ucb->gpio.direction_input = ucb1x00_gpio_direction_input; | |
589 | ucb->gpio.direction_output = ucb1x00_gpio_direction_output; | |
590 | ret = gpiochip_add(&ucb->gpio); | |
591 | if (ret) | |
f5ae587f | 592 | goto err_gpio_add; |
9ca3dc80 TK |
593 | } else |
594 | dev_info(&ucb->dev, "gpio_base not set so no gpiolib support"); | |
595 | ||
dace1453 | 596 | ret = request_irq(ucb->irq, ucb1x00_irq, IRQF_TRIGGER_RISING, |
65f2e753 | 597 | "UCB1x00", ucb); |
05c45ca9 | 598 | if (ret) { |
f5ae587f | 599 | dev_err(&ucb->dev, "ucb1x00: unable to grab irq%d: %d\n", |
65f2e753 | 600 | ucb->irq, ret); |
f5ae587f | 601 | goto err_irq; |
05c45ca9 RK |
602 | } |
603 | ||
05c45ca9 RK |
604 | mcp_set_drvdata(mcp, ucb); |
605 | ||
05c45ca9 | 606 | INIT_LIST_HEAD(&ucb->devs); |
a621aaed | 607 | mutex_lock(&ucb1x00_mutex); |
65b539bb | 608 | list_add_tail(&ucb->node, &ucb1x00_devices); |
05c45ca9 RK |
609 | list_for_each_entry(drv, &ucb1x00_drivers, node) { |
610 | ucb1x00_add_dev(ucb, drv); | |
611 | } | |
a621aaed | 612 | mutex_unlock(&ucb1x00_mutex); |
9ca3dc80 | 613 | |
2f7510c6 | 614 | return ret; |
05c45ca9 RK |
615 | |
616 | err_irq: | |
9ca3dc80 TK |
617 | if (ucb->gpio.base != -1) |
618 | temp = gpiochip_remove(&ucb->gpio); | |
f5ae587f RK |
619 | err_gpio_add: |
620 | err_no_irq: | |
621 | device_del(&ucb->dev); | |
622 | err_dev_add: | |
623 | put_device(&ucb->dev); | |
05c45ca9 RK |
624 | err_disable: |
625 | mcp_disable(mcp); | |
626 | out: | |
2f7510c6 RK |
627 | if (pdata && pdata->reset) |
628 | pdata->reset(UCB_RST_PROBE_FAIL); | |
05c45ca9 RK |
629 | return ret; |
630 | } | |
631 | ||
632 | static void ucb1x00_remove(struct mcp *mcp) | |
633 | { | |
2f7510c6 | 634 | struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
05c45ca9 RK |
635 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); |
636 | struct list_head *l, *n; | |
9ca3dc80 | 637 | int ret; |
05c45ca9 | 638 | |
a621aaed | 639 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
640 | list_del(&ucb->node); |
641 | list_for_each_safe(l, n, &ucb->devs) { | |
642 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node); | |
643 | ucb1x00_remove_dev(dev); | |
644 | } | |
a621aaed | 645 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 | 646 | |
9ca3dc80 TK |
647 | if (ucb->gpio.base != -1) { |
648 | ret = gpiochip_remove(&ucb->gpio); | |
649 | if (ret) | |
650 | dev_err(&ucb->dev, "Can't remove gpio chip: %d\n", ret); | |
651 | } | |
652 | ||
05c45ca9 | 653 | free_irq(ucb->irq, ucb); |
0c55445f | 654 | device_unregister(&ucb->dev); |
2f7510c6 RK |
655 | |
656 | if (pdata && pdata->reset) | |
657 | pdata->reset(UCB_RST_REMOVE); | |
05c45ca9 RK |
658 | } |
659 | ||
05c45ca9 RK |
660 | int ucb1x00_register_driver(struct ucb1x00_driver *drv) |
661 | { | |
662 | struct ucb1x00 *ucb; | |
663 | ||
664 | INIT_LIST_HEAD(&drv->devs); | |
a621aaed | 665 | mutex_lock(&ucb1x00_mutex); |
65b539bb | 666 | list_add_tail(&drv->node, &ucb1x00_drivers); |
05c45ca9 RK |
667 | list_for_each_entry(ucb, &ucb1x00_devices, node) { |
668 | ucb1x00_add_dev(ucb, drv); | |
669 | } | |
a621aaed | 670 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
671 | return 0; |
672 | } | |
673 | ||
674 | void ucb1x00_unregister_driver(struct ucb1x00_driver *drv) | |
675 | { | |
676 | struct list_head *n, *l; | |
677 | ||
a621aaed | 678 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
679 | list_del(&drv->node); |
680 | list_for_each_safe(l, n, &drv->devs) { | |
681 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node); | |
682 | ucb1x00_remove_dev(dev); | |
683 | } | |
a621aaed | 684 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
685 | } |
686 | ||
687 | static int ucb1x00_suspend(struct mcp *mcp, pm_message_t state) | |
688 | { | |
689 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
690 | struct ucb1x00_dev *dev; | |
691 | ||
a621aaed | 692 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
693 | list_for_each_entry(dev, &ucb->devs, dev_node) { |
694 | if (dev->drv->suspend) | |
695 | dev->drv->suspend(dev, state); | |
696 | } | |
a621aaed | 697 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
698 | return 0; |
699 | } | |
700 | ||
701 | static int ucb1x00_resume(struct mcp *mcp) | |
702 | { | |
703 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
704 | struct ucb1x00_dev *dev; | |
705 | ||
2e95e51e | 706 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
9ca3dc80 | 707 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
a621aaed | 708 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
709 | list_for_each_entry(dev, &ucb->devs, dev_node) { |
710 | if (dev->drv->resume) | |
711 | dev->drv->resume(dev); | |
712 | } | |
a621aaed | 713 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
714 | return 0; |
715 | } | |
716 | ||
717 | static struct mcp_driver ucb1x00_driver = { | |
718 | .drv = { | |
719 | .name = "ucb1x00", | |
ddb1e04a | 720 | .owner = THIS_MODULE, |
05c45ca9 RK |
721 | }, |
722 | .probe = ucb1x00_probe, | |
723 | .remove = ucb1x00_remove, | |
724 | .suspend = ucb1x00_suspend, | |
725 | .resume = ucb1x00_resume, | |
726 | }; | |
727 | ||
728 | static int __init ucb1x00_init(void) | |
729 | { | |
730 | int ret = class_register(&ucb1x00_class); | |
731 | if (ret == 0) { | |
732 | ret = mcp_driver_register(&ucb1x00_driver); | |
733 | if (ret) | |
734 | class_unregister(&ucb1x00_class); | |
735 | } | |
736 | return ret; | |
737 | } | |
738 | ||
739 | static void __exit ucb1x00_exit(void) | |
740 | { | |
741 | mcp_driver_unregister(&ucb1x00_driver); | |
742 | class_unregister(&ucb1x00_class); | |
743 | } | |
744 | ||
745 | module_init(ucb1x00_init); | |
746 | module_exit(ucb1x00_exit); | |
747 | ||
05c45ca9 RK |
748 | EXPORT_SYMBOL(ucb1x00_io_set_dir); |
749 | EXPORT_SYMBOL(ucb1x00_io_write); | |
750 | EXPORT_SYMBOL(ucb1x00_io_read); | |
751 | ||
752 | EXPORT_SYMBOL(ucb1x00_adc_enable); | |
753 | EXPORT_SYMBOL(ucb1x00_adc_read); | |
754 | EXPORT_SYMBOL(ucb1x00_adc_disable); | |
755 | ||
756 | EXPORT_SYMBOL(ucb1x00_hook_irq); | |
757 | EXPORT_SYMBOL(ucb1x00_free_irq); | |
758 | EXPORT_SYMBOL(ucb1x00_enable_irq); | |
759 | EXPORT_SYMBOL(ucb1x00_disable_irq); | |
760 | ||
761 | EXPORT_SYMBOL(ucb1x00_register_driver); | |
762 | EXPORT_SYMBOL(ucb1x00_unregister_driver); | |
763 | ||
ddb1e04a | 764 | MODULE_ALIAS("mcp:ucb1x00"); |
05c45ca9 RK |
765 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); |
766 | MODULE_DESCRIPTION("UCB1x00 core driver"); | |
767 | MODULE_LICENSE("GPL"); |