[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / wm831x-irq.c

/*
 * wm831x-irq.c  --  Interrupt controller support for Wolfson WM831x PMICs
 *
 * Copyright 2009 Wolfson Microelectronics PLC.
 *
 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/interrupt.h>

#include <linux/mfd/wm831x/core.h>
#include <linux/mfd/wm831x/pdata.h>
#include <linux/mfd/wm831x/gpio.h>
#include <linux/mfd/wm831x/irq.h>

#include <linux/delay.h>

struct wm831x_irq_data {
	int primary;
	int reg;
	int mask;
};

static struct wm831x_irq_data wm831x_irqs[] = {
	[WM831X_IRQ_TEMP_THW] = {
		.primary = WM831X_TEMP_INT,
		.reg = 1,
		.mask = WM831X_TEMP_THW_EINT,
	},
	[WM831X_IRQ_GPIO_1] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP1_EINT,
	},
	[WM831X_IRQ_GPIO_2] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP2_EINT,
	},
	[WM831X_IRQ_GPIO_3] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP3_EINT,
	},
	[WM831X_IRQ_GPIO_4] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP4_EINT,
	},
	[WM831X_IRQ_GPIO_5] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP5_EINT,
	},
	[WM831X_IRQ_GPIO_6] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP6_EINT,
	},
	[WM831X_IRQ_GPIO_7] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP7_EINT,
	},
	[WM831X_IRQ_GPIO_8] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP8_EINT,
	},
	[WM831X_IRQ_GPIO_9] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP9_EINT,
	},
	[WM831X_IRQ_GPIO_10] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP10_EINT,
	},
	[WM831X_IRQ_GPIO_11] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP11_EINT,
	},
	[WM831X_IRQ_GPIO_12] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP12_EINT,
	},
	[WM831X_IRQ_GPIO_13] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP13_EINT,
	},
	[WM831X_IRQ_GPIO_14] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP14_EINT,
	},
	[WM831X_IRQ_GPIO_15] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP15_EINT,
	},
	[WM831X_IRQ_GPIO_16] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP16_EINT,
	},
	[WM831X_IRQ_ON] = {
		.primary = WM831X_ON_PIN_INT,
		.reg = 1,
		.mask = WM831X_ON_PIN_EINT,
	},
	[WM831X_IRQ_PPM_SYSLO] = {
		.primary = WM831X_PPM_INT,
		.reg = 1,
		.mask = WM831X_PPM_SYSLO_EINT,
	},
	[WM831X_IRQ_PPM_PWR_SRC] = {
		.primary = WM831X_PPM_INT,
		.reg = 1,
		.mask = WM831X_PPM_PWR_SRC_EINT,
	},
	[WM831X_IRQ_PPM_USB_CURR] = {
		.primary = WM831X_PPM_INT,
		.reg = 1,
		.mask = WM831X_PPM_USB_CURR_EINT,
	},
	[WM831X_IRQ_WDOG_TO] = {
		.primary = WM831X_WDOG_INT,
		.reg = 1,
		.mask = WM831X_WDOG_TO_EINT,
	},
	[WM831X_IRQ_RTC_PER] = {
		.primary = WM831X_RTC_INT,
		.reg = 1,
		.mask = WM831X_RTC_PER_EINT,
	},
	[WM831X_IRQ_RTC_ALM] = {
		.primary = WM831X_RTC_INT,
		.reg = 1,
		.mask = WM831X_RTC_ALM_EINT,
	},
	[WM831X_IRQ_CHG_BATT_HOT] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_BATT_HOT_EINT,
	},
	[WM831X_IRQ_CHG_BATT_COLD] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_BATT_COLD_EINT,
	},
	[WM831X_IRQ_CHG_BATT_FAIL] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_BATT_FAIL_EINT,
	},
	[WM831X_IRQ_CHG_OV] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_OV_EINT,
	},
	[WM831X_IRQ_CHG_END] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_END_EINT,
	},
	[WM831X_IRQ_CHG_TO] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_TO_EINT,
	},
	[WM831X_IRQ_CHG_MODE] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_MODE_EINT,
	},
	[WM831X_IRQ_CHG_START] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_START_EINT,
	},
	[WM831X_IRQ_TCHDATA] = {
		.primary = WM831X_TCHDATA_INT,
		.reg = 1,
		.mask = WM831X_TCHDATA_EINT,
	},
	[WM831X_IRQ_TCHPD] = {
		.primary = WM831X_TCHPD_INT,
		.reg = 1,
		.mask = WM831X_TCHPD_EINT,
	},
	[WM831X_IRQ_AUXADC_DATA] = {
		.primary = WM831X_AUXADC_INT,
		.reg = 1,
		.mask = WM831X_AUXADC_DATA_EINT,
	},
	[WM831X_IRQ_AUXADC_DCOMP1] = {
		.primary = WM831X_AUXADC_INT,
		.reg = 1,
		.mask = WM831X_AUXADC_DCOMP1_EINT,
	},
	[WM831X_IRQ_AUXADC_DCOMP2] = {
		.primary = WM831X_AUXADC_INT,
		.reg = 1,
		.mask = WM831X_AUXADC_DCOMP2_EINT,
	},
	[WM831X_IRQ_AUXADC_DCOMP3] = {
		.primary = WM831X_AUXADC_INT,
		.reg = 1,
		.mask = WM831X_AUXADC_DCOMP3_EINT,
	},
	[WM831X_IRQ_AUXADC_DCOMP4] = {
		.primary = WM831X_AUXADC_INT,
		.reg = 1,
		.mask = WM831X_AUXADC_DCOMP4_EINT,
	},
	[WM831X_IRQ_CS1] = {
		.primary = WM831X_CS_INT,
		.reg = 2,
		.mask = WM831X_CS1_EINT,
	},
	[WM831X_IRQ_CS2] = {
		.primary = WM831X_CS_INT,
		.reg = 2,
		.mask = WM831X_CS2_EINT,
	},
	[WM831X_IRQ_HC_DC1] = {
		.primary = WM831X_HC_INT,
		.reg = 4,
		.mask = WM831X_HC_DC1_EINT,
	},
	[WM831X_IRQ_HC_DC2] = {
		.primary = WM831X_HC_INT,
		.reg = 4,
		.mask = WM831X_HC_DC2_EINT,
	},
	[WM831X_IRQ_UV_LDO1] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO1_EINT,
	},
	[WM831X_IRQ_UV_LDO2] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO2_EINT,
	},
	[WM831X_IRQ_UV_LDO3] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO3_EINT,
	},
	[WM831X_IRQ_UV_LDO4] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO4_EINT,
	},
	[WM831X_IRQ_UV_LDO5] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO5_EINT,
	},
	[WM831X_IRQ_UV_LDO6] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO6_EINT,
	},
	[WM831X_IRQ_UV_LDO7] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO7_EINT,
	},
	[WM831X_IRQ_UV_LDO8] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO8_EINT,
	},
	[WM831X_IRQ_UV_LDO9] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO9_EINT,
	},
	[WM831X_IRQ_UV_LDO10] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO10_EINT,
	},
	[WM831X_IRQ_UV_DC1] = {
		.primary = WM831X_UV_INT,
		.reg = 4,
		.mask = WM831X_UV_DC1_EINT,
	},
	[WM831X_IRQ_UV_DC2] = {
		.primary = WM831X_UV_INT,
		.reg = 4,
		.mask = WM831X_UV_DC2_EINT,
	},
	[WM831X_IRQ_UV_DC3] = {
		.primary = WM831X_UV_INT,
		.reg = 4,
		.mask = WM831X_UV_DC3_EINT,
	},
	[WM831X_IRQ_UV_DC4] = {
		.primary = WM831X_UV_INT,
		.reg = 4,
		.mask = WM831X_UV_DC4_EINT,
	},
};

static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
{
	return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
}

static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
							int irq)
{
	return &wm831x_irqs[irq - wm831x->irq_base];
}

static void wm831x_irq_lock(struct irq_data *data)
{
	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);

	mutex_lock(&wm831x->irq_lock);
}

static void wm831x_irq_sync_unlock(struct irq_data *data)
{
	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
	int i;

	for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) {
		if (wm831x->gpio_update[i]) {
			wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i,
					WM831X_GPN_INT_MODE | WM831X_GPN_POL,
					wm831x->gpio_update[i]);
			wm831x->gpio_update[i] = 0;
		}
	}

	for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
		/* If there's been a change in the mask write it back
		 * to the hardware. */
		if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
			dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
				WM831X_INTERRUPT_STATUS_1_MASK + i,
				wm831x->irq_masks_cur[i]);

			wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
			wm831x_reg_write(wm831x,
					 WM831X_INTERRUPT_STATUS_1_MASK + i,
					 wm831x->irq_masks_cur[i]);
		}
	}

	mutex_unlock(&wm831x->irq_lock);
}

static void wm831x_irq_enable(struct irq_data *data)
{
	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
	struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
							     data->irq);

	wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
}

static void wm831x_irq_disable(struct irq_data *data)
{
	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
	struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
							     data->irq);

	wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
}

static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
{
	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
	int irq;

	irq = data->irq - wm831x->irq_base;

	if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) {
		/* Ignore internal-only IRQs */
		if (irq >= 0 && irq < WM831X_NUM_IRQS)
			return 0;
		else
			return -EINVAL;
	}

	/* Rebase the IRQ into the GPIO range so we've got a sensible array
	 * index.
	 */
	irq -= WM831X_IRQ_GPIO_1;

	/* We set the high bit to flag that we need an update; don't
	 * do the update here as we can be called with the bus lock
	 * held.
	 */
	switch (type) {
	case IRQ_TYPE_EDGE_BOTH:
		wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_INT_MODE;
		wm831x->gpio_level[irq] = false;
		break;
	case IRQ_TYPE_EDGE_RISING:
		wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
		wm831x->gpio_level[irq] = false;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		wm831x->gpio_update[irq] = 0x10000;
		wm831x->gpio_level[irq] = false;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
		wm831x->gpio_level[irq] = true;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static struct irq_chip wm831x_irq_chip = {
	.name			= "wm831x",
	.irq_bus_lock		= wm831x_irq_lock,
	.irq_bus_sync_unlock	= wm831x_irq_sync_unlock,
	.irq_disable		= wm831x_irq_disable,
	.irq_enable		= wm831x_irq_enable,
	.irq_set_type		= wm831x_irq_set_type,
};

/* The processing of the primary interrupt occurs in a thread so that
 * we can interact with the device over I2C or SPI. */
static irqreturn_t wm831x_irq_thread(int irq, void *data)
{
	struct wm831x *wm831x = data;
	unsigned int i;
	int primary, status_addr, ret;
	int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
	int read[WM831X_NUM_IRQ_REGS] = { 0 };
	int *status;

	primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
	if (primary < 0) {
		dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
			primary);
		goto out;
	}

	/* The touch interrupts are visible in the primary register as
	 * an optimisation; open code this to avoid complicating the
	 * main handling loop and so we can also skip iterating the
	 * descriptors.
	 */
	if (primary & WM831X_TCHPD_INT)
		handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHPD);
	if (primary & WM831X_TCHDATA_INT)
		handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHDATA);
	primary &= ~(WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT);

	for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
		int offset = wm831x_irqs[i].reg - 1;

		if (!(primary & wm831x_irqs[i].primary))
			continue;

		status = &status_regs[offset];

		/* Hopefully there should only be one register to read
		 * each time otherwise we ought to do a block read. */
		if (!read[offset]) {
			status_addr = irq_data_to_status_reg(&wm831x_irqs[i]);

			*status = wm831x_reg_read(wm831x, status_addr);
			if (*status < 0) {
				dev_err(wm831x->dev,
					"Failed to read IRQ status: %d\n",
					*status);
				goto out;
			}

			read[offset] = 1;

			/* Ignore any bits that we don't think are masked */
			*status &= ~wm831x->irq_masks_cur[offset];

			/* Acknowledge now so we don't miss
			 * notifications while we handle.
			 */
			wm831x_reg_write(wm831x, status_addr, *status);
		}

		if (*status & wm831x_irqs[i].mask)
			handle_nested_irq(wm831x->irq_base + i);

		/* Simulate an edge triggered IRQ by polling the input
		 * status.  This is sucky but improves interoperability.
		 */
		if (primary == WM831X_GP_INT &&
		    wm831x->gpio_level[i - WM831X_IRQ_GPIO_1]) {
			ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
			while (ret & 1 << (i - WM831X_IRQ_GPIO_1)) {
				handle_nested_irq(wm831x->irq_base + i);
				ret = wm831x_reg_read(wm831x,
						      WM831X_GPIO_LEVEL);
			}
		}
	}

out:
	return IRQ_HANDLED;
}

int wm831x_irq_init(struct wm831x *wm831x, int irq)
{
	struct wm831x_pdata *pdata = wm831x->dev->platform_data;
	int i, cur_irq, ret;

	mutex_init(&wm831x->irq_lock);

	/* Mask the individual interrupt sources */
	for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
		wm831x->irq_masks_cur[i] = 0xffff;
		wm831x->irq_masks_cache[i] = 0xffff;
		wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
				 0xffff);
	}

	/* Try to dynamically allocate IRQs if no base is specified */
	if (!pdata || !pdata->irq_base)
		wm831x->irq_base = -1;
	else
		wm831x->irq_base = pdata->irq_base;

	wm831x->irq_base = irq_alloc_descs(wm831x->irq_base, 0,
					   WM831X_NUM_IRQS, 0);
	if (wm831x->irq_base < 0) {
		dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n",
			 wm831x->irq_base);
		wm831x->irq_base = 0;
		return 0;
	}

	if (pdata && pdata->irq_cmos)
		i = 0;
	else
		i = WM831X_IRQ_OD;

	wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
			WM831X_IRQ_OD, i);

	/* Try to flag /IRQ as a wake source; there are a number of
	 * unconditional wake sources in the PMIC so this isn't
	 * conditional but we don't actually care *too* much if it
	 * fails.
	 */
	ret = enable_irq_wake(irq);
	if (ret != 0) {
		dev_warn(wm831x->dev, "Can't enable IRQ as wake source: %d\n",
			 ret);
	}

	wm831x->irq = irq;

	/* Register them with genirq */
	for (cur_irq = wm831x->irq_base;
	     cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base;
	     cur_irq++) {
		irq_set_chip_data(cur_irq, wm831x);
		irq_set_chip_and_handler(cur_irq, &wm831x_irq_chip,
					 handle_edge_irq);
		irq_set_nested_thread(cur_irq, 1);

		/* ARM needs us to explicitly flag the IRQ as valid
		 * and will set them noprobe when we do so. */
#ifdef CONFIG_ARM
		set_irq_flags(cur_irq, IRQF_VALID);
#else
		irq_set_noprobe(cur_irq);
#endif
	}

	if (irq) {
		ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
					   IRQF_TRIGGER_LOW | IRQF_ONESHOT,
					   "wm831x", wm831x);
		if (ret != 0) {
			dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
				irq, ret);
			return ret;
		}
	} else {
		dev_warn(wm831x->dev,
			 "No interrupt specified - functionality limited\n");
	}

	/* Enable top level interrupts, we mask at secondary level */
	wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);

	return 0;
}

void wm831x_irq_exit(struct wm831x *wm831x)
{
	if (wm831x->irq)
		free_irq(wm831x->irq, wm831x);
}
Commit	Line	Data
7d4d0a3e MB	1	/*
	2	* wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs
	3	*
	4	* Copyright 2009 Wolfson Microelectronics PLC.
	5	*
	6	* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/i2c.h>
5fb4d38b	18	#include <linux/irq.h>
7d4d0a3e MB	19	#include <linux/mfd/core.h>
	20	#include <linux/interrupt.h>
	21
	22	#include <linux/mfd/wm831x/core.h>
	23	#include <linux/mfd/wm831x/pdata.h>
896060c7	24	#include <linux/mfd/wm831x/gpio.h>
7d4d0a3e MB	25	#include <linux/mfd/wm831x/irq.h>
	26
	27	#include <linux/delay.h>
	28
7d4d0a3e MB	29	struct wm831x_irq_data {
	30	int primary;
	31	int reg;
	32	int mask;
7d4d0a3e MB	33	};
	34
	35	static struct wm831x_irq_data wm831x_irqs[] = {
	36	[WM831X_IRQ_TEMP_THW] = {
	37	.primary = WM831X_TEMP_INT,
	38	.reg = 1,
	39	.mask = WM831X_TEMP_THW_EINT,
	40	},
	41	[WM831X_IRQ_GPIO_1] = {
	42	.primary = WM831X_GP_INT,
	43	.reg = 5,
	44	.mask = WM831X_GP1_EINT,
	45	},
	46	[WM831X_IRQ_GPIO_2] = {
	47	.primary = WM831X_GP_INT,
	48	.reg = 5,
	49	.mask = WM831X_GP2_EINT,
	50	},
	51	[WM831X_IRQ_GPIO_3] = {
	52	.primary = WM831X_GP_INT,
	53	.reg = 5,
	54	.mask = WM831X_GP3_EINT,
	55	},
	56	[WM831X_IRQ_GPIO_4] = {
	57	.primary = WM831X_GP_INT,
	58	.reg = 5,
	59	.mask = WM831X_GP4_EINT,
	60	},
	61	[WM831X_IRQ_GPIO_5] = {
	62	.primary = WM831X_GP_INT,
	63	.reg = 5,
	64	.mask = WM831X_GP5_EINT,
	65	},
	66	[WM831X_IRQ_GPIO_6] = {
	67	.primary = WM831X_GP_INT,
	68	.reg = 5,
	69	.mask = WM831X_GP6_EINT,
	70	},
	71	[WM831X_IRQ_GPIO_7] = {
	72	.primary = WM831X_GP_INT,
	73	.reg = 5,
	74	.mask = WM831X_GP7_EINT,
	75	},
	76	[WM831X_IRQ_GPIO_8] = {
	77	.primary = WM831X_GP_INT,
	78	.reg = 5,
	79	.mask = WM831X_GP8_EINT,
	80	},
	81	[WM831X_IRQ_GPIO_9] = {
	82	.primary = WM831X_GP_INT,
	83	.reg = 5,
	84	.mask = WM831X_GP9_EINT,
	85	},
	86	[WM831X_IRQ_GPIO_10] = {
	87	.primary = WM831X_GP_INT,
	88	.reg = 5,
	89	.mask = WM831X_GP10_EINT,
	90	},
	91	[WM831X_IRQ_GPIO_11] = {
	92	.primary = WM831X_GP_INT,
	93	.reg = 5,
	94	.mask = WM831X_GP11_EINT,
	95	},
	96	[WM831X_IRQ_GPIO_12] = {
97	.primary = WM831X_GP_INT,
98	.reg = 5,
99	.mask = WM831X_GP12_EINT,
100	},
101	[WM831X_IRQ_GPIO_13] = {
102	.primary = WM831X_GP_INT,
103	.reg = 5,
104	.mask = WM831X_GP13_EINT,
105	},
106	[WM831X_IRQ_GPIO_14] = {
107	.primary = WM831X_GP_INT,
108	.reg = 5,
109	.mask = WM831X_GP14_EINT,
110	},
111	[WM831X_IRQ_GPIO_15] = {
112	.primary = WM831X_GP_INT,
113	.reg = 5,
114	.mask = WM831X_GP15_EINT,
115	},
116	[WM831X_IRQ_GPIO_16] = {
117	.primary = WM831X_GP_INT,
118	.reg = 5,
119	.mask = WM831X_GP16_EINT,
120	},
121	[WM831X_IRQ_ON] = {
122	.primary = WM831X_ON_PIN_INT,
123	.reg = 1,
124	.mask = WM831X_ON_PIN_EINT,
125	},
126	[WM831X_IRQ_PPM_SYSLO] = {
127	.primary = WM831X_PPM_INT,
128	.reg = 1,
129	.mask = WM831X_PPM_SYSLO_EINT,
130	},
131	[WM831X_IRQ_PPM_PWR_SRC] = {
132	.primary = WM831X_PPM_INT,
133	.reg = 1,
134	.mask = WM831X_PPM_PWR_SRC_EINT,
135	},
136	[WM831X_IRQ_PPM_USB_CURR] = {
137	.primary = WM831X_PPM_INT,
138	.reg = 1,
139	.mask = WM831X_PPM_USB_CURR_EINT,
140	},
141	[WM831X_IRQ_WDOG_TO] = {
142	.primary = WM831X_WDOG_INT,
143	.reg = 1,
144	.mask = WM831X_WDOG_TO_EINT,
145	},
146	[WM831X_IRQ_RTC_PER] = {
147	.primary = WM831X_RTC_INT,
148	.reg = 1,
149	.mask = WM831X_RTC_PER_EINT,
150	},
151	[WM831X_IRQ_RTC_ALM] = {
152	.primary = WM831X_RTC_INT,
153	.reg = 1,
154	.mask = WM831X_RTC_ALM_EINT,
155	},
156	[WM831X_IRQ_CHG_BATT_HOT] = {
157	.primary = WM831X_CHG_INT,
158	.reg = 2,
159	.mask = WM831X_CHG_BATT_HOT_EINT,
160	},
161	[WM831X_IRQ_CHG_BATT_COLD] = {
162	.primary = WM831X_CHG_INT,
163	.reg = 2,
164	.mask = WM831X_CHG_BATT_COLD_EINT,
165	},
166	[WM831X_IRQ_CHG_BATT_FAIL] = {
167	.primary = WM831X_CHG_INT,
168	.reg = 2,
169	.mask = WM831X_CHG_BATT_FAIL_EINT,
170	},
171	[WM831X_IRQ_CHG_OV] = {
172	.primary = WM831X_CHG_INT,
173	.reg = 2,
174	.mask = WM831X_CHG_OV_EINT,
175	},
176	[WM831X_IRQ_CHG_END] = {
177	.primary = WM831X_CHG_INT,
178	.reg = 2,
179	.mask = WM831X_CHG_END_EINT,
180	},
181	[WM831X_IRQ_CHG_TO] = {
182	.primary = WM831X_CHG_INT,
183	.reg = 2,
184	.mask = WM831X_CHG_TO_EINT,
185	},
186	[WM831X_IRQ_CHG_MODE] = {
187	.primary = WM831X_CHG_INT,
188	.reg = 2,
189	.mask = WM831X_CHG_MODE_EINT,
190	},
191	[WM831X_IRQ_CHG_START] = {
192	.primary = WM831X_CHG_INT,
193	.reg = 2,
194	.mask = WM831X_CHG_START_EINT,
195	},
196	[WM831X_IRQ_TCHDATA] = {
197	.primary = WM831X_TCHDATA_INT,
198	.reg = 1,
199	.mask = WM831X_TCHDATA_EINT,
200	},
201	[WM831X_IRQ_TCHPD] = {
202	.primary = WM831X_TCHPD_INT,
203	.reg = 1,
204	.mask = WM831X_TCHPD_EINT,
205	},
206	[WM831X_IRQ_AUXADC_DATA] = {
207	.primary = WM831X_AUXADC_INT,
208	.reg = 1,
209	.mask = WM831X_AUXADC_DATA_EINT,
210	},
211	[WM831X_IRQ_AUXADC_DCOMP1] = {
212	.primary = WM831X_AUXADC_INT,
213	.reg = 1,
214	.mask = WM831X_AUXADC_DCOMP1_EINT,
215	},
216	[WM831X_IRQ_AUXADC_DCOMP2] = {
217	.primary = WM831X_AUXADC_INT,
218	.reg = 1,
219	.mask = WM831X_AUXADC_DCOMP2_EINT,
220	},
221	[WM831X_IRQ_AUXADC_DCOMP3] = {
222	.primary = WM831X_AUXADC_INT,
223	.reg = 1,
224	.mask = WM831X_AUXADC_DCOMP3_EINT,
225	},
226	[WM831X_IRQ_AUXADC_DCOMP4] = {
227	.primary = WM831X_AUXADC_INT,
228	.reg = 1,
229	.mask = WM831X_AUXADC_DCOMP4_EINT,
230	},
231	[WM831X_IRQ_CS1] = {
232	.primary = WM831X_CS_INT,
233	.reg = 2,
234	.mask = WM831X_CS1_EINT,
235	},
236	[WM831X_IRQ_CS2] = {
237	.primary = WM831X_CS_INT,
238	.reg = 2,
239	.mask = WM831X_CS2_EINT,
240	},
241	[WM831X_IRQ_HC_DC1] = {
242	.primary = WM831X_HC_INT,
243	.reg = 4,
244	.mask = WM831X_HC_DC1_EINT,
245	},
246	[WM831X_IRQ_HC_DC2] = {
247	.primary = WM831X_HC_INT,
248	.reg = 4,
249	.mask = WM831X_HC_DC2_EINT,
250	},
251	[WM831X_IRQ_UV_LDO1] = {
252	.primary = WM831X_UV_INT,
253	.reg = 3,
254	.mask = WM831X_UV_LDO1_EINT,
255	},
256	[WM831X_IRQ_UV_LDO2] = {
257	.primary = WM831X_UV_INT,
258	.reg = 3,
259	.mask = WM831X_UV_LDO2_EINT,
260	},
261	[WM831X_IRQ_UV_LDO3] = {
262	.primary = WM831X_UV_INT,
263	.reg = 3,
264	.mask = WM831X_UV_LDO3_EINT,
265	},
266	[WM831X_IRQ_UV_LDO4] = {
267	.primary = WM831X_UV_INT,
268	.reg = 3,
269	.mask = WM831X_UV_LDO4_EINT,
270	},
271	[WM831X_IRQ_UV_LDO5] = {
272	.primary = WM831X_UV_INT,
273	.reg = 3,
274	.mask = WM831X_UV_LDO5_EINT,
275	},
276	[WM831X_IRQ_UV_LDO6] = {
277	.primary = WM831X_UV_INT,
278	.reg = 3,
279	.mask = WM831X_UV_LDO6_EINT,
280	},
281	[WM831X_IRQ_UV_LDO7] = {
282	.primary = WM831X_UV_INT,
283	.reg = 3,
284	.mask = WM831X_UV_LDO7_EINT,
285	},
286	[WM831X_IRQ_UV_LDO8] = {
287	.primary = WM831X_UV_INT,
288	.reg = 3,
289	.mask = WM831X_UV_LDO8_EINT,
290	},
291	[WM831X_IRQ_UV_LDO9] = {
292	.primary = WM831X_UV_INT,
293	.reg = 3,
294	.mask = WM831X_UV_LDO9_EINT,
295	},
296	[WM831X_IRQ_UV_LDO10] = {
297	.primary = WM831X_UV_INT,
298	.reg = 3,
299	.mask = WM831X_UV_LDO10_EINT,
300	},
301	[WM831X_IRQ_UV_DC1] = {
302	.primary = WM831X_UV_INT,
303	.reg = 4,
304	.mask = WM831X_UV_DC1_EINT,
305	},
306	[WM831X_IRQ_UV_DC2] = {
307	.primary = WM831X_UV_INT,
308	.reg = 4,
309	.mask = WM831X_UV_DC2_EINT,
310	},
311	[WM831X_IRQ_UV_DC3] = {
312	.primary = WM831X_UV_INT,
313	.reg = 4,
314	.mask = WM831X_UV_DC3_EINT,
315	},
316	[WM831X_IRQ_UV_DC4] = {
317	.primary = WM831X_UV_INT,
318	.reg = 4,
319	.mask = WM831X_UV_DC4_EINT,
320	},
321	};
322
323	static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
324	{
325	return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
326	}
327
5fb4d38b MB	328	static inline struct wm831x_irq_data irq_to_wm831x_irq(struct wm831x wm831x,
5fb4d38b MB	329	int irq)
7d4d0a3e	330	{
5fb4d38b	331	return &wm831x_irqs[irq - wm831x->irq_base];
7d4d0a3e MB	332	}
7d4d0a3e MB	333
ba81cd39	334	static void wm831x_irq_lock(struct irq_data *data)
7d4d0a3e	335	{
25a947f8	336	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
7d4d0a3e	337
7d4d0a3e	338	mutex_lock(&wm831x->irq_lock);
7d4d0a3e	339	}
7d4d0a3e	340
ba81cd39	341	static void wm831x_irq_sync_unlock(struct irq_data *data)
7d4d0a3e	342	{
25a947f8	343	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
5fb4d38b MB	344	int i;
5fb4d38b MB	345
ca7a7182 MB	346	for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) {
	347	if (wm831x->gpio_update[i]) {
	348	wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i,
	349	WM831X_GPN_INT_MODE \| WM831X_GPN_POL,
	350	wm831x->gpio_update[i]);
	351	wm831x->gpio_update[i] = 0;
	352	}
	353	}
	354
5fb4d38b MB	355	for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
	356	/* If there's been a change in the mask write it back
	357	* to the hardware. */
	358	if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
f624effb MB	359	dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
	360	WM831X_INTERRUPT_STATUS_1_MASK + i,
	361	wm831x->irq_masks_cur[i]);
	362
5fb4d38b MB	363	wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
	364	wm831x_reg_write(wm831x,
	365	WM831X_INTERRUPT_STATUS_1_MASK + i,
	366	wm831x->irq_masks_cur[i]);
	367	}
7d4d0a3e MB	368	}
7d4d0a3e MB	369
7d4d0a3e	370	mutex_unlock(&wm831x->irq_lock);
7d4d0a3e	371	}
7d4d0a3e	372
f624effb	373	static void wm831x_irq_enable(struct irq_data *data)
7d4d0a3e	374	{
25a947f8	375	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
ba81cd39 MB	376	struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
ba81cd39 MB	377	data->irq);
7d4d0a3e	378
5fb4d38b	379	wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
7d4d0a3e	380	}
7d4d0a3e	381
f624effb	382	static void wm831x_irq_disable(struct irq_data *data)
7d4d0a3e	383	{
25a947f8	384	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
ba81cd39 MB	385	struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
ba81cd39 MB	386	data->irq);
5fb4d38b MB	387
5fb4d38b MB	388	wm831x->irq_masks_cur[irq_data->reg - 1] \|= irq_data->mask;
7d4d0a3e MB	389	}
7d4d0a3e MB	390
ba81cd39	391	static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
896060c7	392	{
25a947f8	393	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
ca7a7182	394	int irq;
896060c7	395
ba81cd39	396	irq = data->irq - wm831x->irq_base;
896060c7	397
c9d66d35 MB	398	if (irq < WM831X_IRQ_GPIO_1 \|\| irq > WM831X_IRQ_GPIO_11) {
	399	/* Ignore internal-only IRQs */
	400	if (irq >= 0 && irq < WM831X_NUM_IRQS)
	401	return 0;
	402	else
	403	return -EINVAL;
	404	}
896060c7	405
08256712 DP	406	/* Rebase the IRQ into the GPIO range so we've got a sensible array
	407	* index.
	408	*/
	409	irq -= WM831X_IRQ_GPIO_1;
	410
ca7a7182 MB	411	/* We set the high bit to flag that we need an update; don't
	412	* do the update here as we can be called with the bus lock
	413	* held.
	414	*/
896060c7 MB	415	switch (type) {
896060c7 MB	416	case IRQ_TYPE_EDGE_BOTH:
ca7a7182	417	wm831x->gpio_update[irq] = 0x10000 \| WM831X_GPN_INT_MODE;
7583a213	418	wm831x->gpio_level[irq] = false;
896060c7 MB	419	break;
896060c7 MB	420	case IRQ_TYPE_EDGE_RISING:
ca7a7182	421	wm831x->gpio_update[irq] = 0x10000 \| WM831X_GPN_POL;
7583a213	422	wm831x->gpio_level[irq] = false;
896060c7 MB	423	break;
896060c7 MB	424	case IRQ_TYPE_EDGE_FALLING:
ca7a7182	425	wm831x->gpio_update[irq] = 0x10000;
7583a213 MB	426	wm831x->gpio_level[irq] = false;
	427	break;
	428	case IRQ_TYPE_LEVEL_HIGH:
	429	wm831x->gpio_update[irq] = 0x10000 \| WM831X_GPN_POL;
	430	wm831x->gpio_level[irq] = true;
896060c7 MB	431	break;
	432	default:
	433	return -EINVAL;
	434	}
	435
ca7a7182	436	return 0;
896060c7 MB	437	}
896060c7 MB	438
5fb4d38b	439	static struct irq_chip wm831x_irq_chip = {
ba81cd39 MB	440	.name = "wm831x",
	441	.irq_bus_lock = wm831x_irq_lock,
	442	.irq_bus_sync_unlock = wm831x_irq_sync_unlock,
f624effb MB	443	.irq_disable = wm831x_irq_disable,
f624effb MB	444	.irq_enable = wm831x_irq_enable,
ba81cd39	445	.irq_set_type = wm831x_irq_set_type,
5fb4d38b MB	446	};
	447
	448	/* The processing of the primary interrupt occurs in a thread so that
	449	* we can interact with the device over I2C or SPI. */
	450	static irqreturn_t wm831x_irq_thread(int irq, void *data)
7d4d0a3e	451	{
5fb4d38b	452	struct wm831x *wm831x = data;
7d4d0a3e	453	unsigned int i;
7583a213	454	int primary, status_addr, ret;
5fb4d38b MB	455	int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
5fb4d38b MB	456	int read[WM831X_NUM_IRQ_REGS] = { 0 };
7d4d0a3e MB	457	int *status;
	458
	459	primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
	460	if (primary < 0) {
	461	dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
	462	primary);
	463	goto out;
	464	}
	465
8546bd4a MB	466	/* The touch interrupts are visible in the primary register as
	467	* an optimisation; open code this to avoid complicating the
	468	* main handling loop and so we can also skip iterating the
	469	* descriptors.
	470	*/
	471	if (primary & WM831X_TCHPD_INT)
	472	handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHPD);
	473	if (primary & WM831X_TCHDATA_INT)
	474	handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHDATA);
953c7d02	475	primary &= ~(WM831X_TCHDATA_EINT \| WM831X_TCHPD_EINT);
8546bd4a	476
7d4d0a3e MB	477	for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
	478	int offset = wm831x_irqs[i].reg - 1;
	479
	480	if (!(primary & wm831x_irqs[i].primary))
	481	continue;
	482
	483	status = &status_regs[offset];
	484
	485	/* Hopefully there should only be one register to read
	486	* each time otherwise we ought to do a block read. */
	487	if (!read[offset]) {
88c93977 MB	488	status_addr = irq_data_to_status_reg(&wm831x_irqs[i]);
	489
	490	*status = wm831x_reg_read(wm831x, status_addr);
7d4d0a3e MB	491	if (*status < 0) {
	492	dev_err(wm831x->dev,
	493	"Failed to read IRQ status: %d\n",
	494	*status);
5fb4d38b	495	goto out;
7d4d0a3e MB	496	}
7d4d0a3e MB	497
7d4d0a3e	498	read[offset] = 1;
88c93977 MB	499
	500	/* Ignore any bits that we don't think are masked */
	501	*status &= ~wm831x->irq_masks_cur[offset];
	502
	503	/* Acknowledge now so we don't miss
	504	* notifications while we handle.
	505	*/
	506	wm831x_reg_write(wm831x, status_addr, *status);
7d4d0a3e MB	507	}
7d4d0a3e MB	508
88c93977	509	if (*status & wm831x_irqs[i].mask)
5fb4d38b	510	handle_nested_irq(wm831x->irq_base + i);
7583a213 MB	511
	512	/* Simulate an edge triggered IRQ by polling the input
	513	* status. This is sucky but improves interoperability.
	514	*/
	515	if (primary == WM831X_GP_INT &&
	516	wm831x->gpio_level[i - WM831X_IRQ_GPIO_1]) {
	517	ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
	518	while (ret & 1 << (i - WM831X_IRQ_GPIO_1)) {
	519	handle_nested_irq(wm831x->irq_base + i);
	520	ret = wm831x_reg_read(wm831x,
	521	WM831X_GPIO_LEVEL);
	522	}
	523	}
7d4d0a3e MB	524	}
7d4d0a3e MB	525
7d4d0a3e	526	out:
7d4d0a3e MB	527	return IRQ_HANDLED;
	528	}
	529
	530	int wm831x_irq_init(struct wm831x *wm831x, int irq)
	531	{
5fb4d38b MB	532	struct wm831x_pdata *pdata = wm831x->dev->platform_data;
5fb4d38b MB	533	int i, cur_irq, ret;
7d4d0a3e	534
14f572fa MB	535	mutex_init(&wm831x->irq_lock);
14f572fa MB	536
0d7e0e39 MB	537	/* Mask the individual interrupt sources */
	538	for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
	539	wm831x->irq_masks_cur[i] = 0xffff;
	540	wm831x->irq_masks_cache[i] = 0xffff;
	541	wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
	542	0xffff);
	543	}
	544
5c05a8d1 MB	545	/* Try to dynamically allocate IRQs if no base is specified */
	546	if (!pdata \|\| !pdata->irq_base)
	547	wm831x->irq_base = -1;
	548	else
	549	wm831x->irq_base = pdata->irq_base;
	550
	551	wm831x->irq_base = irq_alloc_descs(wm831x->irq_base, 0,
	552	WM831X_NUM_IRQS, 0);
	553	if (wm831x->irq_base < 0) {
	554	dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n",
	555	wm831x->irq_base);
	556	wm831x->irq_base = 0;
5fb4d38b	557	return 0;
7d4d0a3e MB	558	}
7d4d0a3e MB	559
5c05a8d1	560	if (pdata && pdata->irq_cmos)
b103e0b3 MB	561	i = 0;
	562	else
	563	i = WM831X_IRQ_OD;
	564
	565	wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
	566	WM831X_IRQ_OD, i);
	567
180e4f5f MB	568	/* Try to flag /IRQ as a wake source; there are a number of
	569	* unconditional wake sources in the PMIC so this isn't
	570	* conditional but we don't actually care too much if it
	571	* fails.
	572	*/
	573	ret = enable_irq_wake(irq);
	574	if (ret != 0) {
	575	dev_warn(wm831x->dev, "Can't enable IRQ as wake source: %d\n",
	576	ret);
	577	}
	578
7d4d0a3e	579	wm831x->irq = irq;
7d4d0a3e	580
5fb4d38b MB	581	/* Register them with genirq */
	582	for (cur_irq = wm831x->irq_base;
	583	cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base;
	584	cur_irq++) {
d5bb1221 TG	585	irq_set_chip_data(cur_irq, wm831x);
d5bb1221 TG	586	irq_set_chip_and_handler(cur_irq, &wm831x_irq_chip,
5fb4d38b	587	handle_edge_irq);
d5bb1221	588	irq_set_nested_thread(cur_irq, 1);
5fb4d38b MB	589
	590	/* ARM needs us to explicitly flag the IRQ as valid
	591	* and will set them noprobe when we do so. */
	592	#ifdef CONFIG_ARM
	593	set_irq_flags(cur_irq, IRQF_VALID);
	594	#else
d5bb1221	595	irq_set_noprobe(cur_irq);
5fb4d38b MB	596	#endif
5fb4d38b MB	597	}
7d4d0a3e	598
bc86fcee MB	599	if (irq) {
	600	ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
	601	IRQF_TRIGGER_LOW \| IRQF_ONESHOT,
	602	"wm831x", wm831x);
	603	if (ret != 0) {
	604	dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
	605	irq, ret);
	606	return ret;
	607	}
	608	} else {
	609	dev_warn(wm831x->dev,
	610	"No interrupt specified - functionality limited\n");
7d4d0a3e MB	611	}
7d4d0a3e MB	612
5fb4d38b MB	613	/* Enable top level interrupts, we mask at secondary level */
	614	wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
	615
7d4d0a3e MB	616	return 0;
	617	}
	618
	619	void wm831x_irq_exit(struct wm831x *wm831x)
	620	{
	621	if (wm831x->irq)
	622	free_irq(wm831x->irq, wm831x);
	623	}