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c9fbf7e0 MB |
1 | /* |
2 | * wm8994-irq.c -- Interrupt controller support for Wolfson WM8994 | |
3 | * | |
4 | * Copyright 2010 Wolfson Microelectronics PLC. | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/mfd/core.h> | |
20 | #include <linux/interrupt.h> | |
8ab30691 | 21 | #include <linux/regmap.h> |
c9fbf7e0 MB |
22 | |
23 | #include <linux/mfd/wm8994/core.h> | |
24 | #include <linux/mfd/wm8994/registers.h> | |
25 | ||
26 | #include <linux/delay.h> | |
27 | ||
8ab30691 | 28 | static struct regmap_irq wm8994_irqs[] = { |
c9fbf7e0 | 29 | [WM8994_IRQ_TEMP_SHUT] = { |
8ab30691 | 30 | .reg_offset = 1, |
c9fbf7e0 MB |
31 | .mask = WM8994_TEMP_SHUT_EINT, |
32 | }, | |
33 | [WM8994_IRQ_MIC1_DET] = { | |
8ab30691 | 34 | .reg_offset = 1, |
c9fbf7e0 MB |
35 | .mask = WM8994_MIC1_DET_EINT, |
36 | }, | |
37 | [WM8994_IRQ_MIC1_SHRT] = { | |
8ab30691 | 38 | .reg_offset = 1, |
c9fbf7e0 MB |
39 | .mask = WM8994_MIC1_SHRT_EINT, |
40 | }, | |
41 | [WM8994_IRQ_MIC2_DET] = { | |
8ab30691 | 42 | .reg_offset = 1, |
c9fbf7e0 MB |
43 | .mask = WM8994_MIC2_DET_EINT, |
44 | }, | |
45 | [WM8994_IRQ_MIC2_SHRT] = { | |
8ab30691 | 46 | .reg_offset = 1, |
c9fbf7e0 MB |
47 | .mask = WM8994_MIC2_SHRT_EINT, |
48 | }, | |
49 | [WM8994_IRQ_FLL1_LOCK] = { | |
8ab30691 | 50 | .reg_offset = 1, |
c9fbf7e0 MB |
51 | .mask = WM8994_FLL1_LOCK_EINT, |
52 | }, | |
53 | [WM8994_IRQ_FLL2_LOCK] = { | |
8ab30691 | 54 | .reg_offset = 1, |
c9fbf7e0 MB |
55 | .mask = WM8994_FLL2_LOCK_EINT, |
56 | }, | |
57 | [WM8994_IRQ_SRC1_LOCK] = { | |
8ab30691 | 58 | .reg_offset = 1, |
c9fbf7e0 MB |
59 | .mask = WM8994_SRC1_LOCK_EINT, |
60 | }, | |
61 | [WM8994_IRQ_SRC2_LOCK] = { | |
8ab30691 | 62 | .reg_offset = 1, |
c9fbf7e0 MB |
63 | .mask = WM8994_SRC2_LOCK_EINT, |
64 | }, | |
65 | [WM8994_IRQ_AIF1DRC1_SIG_DET] = { | |
8ab30691 | 66 | .reg_offset = 1, |
c9fbf7e0 MB |
67 | .mask = WM8994_AIF1DRC1_SIG_DET, |
68 | }, | |
69 | [WM8994_IRQ_AIF1DRC2_SIG_DET] = { | |
8ab30691 | 70 | .reg_offset = 1, |
c9fbf7e0 MB |
71 | .mask = WM8994_AIF1DRC2_SIG_DET_EINT, |
72 | }, | |
73 | [WM8994_IRQ_AIF2DRC_SIG_DET] = { | |
8ab30691 | 74 | .reg_offset = 1, |
c9fbf7e0 MB |
75 | .mask = WM8994_AIF2DRC_SIG_DET_EINT, |
76 | }, | |
77 | [WM8994_IRQ_FIFOS_ERR] = { | |
8ab30691 | 78 | .reg_offset = 1, |
c9fbf7e0 MB |
79 | .mask = WM8994_FIFOS_ERR_EINT, |
80 | }, | |
81 | [WM8994_IRQ_WSEQ_DONE] = { | |
8ab30691 | 82 | .reg_offset = 1, |
c9fbf7e0 MB |
83 | .mask = WM8994_WSEQ_DONE_EINT, |
84 | }, | |
85 | [WM8994_IRQ_DCS_DONE] = { | |
8ab30691 | 86 | .reg_offset = 1, |
c9fbf7e0 MB |
87 | .mask = WM8994_DCS_DONE_EINT, |
88 | }, | |
89 | [WM8994_IRQ_TEMP_WARN] = { | |
8ab30691 | 90 | .reg_offset = 1, |
c9fbf7e0 MB |
91 | .mask = WM8994_TEMP_WARN_EINT, |
92 | }, | |
93 | [WM8994_IRQ_GPIO(1)] = { | |
c9fbf7e0 MB |
94 | .mask = WM8994_GP1_EINT, |
95 | }, | |
96 | [WM8994_IRQ_GPIO(2)] = { | |
c9fbf7e0 MB |
97 | .mask = WM8994_GP2_EINT, |
98 | }, | |
99 | [WM8994_IRQ_GPIO(3)] = { | |
c9fbf7e0 MB |
100 | .mask = WM8994_GP3_EINT, |
101 | }, | |
102 | [WM8994_IRQ_GPIO(4)] = { | |
c9fbf7e0 MB |
103 | .mask = WM8994_GP4_EINT, |
104 | }, | |
105 | [WM8994_IRQ_GPIO(5)] = { | |
c9fbf7e0 MB |
106 | .mask = WM8994_GP5_EINT, |
107 | }, | |
108 | [WM8994_IRQ_GPIO(6)] = { | |
c9fbf7e0 MB |
109 | .mask = WM8994_GP6_EINT, |
110 | }, | |
111 | [WM8994_IRQ_GPIO(7)] = { | |
c9fbf7e0 MB |
112 | .mask = WM8994_GP7_EINT, |
113 | }, | |
114 | [WM8994_IRQ_GPIO(8)] = { | |
c9fbf7e0 MB |
115 | .mask = WM8994_GP8_EINT, |
116 | }, | |
117 | [WM8994_IRQ_GPIO(9)] = { | |
c9fbf7e0 MB |
118 | .mask = WM8994_GP8_EINT, |
119 | }, | |
120 | [WM8994_IRQ_GPIO(10)] = { | |
c9fbf7e0 MB |
121 | .mask = WM8994_GP10_EINT, |
122 | }, | |
123 | [WM8994_IRQ_GPIO(11)] = { | |
c9fbf7e0 MB |
124 | .mask = WM8994_GP11_EINT, |
125 | }, | |
126 | }; | |
127 | ||
8ab30691 MB |
128 | static struct regmap_irq_chip wm8994_irq_chip = { |
129 | .name = "wm8994", | |
130 | .irqs = wm8994_irqs, | |
131 | .num_irqs = ARRAY_SIZE(wm8994_irqs), | |
c9fbf7e0 | 132 | |
8ab30691 MB |
133 | .num_regs = 2, |
134 | .status_base = WM8994_INTERRUPT_STATUS_1, | |
135 | .mask_base = WM8994_INTERRUPT_STATUS_1_MASK, | |
136 | .ack_base = WM8994_INTERRUPT_STATUS_1, | |
c9fbf7e0 MB |
137 | }; |
138 | ||
c9fbf7e0 MB |
139 | int wm8994_irq_init(struct wm8994 *wm8994) |
140 | { | |
8ab30691 | 141 | int ret; |
c9fbf7e0 MB |
142 | |
143 | if (!wm8994->irq) { | |
144 | dev_warn(wm8994->dev, | |
145 | "No interrupt specified, no interrupts\n"); | |
146 | wm8994->irq_base = 0; | |
147 | return 0; | |
148 | } | |
149 | ||
8ab30691 MB |
150 | ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq, |
151 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, | |
152 | wm8994->irq_base, &wm8994_irq_chip, | |
153 | &wm8994->irq_data); | |
c9fbf7e0 | 154 | if (ret != 0) { |
8ab30691 | 155 | dev_err(wm8994->dev, "Failed to register IRQ chip: %d\n", ret); |
c9fbf7e0 MB |
156 | return ret; |
157 | } | |
158 | ||
159 | /* Enable top level interrupt if it was masked */ | |
160 | wm8994_reg_write(wm8994, WM8994_INTERRUPT_CONTROL, 0); | |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | void wm8994_irq_exit(struct wm8994 *wm8994) | |
166 | { | |
8ab30691 | 167 | regmap_del_irq_chip(wm8994->irq, wm8994->irq_data); |
c9fbf7e0 | 168 | } |