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1 | /* |
2 | * CARMA Board DATA-FPGA Programmer | |
3 | * | |
4 | * Copyright (c) 2009-2011 Ira W. Snyder <iws@ovro.caltech.edu> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/dma-mapping.h> | |
13 | #include <linux/of_platform.h> | |
14 | #include <linux/completion.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/highmem.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/mutex.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/leds.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/kref.h> | |
27 | #include <linux/fs.h> | |
28 | #include <linux/io.h> | |
29 | ||
30 | #include <media/videobuf-dma-sg.h> | |
31 | ||
32 | /* MPC8349EMDS specific get_immrbase() */ | |
33 | #include <sysdev/fsl_soc.h> | |
34 | ||
35 | static const char drv_name[] = "carma-fpga-program"; | |
36 | ||
37 | /* | |
38 | * Firmware images are always this exact size | |
39 | * | |
40 | * 12849552 bytes for a CARMA Digitizer Board (EP2S90 FPGAs) | |
41 | * 18662880 bytes for a CARMA Correlator Board (EP2S130 FPGAs) | |
42 | */ | |
43 | #define FW_SIZE_EP2S90 12849552 | |
44 | #define FW_SIZE_EP2S130 18662880 | |
45 | ||
46 | struct fpga_dev { | |
47 | struct miscdevice miscdev; | |
48 | ||
49 | /* Reference count */ | |
50 | struct kref ref; | |
51 | ||
52 | /* Device Registers */ | |
53 | struct device *dev; | |
54 | void __iomem *regs; | |
55 | void __iomem *immr; | |
56 | ||
57 | /* Freescale DMA Device */ | |
58 | struct dma_chan *chan; | |
59 | ||
60 | /* Interrupts */ | |
61 | int irq, status; | |
62 | struct completion completion; | |
63 | ||
64 | /* FPGA Bitfile */ | |
65 | struct mutex lock; | |
66 | ||
67 | struct videobuf_dmabuf vb; | |
68 | bool vb_allocated; | |
69 | ||
70 | /* max size and written bytes */ | |
71 | size_t fw_size; | |
72 | size_t bytes; | |
73 | }; | |
74 | ||
75 | /* | |
76 | * FPGA Bitfile Helpers | |
77 | */ | |
78 | ||
79 | /** | |
80 | * fpga_drop_firmware_data() - drop the bitfile image from memory | |
81 | * @priv: the driver's private data structure | |
82 | * | |
83 | * LOCKING: must hold priv->lock | |
84 | */ | |
85 | static void fpga_drop_firmware_data(struct fpga_dev *priv) | |
86 | { | |
87 | videobuf_dma_free(&priv->vb); | |
88 | priv->vb_allocated = false; | |
89 | priv->bytes = 0; | |
90 | } | |
91 | ||
92 | /* | |
93 | * Private Data Reference Count | |
94 | */ | |
95 | ||
96 | static void fpga_dev_remove(struct kref *ref) | |
97 | { | |
98 | struct fpga_dev *priv = container_of(ref, struct fpga_dev, ref); | |
99 | ||
100 | /* free any firmware image that was not programmed */ | |
101 | fpga_drop_firmware_data(priv); | |
102 | ||
103 | mutex_destroy(&priv->lock); | |
104 | kfree(priv); | |
105 | } | |
106 | ||
107 | /* | |
108 | * LED Trigger (could be a seperate module) | |
109 | */ | |
110 | ||
111 | /* | |
112 | * NOTE: this whole thing does have the problem that whenever the led's are | |
113 | * NOTE: first set to use the fpga trigger, they could be in the wrong state | |
114 | */ | |
115 | ||
116 | DEFINE_LED_TRIGGER(ledtrig_fpga); | |
117 | ||
118 | static void ledtrig_fpga_programmed(bool enabled) | |
119 | { | |
120 | if (enabled) | |
121 | led_trigger_event(ledtrig_fpga, LED_FULL); | |
122 | else | |
123 | led_trigger_event(ledtrig_fpga, LED_OFF); | |
124 | } | |
125 | ||
126 | /* | |
127 | * FPGA Register Helpers | |
128 | */ | |
129 | ||
130 | /* Register Definitions */ | |
131 | #define FPGA_CONFIG_CONTROL 0x40 | |
132 | #define FPGA_CONFIG_STATUS 0x44 | |
133 | #define FPGA_CONFIG_FIFO_SIZE 0x48 | |
134 | #define FPGA_CONFIG_FIFO_USED 0x4C | |
135 | #define FPGA_CONFIG_TOTAL_BYTE_COUNT 0x50 | |
136 | #define FPGA_CONFIG_CUR_BYTE_COUNT 0x54 | |
137 | ||
138 | #define FPGA_FIFO_ADDRESS 0x3000 | |
139 | ||
140 | static int fpga_fifo_size(void __iomem *regs) | |
141 | { | |
142 | return ioread32be(regs + FPGA_CONFIG_FIFO_SIZE); | |
143 | } | |
144 | ||
145 | #define CFG_STATUS_ERR_MASK 0xfffe | |
146 | ||
147 | static int fpga_config_error(void __iomem *regs) | |
148 | { | |
149 | return ioread32be(regs + FPGA_CONFIG_STATUS) & CFG_STATUS_ERR_MASK; | |
150 | } | |
151 | ||
152 | static int fpga_fifo_empty(void __iomem *regs) | |
153 | { | |
154 | return ioread32be(regs + FPGA_CONFIG_FIFO_USED) == 0; | |
155 | } | |
156 | ||
157 | static void fpga_fifo_write(void __iomem *regs, u32 val) | |
158 | { | |
159 | iowrite32be(val, regs + FPGA_FIFO_ADDRESS); | |
160 | } | |
161 | ||
162 | static void fpga_set_byte_count(void __iomem *regs, u32 count) | |
163 | { | |
164 | iowrite32be(count, regs + FPGA_CONFIG_TOTAL_BYTE_COUNT); | |
165 | } | |
166 | ||
167 | #define CFG_CTL_ENABLE (1 << 0) | |
168 | #define CFG_CTL_RESET (1 << 1) | |
169 | #define CFG_CTL_DMA (1 << 2) | |
170 | ||
171 | static void fpga_programmer_enable(struct fpga_dev *priv, bool dma) | |
172 | { | |
173 | u32 val; | |
174 | ||
175 | val = (dma) ? (CFG_CTL_ENABLE | CFG_CTL_DMA) : CFG_CTL_ENABLE; | |
176 | iowrite32be(val, priv->regs + FPGA_CONFIG_CONTROL); | |
177 | } | |
178 | ||
179 | static void fpga_programmer_disable(struct fpga_dev *priv) | |
180 | { | |
181 | iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL); | |
182 | } | |
183 | ||
184 | static void fpga_dump_registers(struct fpga_dev *priv) | |
185 | { | |
186 | u32 control, status, size, used, total, curr; | |
187 | ||
188 | /* good status: do nothing */ | |
189 | if (priv->status == 0) | |
190 | return; | |
191 | ||
192 | /* Dump all status registers */ | |
193 | control = ioread32be(priv->regs + FPGA_CONFIG_CONTROL); | |
194 | status = ioread32be(priv->regs + FPGA_CONFIG_STATUS); | |
195 | size = ioread32be(priv->regs + FPGA_CONFIG_FIFO_SIZE); | |
196 | used = ioread32be(priv->regs + FPGA_CONFIG_FIFO_USED); | |
197 | total = ioread32be(priv->regs + FPGA_CONFIG_TOTAL_BYTE_COUNT); | |
198 | curr = ioread32be(priv->regs + FPGA_CONFIG_CUR_BYTE_COUNT); | |
199 | ||
200 | dev_err(priv->dev, "Configuration failed, dumping status registers\n"); | |
201 | dev_err(priv->dev, "Control: 0x%.8x\n", control); | |
202 | dev_err(priv->dev, "Status: 0x%.8x\n", status); | |
203 | dev_err(priv->dev, "FIFO Size: 0x%.8x\n", size); | |
204 | dev_err(priv->dev, "FIFO Used: 0x%.8x\n", used); | |
205 | dev_err(priv->dev, "FIFO Total: 0x%.8x\n", total); | |
206 | dev_err(priv->dev, "FIFO Curr: 0x%.8x\n", curr); | |
207 | } | |
208 | ||
209 | /* | |
210 | * FPGA Power Supply Code | |
211 | */ | |
212 | ||
213 | #define CTL_PWR_CONTROL 0x2006 | |
214 | #define CTL_PWR_STATUS 0x200A | |
215 | #define CTL_PWR_FAIL 0x200B | |
216 | ||
217 | #define PWR_CONTROL_ENABLE 0x01 | |
218 | ||
219 | #define PWR_STATUS_ERROR_MASK 0x10 | |
220 | #define PWR_STATUS_GOOD 0x0f | |
221 | ||
222 | /* | |
223 | * Determine if the FPGA power is good for all supplies | |
224 | */ | |
225 | static bool fpga_power_good(struct fpga_dev *priv) | |
226 | { | |
227 | u8 val; | |
228 | ||
229 | val = ioread8(priv->regs + CTL_PWR_STATUS); | |
230 | if (val & PWR_STATUS_ERROR_MASK) | |
231 | return false; | |
232 | ||
233 | return val == PWR_STATUS_GOOD; | |
234 | } | |
235 | ||
236 | /* | |
237 | * Disable the FPGA power supplies | |
238 | */ | |
239 | static void fpga_disable_power_supplies(struct fpga_dev *priv) | |
240 | { | |
241 | unsigned long start; | |
242 | u8 val; | |
243 | ||
244 | iowrite8(0x0, priv->regs + CTL_PWR_CONTROL); | |
245 | ||
246 | /* | |
247 | * Wait 500ms for the power rails to discharge | |
248 | * | |
249 | * Without this delay, the CTL-CPLD state machine can get into a | |
250 | * state where it is waiting for the power-goods to assert, but they | |
251 | * never do. This only happens when enabling and disabling the | |
252 | * power sequencer very rapidly. | |
253 | * | |
254 | * The loop below will also wait for the power goods to de-assert, | |
255 | * but testing has shown that they are always disabled by the time | |
256 | * the sleep completes. However, omitting the sleep and only waiting | |
257 | * for the power-goods to de-assert was not sufficient to ensure | |
258 | * that the power sequencer would not wedge itself. | |
259 | */ | |
260 | msleep(500); | |
261 | ||
262 | start = jiffies; | |
263 | while (time_before(jiffies, start + HZ)) { | |
264 | val = ioread8(priv->regs + CTL_PWR_STATUS); | |
265 | if (!(val & PWR_STATUS_GOOD)) | |
266 | break; | |
267 | ||
268 | usleep_range(5000, 10000); | |
269 | } | |
270 | ||
271 | val = ioread8(priv->regs + CTL_PWR_STATUS); | |
272 | if (val & PWR_STATUS_GOOD) { | |
273 | dev_err(priv->dev, "power disable failed: " | |
274 | "power goods: status 0x%.2x\n", val); | |
275 | } | |
276 | ||
277 | if (val & PWR_STATUS_ERROR_MASK) { | |
278 | dev_err(priv->dev, "power disable failed: " | |
279 | "alarm bit set: status 0x%.2x\n", val); | |
280 | } | |
281 | } | |
282 | ||
283 | /** | |
284 | * fpga_enable_power_supplies() - enable the DATA-FPGA power supplies | |
285 | * @priv: the driver's private data structure | |
286 | * | |
287 | * Enable the DATA-FPGA power supplies, waiting up to 1 second for | |
288 | * them to enable successfully. | |
289 | * | |
290 | * Returns 0 on success, -ERRNO otherwise | |
291 | */ | |
292 | static int fpga_enable_power_supplies(struct fpga_dev *priv) | |
293 | { | |
294 | unsigned long start = jiffies; | |
295 | ||
296 | if (fpga_power_good(priv)) { | |
297 | dev_dbg(priv->dev, "power was already good\n"); | |
298 | return 0; | |
299 | } | |
300 | ||
301 | iowrite8(PWR_CONTROL_ENABLE, priv->regs + CTL_PWR_CONTROL); | |
302 | while (time_before(jiffies, start + HZ)) { | |
303 | if (fpga_power_good(priv)) | |
304 | return 0; | |
305 | ||
306 | usleep_range(5000, 10000); | |
307 | } | |
308 | ||
309 | return fpga_power_good(priv) ? 0 : -ETIMEDOUT; | |
310 | } | |
311 | ||
312 | /* | |
313 | * Determine if the FPGA power supplies are all enabled | |
314 | */ | |
315 | static bool fpga_power_enabled(struct fpga_dev *priv) | |
316 | { | |
317 | u8 val; | |
318 | ||
319 | val = ioread8(priv->regs + CTL_PWR_CONTROL); | |
320 | if (val & PWR_CONTROL_ENABLE) | |
321 | return true; | |
322 | ||
323 | return false; | |
324 | } | |
325 | ||
326 | /* | |
327 | * Determine if the FPGA's are programmed and running correctly | |
328 | */ | |
329 | static bool fpga_running(struct fpga_dev *priv) | |
330 | { | |
331 | if (!fpga_power_good(priv)) | |
332 | return false; | |
333 | ||
334 | /* Check the config done bit */ | |
335 | return ioread32be(priv->regs + FPGA_CONFIG_STATUS) & (1 << 18); | |
336 | } | |
337 | ||
338 | /* | |
339 | * FPGA Programming Code | |
340 | */ | |
341 | ||
342 | /** | |
343 | * fpga_program_block() - put a block of data into the programmer's FIFO | |
344 | * @priv: the driver's private data structure | |
345 | * @buf: the data to program | |
346 | * @count: the length of data to program (must be a multiple of 4 bytes) | |
347 | * | |
348 | * Returns 0 on success, -ERRNO otherwise | |
349 | */ | |
350 | static int fpga_program_block(struct fpga_dev *priv, void *buf, size_t count) | |
351 | { | |
352 | u32 *data = buf; | |
353 | int size = fpga_fifo_size(priv->regs); | |
354 | int i, len; | |
355 | unsigned long timeout; | |
356 | ||
357 | /* enforce correct data length for the FIFO */ | |
358 | BUG_ON(count % 4 != 0); | |
359 | ||
360 | while (count > 0) { | |
361 | ||
362 | /* Get the size of the block to write (maximum is FIFO_SIZE) */ | |
363 | len = min_t(size_t, count, size); | |
364 | timeout = jiffies + HZ / 4; | |
365 | ||
366 | /* Write the block */ | |
367 | for (i = 0; i < len / 4; i++) | |
368 | fpga_fifo_write(priv->regs, data[i]); | |
369 | ||
370 | /* Update the amounts left */ | |
371 | count -= len; | |
372 | data += len / 4; | |
373 | ||
374 | /* Wait for the fifo to empty */ | |
375 | while (true) { | |
376 | ||
377 | if (fpga_fifo_empty(priv->regs)) { | |
378 | break; | |
379 | } else { | |
380 | dev_dbg(priv->dev, "Fifo not empty\n"); | |
381 | cpu_relax(); | |
382 | } | |
383 | ||
384 | if (fpga_config_error(priv->regs)) { | |
385 | dev_err(priv->dev, "Error detected\n"); | |
386 | return -EIO; | |
387 | } | |
388 | ||
389 | if (time_after(jiffies, timeout)) { | |
390 | dev_err(priv->dev, "Fifo drain timeout\n"); | |
391 | return -ETIMEDOUT; | |
392 | } | |
393 | ||
394 | usleep_range(5000, 10000); | |
395 | } | |
396 | } | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | /** | |
402 | * fpga_program_cpu() - program the DATA-FPGA's using the CPU | |
403 | * @priv: the driver's private data structure | |
404 | * | |
405 | * This is useful when the DMA programming method fails. It is possible to | |
406 | * wedge the Freescale DMA controller such that the DMA programming method | |
407 | * always fails. This method has always succeeded. | |
408 | * | |
409 | * Returns 0 on success, -ERRNO otherwise | |
410 | */ | |
411 | static noinline int fpga_program_cpu(struct fpga_dev *priv) | |
412 | { | |
413 | int ret; | |
414 | ||
415 | /* Disable the programmer */ | |
416 | fpga_programmer_disable(priv); | |
417 | ||
418 | /* Set the total byte count */ | |
419 | fpga_set_byte_count(priv->regs, priv->bytes); | |
420 | dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes); | |
421 | ||
422 | /* Enable the controller for programming */ | |
423 | fpga_programmer_enable(priv, false); | |
424 | dev_dbg(priv->dev, "enabled the controller\n"); | |
425 | ||
426 | /* Write each chunk of the FPGA bitfile to FPGA programmer */ | |
427 | ret = fpga_program_block(priv, priv->vb.vaddr, priv->bytes); | |
428 | if (ret) | |
429 | goto out_disable_controller; | |
430 | ||
431 | /* Wait for the interrupt handler to signal that programming finished */ | |
432 | ret = wait_for_completion_timeout(&priv->completion, 2 * HZ); | |
433 | if (!ret) { | |
434 | dev_err(priv->dev, "Timed out waiting for completion\n"); | |
435 | ret = -ETIMEDOUT; | |
436 | goto out_disable_controller; | |
437 | } | |
438 | ||
439 | /* Retrieve the status from the interrupt handler */ | |
440 | ret = priv->status; | |
441 | ||
442 | out_disable_controller: | |
443 | fpga_programmer_disable(priv); | |
444 | return ret; | |
445 | } | |
446 | ||
447 | #define FIFO_DMA_ADDRESS 0xf0003000 | |
448 | #define FIFO_MAX_LEN 4096 | |
449 | ||
450 | /** | |
451 | * fpga_program_dma() - program the DATA-FPGA's using the DMA engine | |
452 | * @priv: the driver's private data structure | |
453 | * | |
454 | * Program the DATA-FPGA's using the Freescale DMA engine. This requires that | |
455 | * the engine is programmed such that the hardware DMA request lines can | |
456 | * control the entire DMA transaction. The system controller FPGA then | |
457 | * completely offloads the programming from the CPU. | |
458 | * | |
459 | * Returns 0 on success, -ERRNO otherwise | |
460 | */ | |
461 | static noinline int fpga_program_dma(struct fpga_dev *priv) | |
462 | { | |
463 | struct videobuf_dmabuf *vb = &priv->vb; | |
464 | struct dma_chan *chan = priv->chan; | |
465 | struct dma_async_tx_descriptor *tx; | |
466 | size_t num_pages, len, avail = 0; | |
467 | struct dma_slave_config config; | |
468 | struct scatterlist *sg; | |
469 | struct sg_table table; | |
470 | dma_cookie_t cookie; | |
471 | int ret, i; | |
472 | ||
473 | /* Disable the programmer */ | |
474 | fpga_programmer_disable(priv); | |
475 | ||
476 | /* Allocate a scatterlist for the DMA destination */ | |
477 | num_pages = DIV_ROUND_UP(priv->bytes, FIFO_MAX_LEN); | |
478 | ret = sg_alloc_table(&table, num_pages, GFP_KERNEL); | |
479 | if (ret) { | |
480 | dev_err(priv->dev, "Unable to allocate dst scatterlist\n"); | |
481 | ret = -ENOMEM; | |
482 | goto out_return; | |
483 | } | |
484 | ||
485 | /* | |
486 | * This is an ugly hack | |
487 | * | |
488 | * We fill in a scatterlist as if it were mapped for DMA. This is | |
489 | * necessary because there exists no better structure for this | |
490 | * inside the kernel code. | |
491 | * | |
492 | * As an added bonus, we can use the DMAEngine API for all of this, | |
493 | * rather than inventing another extremely similar API. | |
494 | */ | |
495 | avail = priv->bytes; | |
496 | for_each_sg(table.sgl, sg, num_pages, i) { | |
497 | len = min_t(size_t, avail, FIFO_MAX_LEN); | |
498 | sg_dma_address(sg) = FIFO_DMA_ADDRESS; | |
499 | sg_dma_len(sg) = len; | |
500 | ||
501 | avail -= len; | |
502 | } | |
503 | ||
504 | /* Map the buffer for DMA */ | |
505 | ret = videobuf_dma_map(priv->dev, &priv->vb); | |
506 | if (ret) { | |
507 | dev_err(priv->dev, "Unable to map buffer for DMA\n"); | |
508 | goto out_free_table; | |
509 | } | |
510 | ||
511 | /* | |
512 | * Configure the DMA channel to transfer FIFO_SIZE / 2 bytes per | |
513 | * transaction, and then put it under external control | |
514 | */ | |
515 | memset(&config, 0, sizeof(config)); | |
516 | config.direction = DMA_TO_DEVICE; | |
517 | config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
518 | config.dst_maxburst = fpga_fifo_size(priv->regs) / 2 / 4; | |
519 | ret = chan->device->device_control(chan, DMA_SLAVE_CONFIG, | |
520 | (unsigned long)&config); | |
521 | if (ret) { | |
522 | dev_err(priv->dev, "DMA slave configuration failed\n"); | |
523 | goto out_dma_unmap; | |
524 | } | |
525 | ||
526 | ret = chan->device->device_control(chan, FSLDMA_EXTERNAL_START, 1); | |
527 | if (ret) { | |
528 | dev_err(priv->dev, "DMA external control setup failed\n"); | |
529 | goto out_dma_unmap; | |
530 | } | |
531 | ||
532 | /* setup and submit the DMA transaction */ | |
533 | tx = chan->device->device_prep_dma_sg(chan, | |
534 | table.sgl, num_pages, | |
535 | vb->sglist, vb->sglen, 0); | |
536 | if (!tx) { | |
537 | dev_err(priv->dev, "Unable to prep DMA transaction\n"); | |
538 | ret = -ENOMEM; | |
539 | goto out_dma_unmap; | |
540 | } | |
541 | ||
542 | cookie = tx->tx_submit(tx); | |
543 | if (dma_submit_error(cookie)) { | |
544 | dev_err(priv->dev, "Unable to submit DMA transaction\n"); | |
545 | ret = -ENOMEM; | |
546 | goto out_dma_unmap; | |
547 | } | |
548 | ||
549 | dma_async_memcpy_issue_pending(chan); | |
550 | ||
551 | /* Set the total byte count */ | |
552 | fpga_set_byte_count(priv->regs, priv->bytes); | |
553 | dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes); | |
554 | ||
555 | /* Enable the controller for DMA programming */ | |
556 | fpga_programmer_enable(priv, true); | |
557 | dev_dbg(priv->dev, "enabled the controller\n"); | |
558 | ||
559 | /* Wait for the interrupt handler to signal that programming finished */ | |
560 | ret = wait_for_completion_timeout(&priv->completion, 2 * HZ); | |
561 | if (!ret) { | |
562 | dev_err(priv->dev, "Timed out waiting for completion\n"); | |
563 | ret = -ETIMEDOUT; | |
564 | goto out_disable_controller; | |
565 | } | |
566 | ||
567 | /* Retrieve the status from the interrupt handler */ | |
568 | ret = priv->status; | |
569 | ||
570 | out_disable_controller: | |
571 | fpga_programmer_disable(priv); | |
572 | out_dma_unmap: | |
573 | videobuf_dma_unmap(priv->dev, vb); | |
574 | out_free_table: | |
575 | sg_free_table(&table); | |
576 | out_return: | |
577 | return ret; | |
578 | } | |
579 | ||
580 | /* | |
581 | * Interrupt Handling | |
582 | */ | |
583 | ||
584 | static irqreturn_t fpga_irq(int irq, void *dev_id) | |
585 | { | |
586 | struct fpga_dev *priv = dev_id; | |
587 | ||
588 | /* Save the status */ | |
589 | priv->status = fpga_config_error(priv->regs) ? -EIO : 0; | |
590 | dev_dbg(priv->dev, "INTERRUPT status %d\n", priv->status); | |
591 | fpga_dump_registers(priv); | |
592 | ||
593 | /* Disabling the programmer clears the interrupt */ | |
594 | fpga_programmer_disable(priv); | |
595 | ||
596 | /* Notify any waiters */ | |
597 | complete(&priv->completion); | |
598 | ||
599 | return IRQ_HANDLED; | |
600 | } | |
601 | ||
602 | /* | |
603 | * SYSFS Helpers | |
604 | */ | |
605 | ||
606 | /** | |
607 | * fpga_do_stop() - deconfigure (reset) the DATA-FPGA's | |
608 | * @priv: the driver's private data structure | |
609 | * | |
610 | * LOCKING: must hold priv->lock | |
611 | */ | |
612 | static int fpga_do_stop(struct fpga_dev *priv) | |
613 | { | |
614 | u32 val; | |
615 | ||
616 | /* Set the led to unprogrammed */ | |
617 | ledtrig_fpga_programmed(false); | |
618 | ||
619 | /* Pulse the config line to reset the FPGA's */ | |
620 | val = CFG_CTL_ENABLE | CFG_CTL_RESET; | |
621 | iowrite32be(val, priv->regs + FPGA_CONFIG_CONTROL); | |
622 | iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL); | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
627 | static noinline int fpga_do_program(struct fpga_dev *priv) | |
628 | { | |
629 | int ret; | |
630 | ||
631 | if (priv->bytes != priv->fw_size) { | |
632 | dev_err(priv->dev, "Incorrect bitfile size: got %zu bytes, " | |
633 | "should be %zu bytes\n", | |
634 | priv->bytes, priv->fw_size); | |
635 | return -EINVAL; | |
636 | } | |
637 | ||
638 | if (!fpga_power_enabled(priv)) { | |
639 | dev_err(priv->dev, "Power not enabled\n"); | |
640 | return -EINVAL; | |
641 | } | |
642 | ||
643 | if (!fpga_power_good(priv)) { | |
644 | dev_err(priv->dev, "Power not good\n"); | |
645 | return -EINVAL; | |
646 | } | |
647 | ||
648 | /* Set the LED to unprogrammed */ | |
649 | ledtrig_fpga_programmed(false); | |
650 | ||
651 | /* Try to program the FPGA's using DMA */ | |
652 | ret = fpga_program_dma(priv); | |
653 | ||
654 | /* If DMA failed or doesn't exist, try with CPU */ | |
655 | if (ret) { | |
656 | dev_warn(priv->dev, "Falling back to CPU programming\n"); | |
657 | ret = fpga_program_cpu(priv); | |
658 | } | |
659 | ||
660 | if (ret) { | |
661 | dev_err(priv->dev, "Unable to program FPGA's\n"); | |
662 | return ret; | |
663 | } | |
664 | ||
665 | /* Drop the firmware bitfile from memory */ | |
666 | fpga_drop_firmware_data(priv); | |
667 | ||
668 | dev_dbg(priv->dev, "FPGA programming successful\n"); | |
669 | ledtrig_fpga_programmed(true); | |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
674 | /* | |
675 | * File Operations | |
676 | */ | |
677 | ||
678 | static int fpga_open(struct inode *inode, struct file *filp) | |
679 | { | |
680 | /* | |
681 | * The miscdevice layer puts our struct miscdevice into the | |
682 | * filp->private_data field. We use this to find our private | |
683 | * data and then overwrite it with our own private structure. | |
684 | */ | |
685 | struct fpga_dev *priv = container_of(filp->private_data, | |
686 | struct fpga_dev, miscdev); | |
687 | unsigned int nr_pages; | |
688 | int ret; | |
689 | ||
690 | /* We only allow one process at a time */ | |
691 | ret = mutex_lock_interruptible(&priv->lock); | |
692 | if (ret) | |
693 | return ret; | |
694 | ||
695 | filp->private_data = priv; | |
696 | kref_get(&priv->ref); | |
697 | ||
698 | /* Truncation: drop any existing data */ | |
699 | if (filp->f_flags & O_TRUNC) | |
700 | priv->bytes = 0; | |
701 | ||
702 | /* Check if we have already allocated a buffer */ | |
703 | if (priv->vb_allocated) | |
704 | return 0; | |
705 | ||
706 | /* Allocate a buffer to hold enough data for the bitfile */ | |
707 | nr_pages = DIV_ROUND_UP(priv->fw_size, PAGE_SIZE); | |
708 | ret = videobuf_dma_init_kernel(&priv->vb, DMA_TO_DEVICE, nr_pages); | |
709 | if (ret) { | |
710 | dev_err(priv->dev, "unable to allocate data buffer\n"); | |
711 | mutex_unlock(&priv->lock); | |
712 | kref_put(&priv->ref, fpga_dev_remove); | |
713 | return ret; | |
714 | } | |
715 | ||
716 | priv->vb_allocated = true; | |
717 | return 0; | |
718 | } | |
719 | ||
720 | static int fpga_release(struct inode *inode, struct file *filp) | |
721 | { | |
722 | struct fpga_dev *priv = filp->private_data; | |
723 | ||
724 | mutex_unlock(&priv->lock); | |
725 | kref_put(&priv->ref, fpga_dev_remove); | |
726 | return 0; | |
727 | } | |
728 | ||
729 | static ssize_t fpga_write(struct file *filp, const char __user *buf, | |
730 | size_t count, loff_t *f_pos) | |
731 | { | |
732 | struct fpga_dev *priv = filp->private_data; | |
733 | ||
734 | /* FPGA bitfiles have an exact size: disallow anything else */ | |
735 | if (priv->bytes >= priv->fw_size) | |
736 | return -ENOSPC; | |
737 | ||
738 | count = min_t(size_t, priv->fw_size - priv->bytes, count); | |
739 | if (copy_from_user(priv->vb.vaddr + priv->bytes, buf, count)) | |
740 | return -EFAULT; | |
741 | ||
742 | priv->bytes += count; | |
743 | return count; | |
744 | } | |
745 | ||
746 | static ssize_t fpga_read(struct file *filp, char __user *buf, size_t count, | |
747 | loff_t *f_pos) | |
748 | { | |
749 | struct fpga_dev *priv = filp->private_data; | |
750 | ||
751 | count = min_t(size_t, priv->bytes - *f_pos, count); | |
752 | if (copy_to_user(buf, priv->vb.vaddr + *f_pos, count)) | |
753 | return -EFAULT; | |
754 | ||
755 | *f_pos += count; | |
756 | return count; | |
757 | } | |
758 | ||
759 | static loff_t fpga_llseek(struct file *filp, loff_t offset, int origin) | |
760 | { | |
761 | struct fpga_dev *priv = filp->private_data; | |
762 | loff_t newpos; | |
763 | ||
764 | /* only read-only opens are allowed to seek */ | |
765 | if ((filp->f_flags & O_ACCMODE) != O_RDONLY) | |
766 | return -EINVAL; | |
767 | ||
768 | switch (origin) { | |
769 | case SEEK_SET: /* seek relative to the beginning of the file */ | |
770 | newpos = offset; | |
771 | break; | |
772 | case SEEK_CUR: /* seek relative to current position in the file */ | |
773 | newpos = filp->f_pos + offset; | |
774 | break; | |
775 | case SEEK_END: /* seek relative to the end of the file */ | |
776 | newpos = priv->fw_size - offset; | |
777 | break; | |
778 | default: | |
779 | return -EINVAL; | |
780 | } | |
781 | ||
782 | /* check for sanity */ | |
783 | if (newpos > priv->fw_size) | |
784 | return -EINVAL; | |
785 | ||
786 | filp->f_pos = newpos; | |
787 | return newpos; | |
788 | } | |
789 | ||
790 | static const struct file_operations fpga_fops = { | |
791 | .open = fpga_open, | |
792 | .release = fpga_release, | |
793 | .write = fpga_write, | |
794 | .read = fpga_read, | |
795 | .llseek = fpga_llseek, | |
796 | }; | |
797 | ||
798 | /* | |
799 | * Device Attributes | |
800 | */ | |
801 | ||
802 | static ssize_t pfail_show(struct device *dev, struct device_attribute *attr, | |
803 | char *buf) | |
804 | { | |
805 | struct fpga_dev *priv = dev_get_drvdata(dev); | |
806 | u8 val; | |
807 | ||
808 | val = ioread8(priv->regs + CTL_PWR_FAIL); | |
809 | return snprintf(buf, PAGE_SIZE, "0x%.2x\n", val); | |
810 | } | |
811 | ||
812 | static ssize_t pgood_show(struct device *dev, struct device_attribute *attr, | |
813 | char *buf) | |
814 | { | |
815 | struct fpga_dev *priv = dev_get_drvdata(dev); | |
816 | return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_good(priv)); | |
817 | } | |
818 | ||
819 | static ssize_t penable_show(struct device *dev, struct device_attribute *attr, | |
820 | char *buf) | |
821 | { | |
822 | struct fpga_dev *priv = dev_get_drvdata(dev); | |
823 | return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_enabled(priv)); | |
824 | } | |
825 | ||
826 | static ssize_t penable_store(struct device *dev, struct device_attribute *attr, | |
827 | const char *buf, size_t count) | |
828 | { | |
829 | struct fpga_dev *priv = dev_get_drvdata(dev); | |
830 | unsigned long val; | |
831 | int ret; | |
832 | ||
833 | if (strict_strtoul(buf, 0, &val)) | |
834 | return -EINVAL; | |
835 | ||
836 | if (val) { | |
837 | ret = fpga_enable_power_supplies(priv); | |
838 | if (ret) | |
839 | return ret; | |
840 | } else { | |
841 | fpga_do_stop(priv); | |
842 | fpga_disable_power_supplies(priv); | |
843 | } | |
844 | ||
845 | return count; | |
846 | } | |
847 | ||
848 | static ssize_t program_show(struct device *dev, struct device_attribute *attr, | |
849 | char *buf) | |
850 | { | |
851 | struct fpga_dev *priv = dev_get_drvdata(dev); | |
852 | return snprintf(buf, PAGE_SIZE, "%d\n", fpga_running(priv)); | |
853 | } | |
854 | ||
855 | static ssize_t program_store(struct device *dev, struct device_attribute *attr, | |
856 | const char *buf, size_t count) | |
857 | { | |
858 | struct fpga_dev *priv = dev_get_drvdata(dev); | |
859 | unsigned long val; | |
860 | int ret; | |
861 | ||
862 | if (strict_strtoul(buf, 0, &val)) | |
863 | return -EINVAL; | |
864 | ||
865 | /* We can't have an image writer and be programming simultaneously */ | |
866 | if (mutex_lock_interruptible(&priv->lock)) | |
867 | return -ERESTARTSYS; | |
868 | ||
869 | /* Program or Reset the FPGA's */ | |
870 | ret = val ? fpga_do_program(priv) : fpga_do_stop(priv); | |
871 | if (ret) | |
872 | goto out_unlock; | |
873 | ||
874 | /* Success */ | |
875 | ret = count; | |
876 | ||
877 | out_unlock: | |
878 | mutex_unlock(&priv->lock); | |
879 | return ret; | |
880 | } | |
881 | ||
882 | static DEVICE_ATTR(power_fail, S_IRUGO, pfail_show, NULL); | |
883 | static DEVICE_ATTR(power_good, S_IRUGO, pgood_show, NULL); | |
884 | static DEVICE_ATTR(power_enable, S_IRUGO | S_IWUSR, | |
885 | penable_show, penable_store); | |
886 | ||
887 | static DEVICE_ATTR(program, S_IRUGO | S_IWUSR, | |
888 | program_show, program_store); | |
889 | ||
890 | static struct attribute *fpga_attributes[] = { | |
891 | &dev_attr_power_fail.attr, | |
892 | &dev_attr_power_good.attr, | |
893 | &dev_attr_power_enable.attr, | |
894 | &dev_attr_program.attr, | |
895 | NULL, | |
896 | }; | |
897 | ||
898 | static const struct attribute_group fpga_attr_group = { | |
899 | .attrs = fpga_attributes, | |
900 | }; | |
901 | ||
902 | /* | |
903 | * OpenFirmware Device Subsystem | |
904 | */ | |
905 | ||
906 | #define SYS_REG_VERSION 0x00 | |
907 | #define SYS_REG_GEOGRAPHIC 0x10 | |
908 | ||
909 | static bool dma_filter(struct dma_chan *chan, void *data) | |
910 | { | |
911 | /* | |
912 | * DMA Channel #0 is the only acceptable device | |
913 | * | |
914 | * This probably won't survive an unload/load cycle of the Freescale | |
915 | * DMAEngine driver, but that won't be a problem | |
916 | */ | |
917 | return chan->chan_id == 0 && chan->device->dev_id == 0; | |
918 | } | |
919 | ||
920 | static int fpga_of_remove(struct platform_device *op) | |
921 | { | |
922 | struct fpga_dev *priv = dev_get_drvdata(&op->dev); | |
923 | struct device *this_device = priv->miscdev.this_device; | |
924 | ||
925 | sysfs_remove_group(&this_device->kobj, &fpga_attr_group); | |
926 | misc_deregister(&priv->miscdev); | |
927 | ||
928 | free_irq(priv->irq, priv); | |
929 | irq_dispose_mapping(priv->irq); | |
930 | ||
931 | /* make sure the power supplies are off */ | |
932 | fpga_disable_power_supplies(priv); | |
933 | ||
934 | /* unmap registers */ | |
935 | iounmap(priv->immr); | |
936 | iounmap(priv->regs); | |
937 | ||
938 | dma_release_channel(priv->chan); | |
939 | ||
940 | /* drop our reference to the private data structure */ | |
941 | kref_put(&priv->ref, fpga_dev_remove); | |
942 | return 0; | |
943 | } | |
944 | ||
945 | /* CTL-CPLD Version Register */ | |
946 | #define CTL_CPLD_VERSION 0x2000 | |
947 | ||
948 | static int fpga_of_probe(struct platform_device *op, | |
949 | const struct of_device_id *match) | |
950 | { | |
951 | struct device_node *of_node = op->dev.of_node; | |
952 | struct device *this_device; | |
953 | struct fpga_dev *priv; | |
954 | dma_cap_mask_t mask; | |
955 | u32 ver; | |
956 | int ret; | |
957 | ||
958 | /* Allocate private data */ | |
959 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
960 | if (!priv) { | |
961 | dev_err(&op->dev, "Unable to allocate private data\n"); | |
962 | ret = -ENOMEM; | |
963 | goto out_return; | |
964 | } | |
965 | ||
966 | /* Setup the miscdevice */ | |
967 | priv->miscdev.minor = MISC_DYNAMIC_MINOR; | |
968 | priv->miscdev.name = drv_name; | |
969 | priv->miscdev.fops = &fpga_fops; | |
970 | ||
971 | kref_init(&priv->ref); | |
972 | ||
973 | dev_set_drvdata(&op->dev, priv); | |
974 | priv->dev = &op->dev; | |
975 | mutex_init(&priv->lock); | |
976 | init_completion(&priv->completion); | |
977 | videobuf_dma_init(&priv->vb); | |
978 | ||
979 | dev_set_drvdata(priv->dev, priv); | |
980 | dma_cap_zero(mask); | |
981 | dma_cap_set(DMA_MEMCPY, mask); | |
982 | dma_cap_set(DMA_INTERRUPT, mask); | |
983 | dma_cap_set(DMA_SLAVE, mask); | |
984 | dma_cap_set(DMA_SG, mask); | |
985 | ||
986 | /* Get control of DMA channel #0 */ | |
987 | priv->chan = dma_request_channel(mask, dma_filter, NULL); | |
988 | if (!priv->chan) { | |
989 | dev_err(&op->dev, "Unable to acquire DMA channel #0\n"); | |
990 | ret = -ENODEV; | |
991 | goto out_free_priv; | |
992 | } | |
993 | ||
994 | /* Remap the registers for use */ | |
995 | priv->regs = of_iomap(of_node, 0); | |
996 | if (!priv->regs) { | |
997 | dev_err(&op->dev, "Unable to ioremap registers\n"); | |
998 | ret = -ENOMEM; | |
999 | goto out_dma_release_channel; | |
1000 | } | |
1001 | ||
1002 | /* Remap the IMMR for use */ | |
1003 | priv->immr = ioremap(get_immrbase(), 0x100000); | |
1004 | if (!priv->immr) { | |
1005 | dev_err(&op->dev, "Unable to ioremap IMMR\n"); | |
1006 | ret = -ENOMEM; | |
1007 | goto out_unmap_regs; | |
1008 | } | |
1009 | ||
1010 | /* | |
1011 | * Check that external DMA is configured | |
1012 | * | |
1013 | * U-Boot does this for us, but we should check it and bail out if | |
1014 | * there is a problem. Failing to have this register setup correctly | |
1015 | * will cause the DMA controller to transfer a single cacheline | |
1016 | * worth of data, then wedge itself. | |
1017 | */ | |
1018 | if ((ioread32be(priv->immr + 0x114) & 0xE00) != 0xE00) { | |
1019 | dev_err(&op->dev, "External DMA control not configured\n"); | |
1020 | ret = -ENODEV; | |
1021 | goto out_unmap_immr; | |
1022 | } | |
1023 | ||
1024 | /* | |
1025 | * Check the CTL-CPLD version | |
1026 | * | |
1027 | * This driver uses the CTL-CPLD DATA-FPGA power sequencer, and we | |
1028 | * don't want to run on any version of the CTL-CPLD that does not use | |
1029 | * a compatible register layout. | |
1030 | * | |
1031 | * v2: changed register layout, added power sequencer | |
1032 | * v3: added glitch filter on the i2c overcurrent/overtemp outputs | |
1033 | */ | |
1034 | ver = ioread8(priv->regs + CTL_CPLD_VERSION); | |
1035 | if (ver != 0x02 && ver != 0x03) { | |
1036 | dev_err(&op->dev, "CTL-CPLD is not version 0x02 or 0x03!\n"); | |
1037 | ret = -ENODEV; | |
1038 | goto out_unmap_immr; | |
1039 | } | |
1040 | ||
1041 | /* Set the exact size that the firmware image should be */ | |
1042 | ver = ioread32be(priv->regs + SYS_REG_VERSION); | |
1043 | priv->fw_size = (ver & (1 << 18)) ? FW_SIZE_EP2S130 : FW_SIZE_EP2S90; | |
1044 | ||
1045 | /* Find the correct IRQ number */ | |
1046 | priv->irq = irq_of_parse_and_map(of_node, 0); | |
1047 | if (priv->irq == NO_IRQ) { | |
1048 | dev_err(&op->dev, "Unable to find IRQ line\n"); | |
1049 | ret = -ENODEV; | |
1050 | goto out_unmap_immr; | |
1051 | } | |
1052 | ||
1053 | /* Request the IRQ */ | |
1054 | ret = request_irq(priv->irq, fpga_irq, IRQF_SHARED, drv_name, priv); | |
1055 | if (ret) { | |
1056 | dev_err(&op->dev, "Unable to request IRQ %d\n", priv->irq); | |
1057 | ret = -ENODEV; | |
1058 | goto out_irq_dispose_mapping; | |
1059 | } | |
1060 | ||
1061 | /* Reset and stop the FPGA's, just in case */ | |
1062 | fpga_do_stop(priv); | |
1063 | ||
1064 | /* Register the miscdevice */ | |
1065 | ret = misc_register(&priv->miscdev); | |
1066 | if (ret) { | |
1067 | dev_err(&op->dev, "Unable to register miscdevice\n"); | |
1068 | goto out_free_irq; | |
1069 | } | |
1070 | ||
1071 | /* Create the sysfs files */ | |
1072 | this_device = priv->miscdev.this_device; | |
1073 | dev_set_drvdata(this_device, priv); | |
1074 | ret = sysfs_create_group(&this_device->kobj, &fpga_attr_group); | |
1075 | if (ret) { | |
1076 | dev_err(&op->dev, "Unable to create sysfs files\n"); | |
1077 | goto out_misc_deregister; | |
1078 | } | |
1079 | ||
1080 | dev_info(priv->dev, "CARMA FPGA Programmer: %s rev%s with %s FPGAs\n", | |
1081 | (ver & (1 << 17)) ? "Correlator" : "Digitizer", | |
1082 | (ver & (1 << 16)) ? "B" : "A", | |
1083 | (ver & (1 << 18)) ? "EP2S130" : "EP2S90"); | |
1084 | ||
1085 | return 0; | |
1086 | ||
1087 | out_misc_deregister: | |
1088 | misc_deregister(&priv->miscdev); | |
1089 | out_free_irq: | |
1090 | free_irq(priv->irq, priv); | |
1091 | out_irq_dispose_mapping: | |
1092 | irq_dispose_mapping(priv->irq); | |
1093 | out_unmap_immr: | |
1094 | iounmap(priv->immr); | |
1095 | out_unmap_regs: | |
1096 | iounmap(priv->regs); | |
1097 | out_dma_release_channel: | |
1098 | dma_release_channel(priv->chan); | |
1099 | out_free_priv: | |
1100 | kref_put(&priv->ref, fpga_dev_remove); | |
1101 | out_return: | |
1102 | return ret; | |
1103 | } | |
1104 | ||
1105 | static struct of_device_id fpga_of_match[] = { | |
1106 | { .compatible = "carma,fpga-programmer", }, | |
1107 | {}, | |
1108 | }; | |
1109 | ||
1110 | static struct of_platform_driver fpga_of_driver = { | |
1111 | .probe = fpga_of_probe, | |
1112 | .remove = fpga_of_remove, | |
1113 | .driver = { | |
1114 | .name = drv_name, | |
1115 | .of_match_table = fpga_of_match, | |
1116 | .owner = THIS_MODULE, | |
1117 | }, | |
1118 | }; | |
1119 | ||
1120 | /* | |
1121 | * Module Init / Exit | |
1122 | */ | |
1123 | ||
1124 | static int __init fpga_init(void) | |
1125 | { | |
1126 | led_trigger_register_simple("fpga", &ledtrig_fpga); | |
1127 | return of_register_platform_driver(&fpga_of_driver); | |
1128 | } | |
1129 | ||
1130 | static void __exit fpga_exit(void) | |
1131 | { | |
1132 | of_unregister_platform_driver(&fpga_of_driver); | |
1133 | led_trigger_unregister_simple(ledtrig_fpga); | |
1134 | } | |
1135 | ||
1136 | MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>"); | |
1137 | MODULE_DESCRIPTION("CARMA Board DATA-FPGA Programmer"); | |
1138 | MODULE_LICENSE("GPL"); | |
1139 | ||
1140 | module_init(fpga_init); | |
1141 | module_exit(fpga_exit); |