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cxl: Fix force unmapping mmaps of contexts allocated through the kernel api
[mirror_ubuntu-hirsute-kernel.git] / drivers / misc / cxl / cxl.h
CommitLineData
f204e0b8
IM		 1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#ifndef _CXL_H_
11#define _CXL_H_
12
13#include <linux/interrupt.h>
14#include <linux/semaphore.h>
15#include <linux/device.h>
16#include <linux/types.h>
17#include <linux/cdev.h>
18#include <linux/pid.h>
19#include <linux/io.h>
20#include <linux/pci.h>
0520336a 21#include <linux/fs.h>
f204e0b8
IM		 22#include <asm/cputable.h>
23#include <asm/mmu.h>
24#include <asm/reg.h>
ec249dd8 25#include <misc/cxl-base.h>
f204e0b8
IM		 26
27#include <uapi/misc/cxl.h>
28
29extern uint cxl_verbose;
30
31#define CXL_TIMEOUT 5
32
33/*
34 * Bump version each time a user API change is made, whether it is
35 * backwards compatible ot not.
36 */
d9232a3d 37#define CXL_API_VERSION 2
f204e0b8
IM		 38#define CXL_API_VERSION_COMPATIBLE 1
39
40/*
41 * Opaque types to avoid accidentally passing registers for the wrong MMIO
42 *
43 * At the end of the day, I'm not married to using typedef here, but it might
44 * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
45 * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
46 *
47 * I'm quite happy if these are changed back to #defines before upstreaming, it
48 * should be little more than a regexp search+replace operation in this file.
49 */
50typedef struct {
51 const int x;
52} cxl_p1_reg_t;
53typedef struct {
54 const int x;
55} cxl_p1n_reg_t;
56typedef struct {
57 const int x;
58} cxl_p2n_reg_t;
59#define cxl_reg_off(reg) \
60 (reg.x)
61
62/* Memory maps. Ref CXL Appendix A */
63
64/* PSL Privilege 1 Memory Map */
65/* Configuration and Control area */
66static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
67static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
68static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010};
69static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018};
70static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
71/* Downloading */
72static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060};
73static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068};
74
75/* PSL Lookaside Buffer Management Area */
76static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080};
77static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088};
78static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090};
79static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0};
80static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8};
81static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0};
82
83/* 0x00C0:7EFF Implementation dependent area */
84static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100};
85static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108};
86static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118};
87static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128};
88static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148};
89static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150};
90static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
91static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170};
92/* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
93/* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
94
95/* PSL Slice Privilege 1 Memory Map */
96/* Configuration Area */
97static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00};
98static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08};
99static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10};
100static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18};
101static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20};
102static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28};
103/* Memory Management and Lookaside Buffer Management */
104static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30};
105static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38};
106/* Pointer Area */
107static const cxl_p1n_reg_t CXL_HAURP_An = {0x80};
108static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88};
109static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90};
110/* Control Area */
111static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0};
112static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8};
113static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
114static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8};
115/* 0xC0:FF Implementation Dependent Area */
116static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0};
117static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8};
118static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0};
119static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8};
120static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0};
121static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8};
122
123/* PSL Slice Privilege 2 Memory Map */
124/* Configuration and Control Area */
125static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
126static const cxl_p2n_reg_t CXL_CSRP_An = {0x008};
127static const cxl_p2n_reg_t CXL_AURP0_An = {0x010};
128static const cxl_p2n_reg_t CXL_AURP1_An = {0x018};
129static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020};
130static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028};
131static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030};
132/* Segment Lookaside Buffer Management */
133static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040};
134static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048};
135static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
136/* Interrupt Registers */
137static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060};
138static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068};
139static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070};
140static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078};
141static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
142static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
143/* AFU Registers */
144static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090};
145static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098};
146/* Work Element Descriptor */
147static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
148/* 0x0C0:FFF Implementation Dependent Area */
149
150#define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
151#define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
152#define CXL_PSL_SPAP_Size_Shift 4
153#define CXL_PSL_SPAP_V 0x0000000000000001ULL
154
155/****** CXL_PSL_DLCNTL *****************************************************/
156#define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
157#define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
158#define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
159#define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
160#define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
161#define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
162
163/****** CXL_PSL_SR_An ******************************************************/
164#define CXL_PSL_SR_An_SF MSR_SF /* 64bit */
165#define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
166#define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */
167#define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */
168#define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
169#define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
170#define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
171#define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
172#define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */
173#define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
174#define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
175
176/****** CXL_PSL_LLCMD_An ****************************************************/
177#define CXL_LLCMD_TERMINATE 0x0001000000000000ULL
178#define CXL_LLCMD_REMOVE 0x0002000000000000ULL
179#define CXL_LLCMD_SUSPEND 0x0003000000000000ULL
180#define CXL_LLCMD_RESUME 0x0004000000000000ULL
181#define CXL_LLCMD_ADD 0x0005000000000000ULL
182#define CXL_LLCMD_UPDATE 0x0006000000000000ULL
183#define CXL_LLCMD_HANDLE_MASK 0x000000000000ffffULL
184
185/****** CXL_PSL_ID_An ****************************************************/
186#define CXL_PSL_ID_An_F (1ull << (63-31))
187#define CXL_PSL_ID_An_L (1ull << (63-30))
188
189/****** CXL_PSL_SCNTL_An ****************************************************/
190#define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15))
191/* Programming Modes: */
192#define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31))
193#define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31))
194#define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31))
195#define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31))
196#define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31))
197#define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31))
198/* Purge Status (ro) */
199#define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39))
200#define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39))
201#define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
202/* Purge */
203#define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48))
204/* Suspend Status (ro) */
205#define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55))
206#define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55))
207#define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
208/* Suspend Control */
209#define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63))
210
211/* AFU Slice Enable Status (ro) */
212#define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2))
213#define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
214#define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2))
215/* AFU Slice Enable */
216#define CXL_AFU_Cntl_An_E (0x1ull << (63-3))
217/* AFU Slice Reset status (ro) */
218#define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5))
219#define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5))
220#define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
221/* AFU Slice Reset */
222#define CXL_AFU_Cntl_An_RA (0x1ull << (63-7))
223
224/****** CXL_SSTP0/1_An ******************************************************/
225/* These top bits are for the segment that CONTAINS the segment table */
226#define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT
227#define CXL_SSTP0_An_KS (1ull << (63-2))
228#define CXL_SSTP0_An_KP (1ull << (63-3))
229#define CXL_SSTP0_An_N (1ull << (63-4))
230#define CXL_SSTP0_An_L (1ull << (63-5))
231#define CXL_SSTP0_An_C (1ull << (63-6))
232#define CXL_SSTP0_An_TA (1ull << (63-7))
233#define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */
234/* And finally, the virtual address & size of the segment table: */
235#define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */
236#define CXL_SSTP0_An_SegTableSize_MASK \
237 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
238#define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
239#define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
240#define CXL_SSTP1_An_V (1ull << (63-63))
241
242/****** CXL_PSL_SLBIE_[An] **************************************************/
243/* write: */
244#define CXL_SLBIE_C PPC_BIT(36) /* Class */
245#define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */
246#define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
247#define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */
248/* read: */
249#define CXL_SLBIE_MAX PPC_BITMASK(24, 31)
250#define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)
251
252/****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/
253#define CXL_TLB_SLB_P (1ull) /* Pending (read) */
254
255/****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/
256#define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */
257#define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */
258#define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
259
260/****** CXL_PSL_AFUSEL ******************************************************/
261#define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
262
263/****** CXL_PSL_DSISR_An ****************************************************/
264#define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
265#define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
266#define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
267#define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
268#define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
269#define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
270#define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
271#define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
272/* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
273#define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */
274#define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */
275#define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
276#define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */
277#define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */
278
279/****** CXL_PSL_TFC_An ******************************************************/
280#define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
281#define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
282#define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
283#define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
284
285/* cxl_process_element->software_status */
286#define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */
287#define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
288#define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
289#define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
290
d6a6af2c
IM		 291/****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
292 * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
293 * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
294 * of the hang pulse frequency.
295 */
296#define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL
297
f204e0b8
IM		 298/* SPA->sw_command_status */
299#define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL
300#define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL
301#define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL
302#define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL
303#define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL
304#define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL
305#define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL
306#define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL
307#define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
308#define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL
309#define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL
310#define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL
311#define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL
312#define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL
313#define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL
314#define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL
315
316#define CXL_MAX_SLICES 4
317#define MAX_AFU_MMIO_REGS 3
318
f204e0b8
IM		 319#define CXL_MODE_TIME_SLICED 0x4
320#define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
321
322enum cxl_context_status {
323 CLOSED,
324 OPENED,
325 STARTED
326};
327
328enum prefault_modes {
329 CXL_PREFAULT_NONE,
330 CXL_PREFAULT_WED,
331 CXL_PREFAULT_ALL,
332};
333
334struct cxl_sste {
335 __be64 esid_data;
336 __be64 vsid_data;
337};
338
339#define to_cxl_adapter(d) container_of(d, struct cxl, dev)
340#define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
341
342struct cxl_afu {
343 irq_hw_number_t psl_hwirq;
344 irq_hw_number_t serr_hwirq;
80fa93fc
MN		 345 char *err_irq_name;
346 char *psl_irq_name;
f204e0b8
IM		 347 unsigned int serr_virq;
348 void __iomem *p1n_mmio;
349 void __iomem *p2n_mmio;
350 phys_addr_t psn_phys;
351 u64 pp_offset;
352 u64 pp_size;
353 void __iomem *afu_desc_mmio;
354 struct cxl *adapter;
355 struct device dev;
356 struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
357 struct device *chardev_s, *chardev_m, *chardev_d;
358 struct idr contexts_idr;
359 struct dentry *debugfs;
ee41d11d 360 struct mutex contexts_lock;
f204e0b8
IM		 361 struct mutex spa_mutex;
362 spinlock_t afu_cntl_lock;
363
e36f6fe1
VJ		 364 /* AFU error buffer fields and bin attribute for sysfs */
365 u64 eb_len, eb_offset;
366 struct bin_attribute attr_eb;
367
f204e0b8
IM		 368 /*
369 * Only the first part of the SPA is used for the process element
370 * linked list. The only other part that software needs to worry about
371 * is sw_command_status, which we store a separate pointer to.
372 * Everything else in the SPA is only used by hardware
373 */
374 struct cxl_process_element *spa;
375 __be64 *sw_command_status;
376 unsigned int spa_size;
377 int spa_order;
378 int spa_max_procs;
379 unsigned int psl_virq;
380
6f7f0b3d
MN		 381 /* pointer to the vphb */
382 struct pci_controller *phb;
383
f204e0b8
IM		 384 int pp_irqs;
385 int irqs_max;
386 int num_procs;
387 int max_procs_virtualised;
388 int slice;
389 int modes_supported;
390 int current_mode;
b087e619
IM		 391 int crs_num;
392 u64 crs_len;
393 u64 crs_offset;
394 struct list_head crs;
f204e0b8
IM		 395 enum prefault_modes prefault_mode;
396 bool psa;
397 bool pp_psa;
398 bool enabled;
399};
400
80fa93fc
MN		 401
402struct cxl_irq_name {
403 struct list_head list;
404 char *name;
405};
406
f204e0b8
IM		 407/*
408 * This is a cxl context. If the PSL is in dedicated mode, there will be one
409 * of these per AFU. If in AFU directed there can be lots of these.
410 */
411struct cxl_context {
412 struct cxl_afu *afu;
413
414 /* Problem state MMIO */
415 phys_addr_t psn_phys;
416 u64 psn_size;
417
b123429e
IM		 418 /* Used to unmap any mmaps when force detaching */
419 struct address_space *mapping;
420 struct mutex mapping_lock;
d9232a3d
IM		 421 struct page *ff_page;
422 bool mmio_err_ff;
55e07668 423 bool kernelapi;
b123429e 424
f204e0b8
IM		 425 spinlock_t sste_lock; /* Protects segment table entries */
426 struct cxl_sste *sstp;
427 u64 sstp0, sstp1;
428 unsigned int sst_size, sst_lru;
429
430 wait_queue_head_t wq;
431 struct pid *pid;
432 spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
433 /* Only used in PR mode */
434 u64 process_token;
435
436 unsigned long *irq_bitmap; /* Accessed from IRQ context */
437 struct cxl_irq_ranges irqs;
80fa93fc 438 struct list_head irq_names;
f204e0b8
IM		 439 u64 fault_addr;
440 u64 fault_dsisr;
441 u64 afu_err;
442
443 /*
444 * This status and it's lock pretects start and detach context
445 * from racing. It also prevents detach from racing with
446 * itself
447 */
448 enum cxl_context_status status;
449 struct mutex status_mutex;
450
451
452 /* XXX: Is it possible to need multiple work items at once? */
453 struct work_struct fault_work;
454 u64 dsisr;
455 u64 dar;
456
457 struct cxl_process_element *elem;
458
459 int pe; /* process element handle */
460 u32 irq_count;
461 bool pe_inserted;
462 bool master;
463 bool kernel;
464 bool pending_irq;
465 bool pending_fault;
466 bool pending_afu_err;
8ac75b96
IM		 467
468 struct rcu_head rcu;
f204e0b8
IM		 469};
470
471struct cxl {
472 void __iomem *p1_mmio;
473 void __iomem *p2_mmio;
474 irq_hw_number_t err_hwirq;
475 unsigned int err_virq;
476 spinlock_t afu_list_lock;
477 struct cxl_afu *afu[CXL_MAX_SLICES];
478 struct device dev;
479 struct dentry *trace;
480 struct dentry *psl_err_chk;
481 struct dentry *debugfs;
80fa93fc 482 char *irq_name;
f204e0b8
IM		 483 struct bin_attribute cxl_attr;
484 int adapter_num;
485 int user_irqs;
486 u64 afu_desc_off;
487 u64 afu_desc_size;
488 u64 ps_off;
489 u64 ps_size;
490 u16 psl_rev;
491 u16 base_image;
492 u8 vsec_status;
493 u8 caia_major;
494 u8 caia_minor;
495 u8 slices;
496 bool user_image_loaded;
497 bool perst_loads_image;
498 bool perst_select_user;
13e68d8b 499 bool perst_same_image;
f204e0b8
IM		 500};
501
502int cxl_alloc_one_irq(struct cxl *adapter);
503void cxl_release_one_irq(struct cxl *adapter, int hwirq);
504int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
505void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
506int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
4beb5421 507int cxl_update_image_control(struct cxl *adapter);
62fa19d4 508int cxl_reset(struct cxl *adapter);
f204e0b8
IM		 509
510/* common == phyp + powernv */
511struct cxl_process_element_common {
512 __be32 tid;
513 __be32 pid;
514 __be64 csrp;
515 __be64 aurp0;
516 __be64 aurp1;
517 __be64 sstp0;
518 __be64 sstp1;
519 __be64 amr;
520 u8 reserved3[4];
521 __be64 wed;
522} __packed;
523
524/* just powernv */
525struct cxl_process_element {
526 __be64 sr;
527 __be64 SPOffset;
528 __be64 sdr;
529 __be64 haurp;
530 __be32 ctxtime;
531 __be16 ivte_offsets[4];
532 __be16 ivte_ranges[4];
533 __be32 lpid;
534 struct cxl_process_element_common common;
535 __be32 software_state;
536} __packed;
537
0b3f9c75
DA		 538static inline bool cxl_adapter_link_ok(struct cxl *cxl)
539{
540 struct pci_dev *pdev;
541
542 pdev = to_pci_dev(cxl->dev.parent);
543 return !pci_channel_offline(pdev);
544}
545
f204e0b8
IM		 546static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
547{
548 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
549 return cxl->p1_mmio + cxl_reg_off(reg);
550}
551
588b34be
DA		 552static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
553{
0b3f9c75
DA		 554 if (likely(cxl_adapter_link_ok(cxl)))
555 out_be64(_cxl_p1_addr(cxl, reg), val);
588b34be
DA		 556}
557
558static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
559{
0b3f9c75
DA		 560 if (likely(cxl_adapter_link_ok(cxl)))
561 return in_be64(_cxl_p1_addr(cxl, reg));
562 else
563 return ~0ULL;
588b34be 564}
f204e0b8
IM		 565
566static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
567{
568 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
569 return afu->p1n_mmio + cxl_reg_off(reg);
570}
571
588b34be
DA		 572static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
573{
0b3f9c75
DA		 574 if (likely(cxl_adapter_link_ok(afu->adapter)))
575 out_be64(_cxl_p1n_addr(afu, reg), val);
588b34be
DA		 576}
577
578static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
579{
0b3f9c75
DA		 580 if (likely(cxl_adapter_link_ok(afu->adapter)))
581 return in_be64(_cxl_p1n_addr(afu, reg));
582 else
583 return ~0ULL;
588b34be 584}
f204e0b8
IM		 585
586static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
587{
588 return afu->p2n_mmio + cxl_reg_off(reg);
589}
590
588b34be
DA		 591static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
592{
0b3f9c75
DA		 593 if (likely(cxl_adapter_link_ok(afu->adapter)))
594 out_be64(_cxl_p2n_addr(afu, reg), val);
588b34be 595}
f204e0b8 596
588b34be
DA		 597static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
598{
0b3f9c75
DA		 599 if (likely(cxl_adapter_link_ok(afu->adapter)))
600 return in_be64(_cxl_p2n_addr(afu, reg));
601 else
602 return ~0ULL;
588b34be 603}
b087e619 604
588b34be
DA		 605static inline u64 cxl_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off)
606{
0b3f9c75
DA		 607 if (likely(cxl_adapter_link_ok(afu->adapter)))
608 return in_le64((afu)->afu_desc_mmio + (afu)->crs_offset +
609 ((cr) * (afu)->crs_len) + (off));
610 else
611 return ~0ULL;
588b34be
DA		 612}
613
614static inline u32 cxl_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off)
615{
0b3f9c75
DA		 616 if (likely(cxl_adapter_link_ok(afu->adapter)))
617 return in_le32((afu)->afu_desc_mmio + (afu)->crs_offset +
618 ((cr) * (afu)->crs_len) + (off));
619 else
620 return 0xffffffff;
588b34be 621}
b087e619
IM		 622u16 cxl_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off);
623u8 cxl_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off);
624
e36f6fe1
VJ		 625ssize_t cxl_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
626 loff_t off, size_t count);
627
b087e619 628
f204e0b8
IM		 629struct cxl_calls {
630 void (*cxl_slbia)(struct mm_struct *mm);
631 struct module *owner;
632};
633int register_cxl_calls(struct cxl_calls *calls);
634void unregister_cxl_calls(struct cxl_calls *calls);
635
636int cxl_alloc_adapter_nr(struct cxl *adapter);
637void cxl_remove_adapter_nr(struct cxl *adapter);
638
05155772
DA		 639int cxl_alloc_spa(struct cxl_afu *afu);
640void cxl_release_spa(struct cxl_afu *afu);
641
f204e0b8
IM		 642int cxl_file_init(void);
643void cxl_file_exit(void);
644int cxl_register_adapter(struct cxl *adapter);
645int cxl_register_afu(struct cxl_afu *afu);
646int cxl_chardev_d_afu_add(struct cxl_afu *afu);
647int cxl_chardev_m_afu_add(struct cxl_afu *afu);
648int cxl_chardev_s_afu_add(struct cxl_afu *afu);
649void cxl_chardev_afu_remove(struct cxl_afu *afu);
650
651void cxl_context_detach_all(struct cxl_afu *afu);
652void cxl_context_free(struct cxl_context *ctx);
653void cxl_context_detach(struct cxl_context *ctx);
654
655int cxl_sysfs_adapter_add(struct cxl *adapter);
656void cxl_sysfs_adapter_remove(struct cxl *adapter);
657int cxl_sysfs_afu_add(struct cxl_afu *afu);
658void cxl_sysfs_afu_remove(struct cxl_afu *afu);
659int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
660void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
661
662int cxl_afu_activate_mode(struct cxl_afu *afu, int mode);
663int _cxl_afu_deactivate_mode(struct cxl_afu *afu, int mode);
664int cxl_afu_deactivate_mode(struct cxl_afu *afu);
665int cxl_afu_select_best_mode(struct cxl_afu *afu);
666
f204e0b8
IM		 667int cxl_register_psl_irq(struct cxl_afu *afu);
668void cxl_release_psl_irq(struct cxl_afu *afu);
669int cxl_register_psl_err_irq(struct cxl *adapter);
670void cxl_release_psl_err_irq(struct cxl *adapter);
671int cxl_register_serr_irq(struct cxl_afu *afu);
672void cxl_release_serr_irq(struct cxl_afu *afu);
673int afu_register_irqs(struct cxl_context *ctx, u32 count);
6428832a 674void afu_release_irqs(struct cxl_context *ctx, void *cookie);
f204e0b8
IM		 675irqreturn_t cxl_slice_irq_err(int irq, void *data);
676
677int cxl_debugfs_init(void);
678void cxl_debugfs_exit(void);
679int cxl_debugfs_adapter_add(struct cxl *adapter);
680void cxl_debugfs_adapter_remove(struct cxl *adapter);
681int cxl_debugfs_afu_add(struct cxl_afu *afu);
682void cxl_debugfs_afu_remove(struct cxl_afu *afu);
683
684void cxl_handle_fault(struct work_struct *work);
685void cxl_prefault(struct cxl_context *ctx, u64 wed);
686
687struct cxl *get_cxl_adapter(int num);
688int cxl_alloc_sst(struct cxl_context *ctx);
689
690void init_cxl_native(void);
691
692struct cxl_context *cxl_context_alloc(void);
b123429e
IM		 693int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master,
694 struct address_space *mapping);
f204e0b8
IM		 695void cxl_context_free(struct cxl_context *ctx);
696int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
1a1a94b8
MN		 697unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
698 irq_handler_t handler, void *cookie, const char *name);
699void cxl_unmap_irq(unsigned int virq, void *cookie);
eda3693c 700int __detach_context(struct cxl_context *ctx);
f204e0b8
IM		 701
702/* This matches the layout of the H_COLLECT_CA_INT_INFO retbuf */
703struct cxl_irq_info {
704 u64 dsisr;
705 u64 dar;
706 u64 dsr;
707 u32 pid;
708 u32 tid;
709 u64 afu_err;
710 u64 errstat;
711 u64 padding[3]; /* to match the expected retbuf size for plpar_hcall9 */
712};
713
1a1a94b8 714void cxl_assign_psn_space(struct cxl_context *ctx);
f204e0b8
IM		 715int cxl_attach_process(struct cxl_context *ctx, bool kernel, u64 wed,
716 u64 amr);
717int cxl_detach_process(struct cxl_context *ctx);
718
bc78b05b 719int cxl_get_irq(struct cxl_afu *afu, struct cxl_irq_info *info);
f204e0b8
IM		 720int cxl_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
721
722int cxl_check_error(struct cxl_afu *afu);
723int cxl_afu_slbia(struct cxl_afu *afu);
724int cxl_tlb_slb_invalidate(struct cxl *adapter);
725int cxl_afu_disable(struct cxl_afu *afu);
b12994fb 726int __cxl_afu_reset(struct cxl_afu *afu);
1a1a94b8 727int cxl_afu_check_and_enable(struct cxl_afu *afu);
f204e0b8
IM		 728int cxl_psl_purge(struct cxl_afu *afu);
729
730void cxl_stop_trace(struct cxl *cxl);
6f7f0b3d 731int cxl_pci_vphb_add(struct cxl_afu *afu);
9e8df8a2 732void cxl_pci_vphb_reconfigure(struct cxl_afu *afu);
6f7f0b3d 733void cxl_pci_vphb_remove(struct cxl_afu *afu);
f204e0b8
IM		 734
735extern struct pci_driver cxl_pci_driver;
c358d84b 736int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
f204e0b8 737
0520336a
MN		 738int afu_open(struct inode *inode, struct file *file);
739int afu_release(struct inode *inode, struct file *file);
740long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
741int afu_mmap(struct file *file, struct vm_area_struct *vm);
742unsigned int afu_poll(struct file *file, struct poll_table_struct *poll);
743ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
744extern const struct file_operations afu_fops;
745
f204e0b8 746#endif
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