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1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#ifndef _CXL_H_
11#define _CXL_H_
12
13#include <linux/interrupt.h>
14#include <linux/semaphore.h>
15#include <linux/device.h>
16#include <linux/types.h>
17#include <linux/cdev.h>
18#include <linux/pid.h>
19#include <linux/io.h>
20#include <linux/pci.h>
0520336a 21#include <linux/fs.h>
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22#include <asm/cputable.h>
23#include <asm/mmu.h>
24#include <asm/reg.h>
ec249dd8 25#include <misc/cxl-base.h>
f204e0b8 26
b810253b 27#include <misc/cxl.h>
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28#include <uapi/misc/cxl.h>
29
30extern uint cxl_verbose;
31
32#define CXL_TIMEOUT 5
33
34/*
35 * Bump version each time a user API change is made, whether it is
36 * backwards compatible ot not.
37 */
b810253b 38#define CXL_API_VERSION 3
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39#define CXL_API_VERSION_COMPATIBLE 1
40
41/*
42 * Opaque types to avoid accidentally passing registers for the wrong MMIO
43 *
44 * At the end of the day, I'm not married to using typedef here, but it might
45 * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
46 * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
47 *
48 * I'm quite happy if these are changed back to #defines before upstreaming, it
49 * should be little more than a regexp search+replace operation in this file.
50 */
51typedef struct {
52 const int x;
53} cxl_p1_reg_t;
54typedef struct {
55 const int x;
56} cxl_p1n_reg_t;
57typedef struct {
58 const int x;
59} cxl_p2n_reg_t;
60#define cxl_reg_off(reg) \
61 (reg.x)
62
63/* Memory maps. Ref CXL Appendix A */
64
65/* PSL Privilege 1 Memory Map */
66/* Configuration and Control area */
67static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
68static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
69static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010};
70static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018};
71static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
72/* Downloading */
73static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060};
74static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068};
75
76/* PSL Lookaside Buffer Management Area */
77static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080};
78static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088};
79static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090};
80static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0};
81static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8};
82static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0};
83
84/* 0x00C0:7EFF Implementation dependent area */
6d382616 85/* PSL registers */
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86static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100};
87static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108};
390fd592 88static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110};
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89static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118};
90static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128};
390fd592 91static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
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92static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148};
93static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150};
94static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
95static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170};
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96/* XSL registers (Mellanox CX4) */
97static const cxl_p1_reg_t CXL_XSL_Timebase = {0x0100};
98static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108};
99static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};
100static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168};
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101/* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
102/* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
103
104/* PSL Slice Privilege 1 Memory Map */
105/* Configuration Area */
106static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00};
107static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08};
108static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10};
109static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18};
110static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20};
111static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28};
112/* Memory Management and Lookaside Buffer Management */
113static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30};
114static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38};
115/* Pointer Area */
116static const cxl_p1n_reg_t CXL_HAURP_An = {0x80};
117static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88};
118static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90};
119/* Control Area */
120static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0};
121static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8};
122static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
123static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8};
124/* 0xC0:FF Implementation Dependent Area */
125static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0};
126static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8};
127static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0};
128static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8};
129static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0};
130static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8};
131
132/* PSL Slice Privilege 2 Memory Map */
133/* Configuration and Control Area */
134static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
135static const cxl_p2n_reg_t CXL_CSRP_An = {0x008};
136static const cxl_p2n_reg_t CXL_AURP0_An = {0x010};
137static const cxl_p2n_reg_t CXL_AURP1_An = {0x018};
138static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020};
139static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028};
140static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030};
141/* Segment Lookaside Buffer Management */
142static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040};
143static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048};
144static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
145/* Interrupt Registers */
146static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060};
147static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068};
148static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070};
149static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078};
150static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
151static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
152/* AFU Registers */
153static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090};
154static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098};
155/* Work Element Descriptor */
156static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
157/* 0x0C0:FFF Implementation Dependent Area */
158
159#define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
160#define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
161#define CXL_PSL_SPAP_Size_Shift 4
162#define CXL_PSL_SPAP_V 0x0000000000000001ULL
163
390fd592 164/****** CXL_PSL_Control ****************************************************/
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165#define CXL_PSL_Control_tb (0x1ull << (63-63))
166#define CXL_PSL_Control_Fr (0x1ull << (63-31))
167#define CXL_PSL_Control_Fs_MASK (0x3ull << (63-29))
168#define CXL_PSL_Control_Fs_Complete (0x3ull << (63-29))
390fd592 169
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170/****** CXL_PSL_DLCNTL *****************************************************/
171#define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
172#define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
173#define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
174#define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
175#define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
176#define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
177
178/****** CXL_PSL_SR_An ******************************************************/
179#define CXL_PSL_SR_An_SF MSR_SF /* 64bit */
180#define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
181#define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */
182#define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */
183#define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
184#define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
185#define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
186#define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
187#define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */
188#define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
189#define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
190
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191/****** CXL_PSL_ID_An ****************************************************/
192#define CXL_PSL_ID_An_F (1ull << (63-31))
193#define CXL_PSL_ID_An_L (1ull << (63-30))
194
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195/****** CXL_PSL_SERR_An ****************************************************/
196#define CXL_PSL_SERR_An_afuto (1ull << (63-0))
197#define CXL_PSL_SERR_An_afudis (1ull << (63-1))
198#define CXL_PSL_SERR_An_afuov (1ull << (63-2))
199#define CXL_PSL_SERR_An_badsrc (1ull << (63-3))
200#define CXL_PSL_SERR_An_badctx (1ull << (63-4))
201#define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
202#define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
203#define CXL_PSL_SERR_An_afupar (1ull << (63-7))
204#define CXL_PSL_SERR_An_afudup (1ull << (63-8))
205#define CXL_PSL_SERR_An_AE (1ull << (63-30))
206
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207/****** CXL_PSL_SCNTL_An ****************************************************/
208#define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15))
209/* Programming Modes: */
210#define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31))
211#define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31))
212#define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31))
213#define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31))
214#define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31))
215#define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31))
216/* Purge Status (ro) */
217#define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39))
218#define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39))
219#define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
220/* Purge */
221#define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48))
222/* Suspend Status (ro) */
223#define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55))
224#define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55))
225#define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
226/* Suspend Control */
227#define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63))
228
229/* AFU Slice Enable Status (ro) */
230#define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2))
231#define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
232#define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2))
233/* AFU Slice Enable */
234#define CXL_AFU_Cntl_An_E (0x1ull << (63-3))
235/* AFU Slice Reset status (ro) */
236#define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5))
237#define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5))
238#define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
239/* AFU Slice Reset */
240#define CXL_AFU_Cntl_An_RA (0x1ull << (63-7))
241
242/****** CXL_SSTP0/1_An ******************************************************/
243/* These top bits are for the segment that CONTAINS the segment table */
244#define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT
245#define CXL_SSTP0_An_KS (1ull << (63-2))
246#define CXL_SSTP0_An_KP (1ull << (63-3))
247#define CXL_SSTP0_An_N (1ull << (63-4))
248#define CXL_SSTP0_An_L (1ull << (63-5))
249#define CXL_SSTP0_An_C (1ull << (63-6))
250#define CXL_SSTP0_An_TA (1ull << (63-7))
251#define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */
252/* And finally, the virtual address & size of the segment table: */
253#define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */
254#define CXL_SSTP0_An_SegTableSize_MASK \
255 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
256#define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
257#define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
258#define CXL_SSTP1_An_V (1ull << (63-63))
259
260/****** CXL_PSL_SLBIE_[An] **************************************************/
261/* write: */
262#define CXL_SLBIE_C PPC_BIT(36) /* Class */
263#define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */
264#define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
265#define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */
266/* read: */
267#define CXL_SLBIE_MAX PPC_BITMASK(24, 31)
268#define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)
269
270/****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/
271#define CXL_TLB_SLB_P (1ull) /* Pending (read) */
272
273/****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/
274#define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */
275#define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */
276#define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
277
278/****** CXL_PSL_AFUSEL ******************************************************/
279#define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
280
281/****** CXL_PSL_DSISR_An ****************************************************/
282#define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
283#define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
284#define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
285#define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
286#define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
287#define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
288#define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
289#define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
2bc79ffc 290#define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
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291/* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
292#define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */
293#define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */
294#define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
295#define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */
296#define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */
297
298/****** CXL_PSL_TFC_An ******************************************************/
299#define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
300#define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
301#define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
302#define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
303
304/* cxl_process_element->software_status */
305#define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */
306#define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
307#define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
308#define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
309
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310/****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
311 * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
312 * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
313 * of the hang pulse frequency.
314 */
315#define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL
316
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317/* SPA->sw_command_status */
318#define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL
319#define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL
320#define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL
321#define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL
322#define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL
323#define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL
324#define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL
325#define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL
326#define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
327#define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL
328#define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL
329#define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL
330#define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL
331#define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL
332#define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL
333#define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL
334
335#define CXL_MAX_SLICES 4
336#define MAX_AFU_MMIO_REGS 3
337
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338#define CXL_MODE_TIME_SLICED 0x4
339#define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
340
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341#define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
342#define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
343#define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
344
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345enum cxl_context_status {
346 CLOSED,
347 OPENED,
348 STARTED
349};
350
351enum prefault_modes {
352 CXL_PREFAULT_NONE,
353 CXL_PREFAULT_WED,
354 CXL_PREFAULT_ALL,
355};
356
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357enum cxl_attrs {
358 CXL_ADAPTER_ATTRS,
359 CXL_AFU_MASTER_ATTRS,
360 CXL_AFU_ATTRS,
361};
362
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363struct cxl_sste {
364 __be64 esid_data;
365 __be64 vsid_data;
366};
367
368#define to_cxl_adapter(d) container_of(d, struct cxl, dev)
369#define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
370
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371struct cxl_afu_native {
372 void __iomem *p1n_mmio;
373 void __iomem *afu_desc_mmio;
f204e0b8 374 irq_hw_number_t psl_hwirq;
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375 unsigned int psl_virq;
376 struct mutex spa_mutex;
377 /*
378 * Only the first part of the SPA is used for the process element
379 * linked list. The only other part that software needs to worry about
380 * is sw_command_status, which we store a separate pointer to.
381 * Everything else in the SPA is only used by hardware
382 */
383 struct cxl_process_element *spa;
384 __be64 *sw_command_status;
385 unsigned int spa_size;
386 int spa_order;
387 int spa_max_procs;
388 u64 pp_offset;
389};
390
391struct cxl_afu_guest {
266eab8f 392 struct cxl_afu *parent;
cbffa3a5
CL
393 u64 handle;
394 phys_addr_t p2n_phys;
395 u64 p2n_size;
396 int max_ints;
266eab8f
CL
397 bool handle_err;
398 struct delayed_work work_err;
0d400f77 399 int previous_state;
cbffa3a5
CL
400};
401
402struct cxl_afu {
403 struct cxl_afu_native *native;
404 struct cxl_afu_guest *guest;
f204e0b8
IM
405 irq_hw_number_t serr_hwirq;
406 unsigned int serr_virq;
cbffa3a5
CL
407 char *psl_irq_name;
408 char *err_irq_name;
f204e0b8
IM
409 void __iomem *p2n_mmio;
410 phys_addr_t psn_phys;
f204e0b8 411 u64 pp_size;
cbffa3a5 412
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413 struct cxl *adapter;
414 struct device dev;
415 struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
416 struct device *chardev_s, *chardev_m, *chardev_d;
417 struct idr contexts_idr;
418 struct dentry *debugfs;
ee41d11d 419 struct mutex contexts_lock;
f204e0b8
IM
420 spinlock_t afu_cntl_lock;
421
e36f6fe1
VJ
422 /* AFU error buffer fields and bin attribute for sysfs */
423 u64 eb_len, eb_offset;
424 struct bin_attribute attr_eb;
425
6f7f0b3d
MN
426 /* pointer to the vphb */
427 struct pci_controller *phb;
428
f204e0b8
IM
429 int pp_irqs;
430 int irqs_max;
431 int num_procs;
432 int max_procs_virtualised;
433 int slice;
434 int modes_supported;
435 int current_mode;
b087e619
IM
436 int crs_num;
437 u64 crs_len;
438 u64 crs_offset;
439 struct list_head crs;
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IM
440 enum prefault_modes prefault_mode;
441 bool psa;
442 bool pp_psa;
443 bool enabled;
444};
445
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MN
446
447struct cxl_irq_name {
448 struct list_head list;
449 char *name;
450};
451
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CL
452struct irq_avail {
453 irq_hw_number_t offset;
454 irq_hw_number_t range;
455 unsigned long *bitmap;
456};
457
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IM
458/*
459 * This is a cxl context. If the PSL is in dedicated mode, there will be one
460 * of these per AFU. If in AFU directed there can be lots of these.
461 */
462struct cxl_context {
463 struct cxl_afu *afu;
464
465 /* Problem state MMIO */
466 phys_addr_t psn_phys;
467 u64 psn_size;
468
b123429e
IM
469 /* Used to unmap any mmaps when force detaching */
470 struct address_space *mapping;
471 struct mutex mapping_lock;
d9232a3d
IM
472 struct page *ff_page;
473 bool mmio_err_ff;
55e07668 474 bool kernelapi;
b123429e 475
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IM
476 spinlock_t sste_lock; /* Protects segment table entries */
477 struct cxl_sste *sstp;
478 u64 sstp0, sstp1;
479 unsigned int sst_size, sst_lru;
480
481 wait_queue_head_t wq;
7b8ad495
VJ
482 /* pid of the group leader associated with the pid */
483 struct pid *glpid;
484 /* use mm context associated with this pid for ds faults */
f204e0b8
IM
485 struct pid *pid;
486 spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
487 /* Only used in PR mode */
488 u64 process_token;
489
ad42de85
MN
490 /* driver private data */
491 void *priv;
492
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IM
493 unsigned long *irq_bitmap; /* Accessed from IRQ context */
494 struct cxl_irq_ranges irqs;
80fa93fc 495 struct list_head irq_names;
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IM
496 u64 fault_addr;
497 u64 fault_dsisr;
498 u64 afu_err;
499
500 /*
501 * This status and it's lock pretects start and detach context
502 * from racing. It also prevents detach from racing with
503 * itself
504 */
505 enum cxl_context_status status;
506 struct mutex status_mutex;
507
508
509 /* XXX: Is it possible to need multiple work items at once? */
510 struct work_struct fault_work;
511 u64 dsisr;
512 u64 dar;
513
514 struct cxl_process_element *elem;
515
14baf4d9
CL
516 /*
517 * pe is the process element handle, assigned by this driver when the
518 * context is initialized.
519 *
520 * external_pe is the PE shown outside of cxl.
521 * On bare-metal, pe=external_pe, because we decide what the handle is.
522 * In a guest, we only find out about the pe used by pHyp when the
523 * context is attached, and that's the value we want to report outside
524 * of cxl.
525 */
526 int pe;
527 int external_pe;
528
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IM
529 u32 irq_count;
530 bool pe_inserted;
531 bool master;
532 bool kernel;
7a0d85d3 533 bool real_mode;
f204e0b8
IM
534 bool pending_irq;
535 bool pending_fault;
536 bool pending_afu_err;
8ac75b96 537
b810253b
PB
538 /* Used by AFU drivers for driver specific event delivery */
539 struct cxl_afu_driver_ops *afu_driver_ops;
540 atomic_t afu_driver_events;
541
8ac75b96 542 struct rcu_head rcu;
cbce0917
IM
543
544 /*
545 * Only used when more interrupts are allocated via
546 * pci_enable_msix_range than are supported in the default context, to
547 * use additional contexts to overcome the limitation. i.e. Mellanox
548 * CX4 only:
549 */
550 struct list_head extra_irq_contexts;
f204e0b8
IM
551};
552
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FB
553struct cxl_service_layer_ops {
554 int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
555 int (*afu_regs_init)(struct cxl_afu *afu);
556 int (*register_serr_irq)(struct cxl_afu *afu);
557 void (*release_serr_irq)(struct cxl_afu *afu);
558 void (*debugfs_add_adapter_sl_regs)(struct cxl *adapter, struct dentry *dir);
559 void (*debugfs_add_afu_sl_regs)(struct cxl_afu *afu, struct dentry *dir);
560 void (*psl_irq_dump_registers)(struct cxl_context *ctx);
561 void (*err_irq_dump_registers)(struct cxl *adapter);
562 void (*debugfs_stop_trace)(struct cxl *adapter);
563 void (*write_timebase_ctrl)(struct cxl *adapter);
564 u64 (*timebase_read)(struct cxl *adapter);
b385c9e9 565 int capi_mode;
5e7823c9 566 bool needs_reset_before_disable;
6d382616
FB
567};
568
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569struct cxl_native {
570 u64 afu_desc_off;
571 u64 afu_desc_size;
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IM
572 void __iomem *p1_mmio;
573 void __iomem *p2_mmio;
574 irq_hw_number_t err_hwirq;
575 unsigned int err_virq;
cbffa3a5 576 u64 ps_off;
6d382616 577 const struct cxl_service_layer_ops *sl_ops;
cbffa3a5
CL
578};
579
580struct cxl_guest {
581 struct platform_device *pdev;
582 int irq_nranges;
583 struct cdev cdev;
584 irq_hw_number_t irq_base_offset;
585 struct irq_avail *irq_avail;
586 spinlock_t irq_alloc_lock;
587 u64 handle;
588 char *status;
589 u16 vendor;
590 u16 device;
591 u16 subsystem_vendor;
592 u16 subsystem;
593};
594
595struct cxl {
596 struct cxl_native *native;
597 struct cxl_guest *guest;
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IM
598 spinlock_t afu_list_lock;
599 struct cxl_afu *afu[CXL_MAX_SLICES];
600 struct device dev;
601 struct dentry *trace;
602 struct dentry *psl_err_chk;
603 struct dentry *debugfs;
80fa93fc 604 char *irq_name;
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IM
605 struct bin_attribute cxl_attr;
606 int adapter_num;
607 int user_irqs;
16479337 608 int min_pe;
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IM
609 u64 ps_size;
610 u16 psl_rev;
611 u16 base_image;
612 u8 vsec_status;
613 u8 caia_major;
614 u8 caia_minor;
615 u8 slices;
616 bool user_image_loaded;
617 bool perst_loads_image;
618 bool perst_select_user;
13e68d8b 619 bool perst_same_image;
e009a7e8 620 bool psl_timebase_synced;
70b565bb
VJ
621
622 /*
623 * number of contexts mapped on to this card. Possible values are:
624 * >0: Number of contexts mapped and new one can be mapped.
625 * 0: No active contexts and new ones can be mapped.
626 * -1: No contexts mapped and new ones cannot be mapped.
627 */
628 atomic_t contexts_num;
f204e0b8
IM
629};
630
2b04cf31
FB
631int cxl_pci_alloc_one_irq(struct cxl *adapter);
632void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
633int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
634void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
635int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
4beb5421 636int cxl_update_image_control(struct cxl *adapter);
2b04cf31
FB
637int cxl_pci_reset(struct cxl *adapter);
638void cxl_pci_release_afu(struct device *dev);
d601ea91 639ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
f204e0b8
IM
640
641/* common == phyp + powernv */
642struct cxl_process_element_common {
643 __be32 tid;
644 __be32 pid;
645 __be64 csrp;
646 __be64 aurp0;
647 __be64 aurp1;
648 __be64 sstp0;
649 __be64 sstp1;
650 __be64 amr;
651 u8 reserved3[4];
652 __be64 wed;
653} __packed;
654
655/* just powernv */
656struct cxl_process_element {
657 __be64 sr;
658 __be64 SPOffset;
659 __be64 sdr;
660 __be64 haurp;
661 __be32 ctxtime;
662 __be16 ivte_offsets[4];
663 __be16 ivte_ranges[4];
664 __be32 lpid;
665 struct cxl_process_element_common common;
666 __be32 software_state;
667} __packed;
668
0d400f77 669static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
0b3f9c75
DA
670{
671 struct pci_dev *pdev;
672
ea2d1f95
FB
673 if (cpu_has_feature(CPU_FTR_HVMODE)) {
674 pdev = to_pci_dev(cxl->dev.parent);
675 return !pci_channel_offline(pdev);
676 }
677 return true;
0b3f9c75
DA
678}
679
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680static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
681{
682 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
cbffa3a5 683 return cxl->native->p1_mmio + cxl_reg_off(reg);
f204e0b8
IM
684}
685
588b34be
DA
686static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
687{
0d400f77 688 if (likely(cxl_adapter_link_ok(cxl, NULL)))
0b3f9c75 689 out_be64(_cxl_p1_addr(cxl, reg), val);
588b34be
DA
690}
691
692static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
693{
0d400f77 694 if (likely(cxl_adapter_link_ok(cxl, NULL)))
0b3f9c75
DA
695 return in_be64(_cxl_p1_addr(cxl, reg));
696 else
697 return ~0ULL;
588b34be 698}
f204e0b8
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699
700static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
701{
702 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
cbffa3a5 703 return afu->native->p1n_mmio + cxl_reg_off(reg);
f204e0b8
IM
704}
705
588b34be
DA
706static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
707{
0d400f77 708 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0b3f9c75 709 out_be64(_cxl_p1n_addr(afu, reg), val);
588b34be
DA
710}
711
712static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
713{
0d400f77 714 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0b3f9c75
DA
715 return in_be64(_cxl_p1n_addr(afu, reg));
716 else
717 return ~0ULL;
588b34be 718}
f204e0b8
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719
720static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
721{
722 return afu->p2n_mmio + cxl_reg_off(reg);
723}
724
588b34be
DA
725static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
726{
0d400f77 727 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0b3f9c75 728 out_be64(_cxl_p2n_addr(afu, reg), val);
588b34be 729}
f204e0b8 730
588b34be
DA
731static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
732{
0d400f77 733 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0b3f9c75
DA
734 return in_be64(_cxl_p2n_addr(afu, reg));
735 else
736 return ~0ULL;
588b34be 737}
b087e619 738
2b04cf31 739ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
e36f6fe1
VJ
740 loff_t off, size_t count);
741
a19bd79e
IM
742/* Internal functions wrapped in cxl_base to allow PHB to call them */
743bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu);
744void _cxl_pci_disable_device(struct pci_dev *dev);
cbce0917 745int _cxl_next_msi_hwirq(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
a2f67d5e
IM
746int _cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
747void _cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
b087e619 748
f204e0b8
IM
749struct cxl_calls {
750 void (*cxl_slbia)(struct mm_struct *mm);
a19bd79e
IM
751 bool (*cxl_pci_associate_default_context)(struct pci_dev *dev, struct cxl_afu *afu);
752 void (*cxl_pci_disable_device)(struct pci_dev *dev);
cbce0917 753 int (*cxl_next_msi_hwirq)(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
a2f67d5e
IM
754 int (*cxl_cx4_setup_msi_irqs)(struct pci_dev *pdev, int nvec, int type);
755 void (*cxl_cx4_teardown_msi_irqs)(struct pci_dev *pdev);
a19bd79e 756
f204e0b8
IM
757 struct module *owner;
758};
759int register_cxl_calls(struct cxl_calls *calls);
760void unregister_cxl_calls(struct cxl_calls *calls);
594ff7d0 761int cxl_update_properties(struct device_node *dn, struct property *new_prop);
f204e0b8 762
f204e0b8
IM
763void cxl_remove_adapter_nr(struct cxl *adapter);
764
05155772
DA
765int cxl_alloc_spa(struct cxl_afu *afu);
766void cxl_release_spa(struct cxl_afu *afu);
767
594ff7d0 768dev_t cxl_get_dev(void);
f204e0b8
IM
769int cxl_file_init(void);
770void cxl_file_exit(void);
771int cxl_register_adapter(struct cxl *adapter);
772int cxl_register_afu(struct cxl_afu *afu);
773int cxl_chardev_d_afu_add(struct cxl_afu *afu);
774int cxl_chardev_m_afu_add(struct cxl_afu *afu);
775int cxl_chardev_s_afu_add(struct cxl_afu *afu);
776void cxl_chardev_afu_remove(struct cxl_afu *afu);
777
778void cxl_context_detach_all(struct cxl_afu *afu);
779void cxl_context_free(struct cxl_context *ctx);
780void cxl_context_detach(struct cxl_context *ctx);
781
782int cxl_sysfs_adapter_add(struct cxl *adapter);
783void cxl_sysfs_adapter_remove(struct cxl *adapter);
784int cxl_sysfs_afu_add(struct cxl_afu *afu);
785void cxl_sysfs_afu_remove(struct cxl_afu *afu);
786int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
787void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
788
86331862
CL
789struct cxl *cxl_alloc_adapter(void);
790struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
f204e0b8
IM
791int cxl_afu_select_best_mode(struct cxl_afu *afu);
792
2b04cf31
FB
793int cxl_native_register_psl_irq(struct cxl_afu *afu);
794void cxl_native_release_psl_irq(struct cxl_afu *afu);
795int cxl_native_register_psl_err_irq(struct cxl *adapter);
796void cxl_native_release_psl_err_irq(struct cxl *adapter);
797int cxl_native_register_serr_irq(struct cxl_afu *afu);
798void cxl_native_release_serr_irq(struct cxl_afu *afu);
f204e0b8 799int afu_register_irqs(struct cxl_context *ctx, u32 count);
6428832a 800void afu_release_irqs(struct cxl_context *ctx, void *cookie);
8dde152e 801void afu_irq_name_free(struct cxl_context *ctx);
f204e0b8
IM
802
803int cxl_debugfs_init(void);
804void cxl_debugfs_exit(void);
805int cxl_debugfs_adapter_add(struct cxl *adapter);
806void cxl_debugfs_adapter_remove(struct cxl *adapter);
807int cxl_debugfs_afu_add(struct cxl_afu *afu);
808void cxl_debugfs_afu_remove(struct cxl_afu *afu);
809
810void cxl_handle_fault(struct work_struct *work);
811void cxl_prefault(struct cxl_context *ctx, u64 wed);
812
813struct cxl *get_cxl_adapter(int num);
814int cxl_alloc_sst(struct cxl_context *ctx);
444c4ba4 815void cxl_dump_debug_buffer(void *addr, size_t size);
f204e0b8
IM
816
817void init_cxl_native(void);
818
819struct cxl_context *cxl_context_alloc(void);
b123429e
IM
820int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master,
821 struct address_space *mapping);
f204e0b8
IM
822void cxl_context_free(struct cxl_context *ctx);
823int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
1a1a94b8
MN
824unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
825 irq_handler_t handler, void *cookie, const char *name);
826void cxl_unmap_irq(unsigned int virq, void *cookie);
eda3693c 827int __detach_context(struct cxl_context *ctx);
f204e0b8 828
444c4ba4
CL
829/*
830 * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
831 * in PAPR.
832 * A word about endianness: a pointer to this structure is passed when
833 * calling the hcall. However, it is not a block of memory filled up by
834 * the hypervisor. The return values are found in registers, and copied
835 * one by one when returning from the hcall. See the end of the call to
836 * plpar_hcall9() in hvCall.S
837 * As a consequence:
838 * - we don't need to do any endianness conversion
839 * - the pid and tid are an exception. They are 32-bit values returned in
840 * the same 64-bit register. So we do need to worry about byte ordering.
841 */
f204e0b8
IM
842struct cxl_irq_info {
843 u64 dsisr;
844 u64 dar;
845 u64 dsr;
444c4ba4 846#ifndef CONFIG_CPU_LITTLE_ENDIAN
f204e0b8
IM
847 u32 pid;
848 u32 tid;
444c4ba4
CL
849#else
850 u32 tid;
851 u32 pid;
852#endif
f204e0b8
IM
853 u64 afu_err;
854 u64 errstat;
444c4ba4
CL
855 u64 proc_handle;
856 u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
f204e0b8
IM
857};
858
1a1a94b8 859void cxl_assign_psn_space(struct cxl_context *ctx);
6d625ed9 860irqreturn_t cxl_irq(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
86331862
CL
861int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
862 void *cookie, irq_hw_number_t *dest_hwirq,
863 unsigned int *dest_virq, const char *name);
864
f204e0b8
IM
865int cxl_check_error(struct cxl_afu *afu);
866int cxl_afu_slbia(struct cxl_afu *afu);
867int cxl_tlb_slb_invalidate(struct cxl *adapter);
aaa2245e 868int cxl_data_cache_flush(struct cxl *adapter);
f204e0b8 869int cxl_afu_disable(struct cxl_afu *afu);
f204e0b8
IM
870int cxl_psl_purge(struct cxl_afu *afu);
871
6d382616
FB
872void cxl_debugfs_add_adapter_psl_regs(struct cxl *adapter, struct dentry *dir);
873void cxl_debugfs_add_adapter_xsl_regs(struct cxl *adapter, struct dentry *dir);
874void cxl_debugfs_add_afu_psl_regs(struct cxl_afu *afu, struct dentry *dir);
875void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx);
876void cxl_native_err_irq_dump_regs(struct cxl *adapter);
f204e0b8 877void cxl_stop_trace(struct cxl *cxl);
6f7f0b3d
MN
878int cxl_pci_vphb_add(struct cxl_afu *afu);
879void cxl_pci_vphb_remove(struct cxl_afu *afu);
f204e0b8
IM
880
881extern struct pci_driver cxl_pci_driver;
14baf4d9 882extern struct platform_driver cxl_of_driver;
c358d84b 883int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
f204e0b8 884
0520336a
MN
885int afu_open(struct inode *inode, struct file *file);
886int afu_release(struct inode *inode, struct file *file);
887long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
888int afu_mmap(struct file *file, struct vm_area_struct *vm);
889unsigned int afu_poll(struct file *file, struct poll_table_struct *poll);
890ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
891extern const struct file_operations afu_fops;
892
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893struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
894void cxl_guest_remove_adapter(struct cxl *adapter);
895int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
896int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
897ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
898ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
899int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
900void cxl_guest_remove_afu(struct cxl_afu *afu);
901int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
902int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
903int cxl_guest_add_chardev(struct cxl *adapter);
904void cxl_guest_remove_chardev(struct cxl *adapter);
905void cxl_guest_reload_module(struct cxl *adapter);
906int cxl_of_probe(struct platform_device *pdev);
907
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908struct cxl_backend_ops {
909 struct module *module;
910 int (*adapter_reset)(struct cxl *adapter);
911 int (*alloc_one_irq)(struct cxl *adapter);
912 void (*release_one_irq)(struct cxl *adapter, int hwirq);
913 int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
914 struct cxl *adapter, unsigned int num);
915 void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
916 struct cxl *adapter);
917 int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
918 unsigned int virq);
919 irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
920 u64 dsisr, u64 errstat);
921 irqreturn_t (*psl_interrupt)(int irq, void *data);
922 int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
2bc79ffc 923 void (*irq_wait)(struct cxl_context *ctx);
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924 int (*attach_process)(struct cxl_context *ctx, bool kernel,
925 u64 wed, u64 amr);
926 int (*detach_process)(struct cxl_context *ctx);
292841b0 927 void (*update_ivtes)(struct cxl_context *ctx);
4752876c 928 bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
0d400f77 929 bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
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930 void (*release_afu)(struct device *dev);
931 ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
932 loff_t off, size_t count);
933 int (*afu_check_and_enable)(struct cxl_afu *afu);
934 int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
935 int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
936 int (*afu_reset)(struct cxl_afu *afu);
937 int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
938 int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
939 int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
940 int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
d601ea91
FB
941 int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
942 int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
943 int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
944 ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
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945};
946extern const struct cxl_backend_ops cxl_native_ops;
14baf4d9 947extern const struct cxl_backend_ops cxl_guest_ops;
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948extern const struct cxl_backend_ops *cxl_ops;
949
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VJ
950/* check if the given pci_dev is on the the cxl vphb bus */
951bool cxl_pci_is_vphb_device(struct pci_dev *dev);
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PB
952
953/* decode AFU error bits in the PSL register PSL_SERR_An */
954void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
70b565bb
VJ
955
956/*
957 * Increments the number of attached contexts on an adapter.
958 * In case an adapter_context_lock is taken the return -EBUSY.
959 */
960int cxl_adapter_context_get(struct cxl *adapter);
961
962/* Decrements the number of attached contexts on an adapter */
963void cxl_adapter_context_put(struct cxl *adapter);
964
965/* If no active contexts then prevents contexts from being attached */
966int cxl_adapter_context_lock(struct cxl *adapter);
967
968/* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
969void cxl_adapter_context_unlock(struct cxl *adapter);
970
f204e0b8 971#endif