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cxl: Drop commands if the PCI channel is not in normal state
[mirror_ubuntu-zesty-kernel.git] / drivers / misc / cxl / native.c
CommitLineData
f204e0b8
IM		 1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/spinlock.h>
11#include <linux/sched.h>
12#include <linux/slab.h>
13#include <linux/sched.h>
14#include <linux/mutex.h>
15#include <linux/mm.h>
16#include <linux/uaccess.h>
17#include <asm/synch.h>
ec249dd8 18#include <misc/cxl-base.h>
f204e0b8
IM		 19
20#include "cxl.h"
9bcf28cd 21#include "trace.h"
f204e0b8
IM		 22
23static int afu_control(struct cxl_afu *afu, u64 command,
24 u64 result, u64 mask, bool enabled)
25{
26 u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
27 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
9bcf28cd 28 int rc = 0;
f204e0b8
IM		 29
30 spin_lock(&afu->afu_cntl_lock);
31 pr_devel("AFU command starting: %llx\n", command);
32
9bcf28cd
IM		 33 trace_cxl_afu_ctrl(afu, command);
34
f204e0b8
IM		 35 cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl | command);
36
37 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
38 while ((AFU_Cntl & mask) != result) {
39 if (time_after_eq(jiffies, timeout)) {
40 dev_warn(&afu->dev, "WARNING: AFU control timed out!\n");
9bcf28cd
IM		 41 rc = -EBUSY;
42 goto out;
f204e0b8 43 }
0b3f9c75
DA		 44
45 if (!cxl_adapter_link_ok(afu->adapter)) {
46 afu->enabled = enabled;
47 rc = -EIO;
48 goto out;
49 }
50
de369538 51 pr_devel_ratelimited("AFU control... (0x%016llx)\n",
f204e0b8
IM		 52 AFU_Cntl | command);
53 cpu_relax();
54 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
55 };
56 pr_devel("AFU command complete: %llx\n", command);
57 afu->enabled = enabled;
9bcf28cd
IM		 58out:
59 trace_cxl_afu_ctrl_done(afu, command, rc);
f204e0b8
IM		 60 spin_unlock(&afu->afu_cntl_lock);
61
9bcf28cd 62 return rc;
f204e0b8
IM		 63}
64
65static int afu_enable(struct cxl_afu *afu)
66{
67 pr_devel("AFU enable request\n");
68
69 return afu_control(afu, CXL_AFU_Cntl_An_E,
70 CXL_AFU_Cntl_An_ES_Enabled,
71 CXL_AFU_Cntl_An_ES_MASK, true);
72}
73
74int cxl_afu_disable(struct cxl_afu *afu)
75{
76 pr_devel("AFU disable request\n");
77
78 return afu_control(afu, 0, CXL_AFU_Cntl_An_ES_Disabled,
79 CXL_AFU_Cntl_An_ES_MASK, false);
80}
81
82/* This will disable as well as reset */
b12994fb 83int __cxl_afu_reset(struct cxl_afu *afu)
f204e0b8
IM		 84{
85 pr_devel("AFU reset request\n");
86
87 return afu_control(afu, CXL_AFU_Cntl_An_RA,
88 CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled,
89 CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK,
90 false);
91}
92
1a1a94b8 93int cxl_afu_check_and_enable(struct cxl_afu *afu)
f204e0b8 94{
0b3f9c75
DA		 95 if (!cxl_adapter_link_ok(afu->adapter)) {
96 WARN(1, "Refusing to enable afu while link down!\n");
97 return -EIO;
98 }
f204e0b8
IM		 99 if (afu->enabled)
100 return 0;
101 return afu_enable(afu);
102}
103
104int cxl_psl_purge(struct cxl_afu *afu)
105{
106 u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
107 u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
108 u64 dsisr, dar;
109 u64 start, end;
110 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
9bcf28cd
IM		 111 int rc = 0;
112
113 trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc);
f204e0b8
IM		 114
115 pr_devel("PSL purge request\n");
116
0b3f9c75
DA		 117 if (!cxl_adapter_link_ok(afu->adapter)) {
118 dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n");
119 rc = -EIO;
120 goto out;
121 }
122
f204e0b8
IM		 123 if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
124 WARN(1, "psl_purge request while AFU not disabled!\n");
125 cxl_afu_disable(afu);
126 }
127
128 cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
129 PSL_CNTL | CXL_PSL_SCNTL_An_Pc);
130 start = local_clock();
131 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
132 while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK)
133 == CXL_PSL_SCNTL_An_Ps_Pending) {
134 if (time_after_eq(jiffies, timeout)) {
135 dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n");
9bcf28cd
IM		 136 rc = -EBUSY;
137 goto out;
f204e0b8 138 }
0b3f9c75
DA		 139 if (!cxl_adapter_link_ok(afu->adapter)) {
140 rc = -EIO;
141 goto out;
142 }
143
f204e0b8 144 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
de369538 145 pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr);
f204e0b8
IM		 146 if (dsisr & CXL_PSL_DSISR_TRANS) {
147 dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
de369538 148 dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar);
f204e0b8
IM		 149 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
150 } else if (dsisr) {
de369538 151 dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr);
f204e0b8
IM		 152 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
153 } else {
154 cpu_relax();
155 }
156 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
157 };
158 end = local_clock();
159 pr_devel("PSL purged in %lld ns\n", end - start);
160
161 cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
162 PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc);
9bcf28cd
IM		 163out:
164 trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc);
165 return rc;
f204e0b8
IM		 166}
167
168static int spa_max_procs(int spa_size)
169{
170 /*
171 * From the CAIA:
172 * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255
173 * Most of that junk is really just an overly-complicated way of saying
174 * the last 256 bytes are __aligned(128), so it's really:
175 * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255
176 * and
177 * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1
178 * so
179 * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256
180 * Ignore the alignment (which is safe in this case as long as we are
181 * careful with our rounding) and solve for n:
182 */
183 return ((spa_size / 8) - 96) / 17;
184}
185
186static int alloc_spa(struct cxl_afu *afu)
187{
188 u64 spap;
189
190 /* Work out how many pages to allocate */
191 afu->spa_order = 0;
192 do {
193 afu->spa_order++;
194 afu->spa_size = (1 << afu->spa_order) * PAGE_SIZE;
195 afu->spa_max_procs = spa_max_procs(afu->spa_size);
196 } while (afu->spa_max_procs < afu->num_procs);
197
198 WARN_ON(afu->spa_size > 0x100000); /* Max size supported by the hardware */
199
200 if (!(afu->spa = (struct cxl_process_element *)
201 __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->spa_order))) {
202 pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n");
203 return -ENOMEM;
204 }
205 pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n",
206 1<<afu->spa_order, afu->spa_max_procs, afu->num_procs);
207
208 afu->sw_command_status = (__be64 *)((char *)afu->spa +
209 ((afu->spa_max_procs + 3) * 128));
210
211 spap = virt_to_phys(afu->spa) & CXL_PSL_SPAP_Addr;
212 spap |= ((afu->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size;
213 spap |= CXL_PSL_SPAP_V;
214 pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", afu->spa, afu->spa_max_procs, afu->sw_command_status, spap);
215 cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap);
216
217 return 0;
218}
219
220static void release_spa(struct cxl_afu *afu)
221{
db7933f3 222 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);
f204e0b8
IM		 223 free_pages((unsigned long) afu->spa, afu->spa_order);
224}
225
226int cxl_tlb_slb_invalidate(struct cxl *adapter)
227{
228 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
229
230 pr_devel("CXL adapter wide TLBIA & SLBIA\n");
231
232 cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A);
233
234 cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL);
235 while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) {
236 if (time_after_eq(jiffies, timeout)) {
237 dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n");
238 return -EBUSY;
239 }
0b3f9c75
DA		 240 if (!cxl_adapter_link_ok(adapter))
241 return -EIO;
f204e0b8
IM		 242 cpu_relax();
243 }
244
245 cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL);
246 while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) {
247 if (time_after_eq(jiffies, timeout)) {
248 dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n");
249 return -EBUSY;
250 }
0b3f9c75
DA		 251 if (!cxl_adapter_link_ok(adapter))
252 return -EIO;
f204e0b8
IM		 253 cpu_relax();
254 }
255 return 0;
256}
257
258int cxl_afu_slbia(struct cxl_afu *afu)
259{
260 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
261
262 pr_devel("cxl_afu_slbia issuing SLBIA command\n");
263 cxl_p2n_write(afu, CXL_SLBIA_An, CXL_TLB_SLB_IQ_ALL);
264 while (cxl_p2n_read(afu, CXL_SLBIA_An) & CXL_TLB_SLB_P) {
265 if (time_after_eq(jiffies, timeout)) {
266 dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n");
267 return -EBUSY;
268 }
0b3f9c75
DA		 269 /* If the adapter has gone down, we can assume that we
270 * will PERST it and that will invalidate everything.
271 */
272 if (!cxl_adapter_link_ok(afu->adapter))
273 return -EIO;
f204e0b8
IM		 274 cpu_relax();
275 }
276 return 0;
277}
278
279static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1)
280{
281 int rc;
282
283 /* 1. Disable SSTP by writing 0 to SSTP1[V] */
284 cxl_p2n_write(afu, CXL_SSTP1_An, 0);
285
286 /* 2. Invalidate all SLB entries */
287 if ((rc = cxl_afu_slbia(afu)))
288 return rc;
289
290 /* 3. Set SSTP0_An */
291 cxl_p2n_write(afu, CXL_SSTP0_An, sstp0);
292
293 /* 4. Set SSTP1_An */
294 cxl_p2n_write(afu, CXL_SSTP1_An, sstp1);
295
296 return 0;
297}
298
299/* Using per slice version may improve performance here. (ie. SLBIA_An) */
300static void slb_invalid(struct cxl_context *ctx)
301{
302 struct cxl *adapter = ctx->afu->adapter;
303 u64 slbia;
304
305 WARN_ON(!mutex_is_locked(&ctx->afu->spa_mutex));
306
307 cxl_p1_write(adapter, CXL_PSL_LBISEL,
308 ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) |
309 be32_to_cpu(ctx->elem->lpid));
310 cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID);
311
312 while (1) {
0b3f9c75
DA		 313 if (!cxl_adapter_link_ok(adapter))
314 break;
f204e0b8
IM		 315 slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA);
316 if (!(slbia & CXL_TLB_SLB_P))
317 break;
318 cpu_relax();
319 }
320}
321
322static int do_process_element_cmd(struct cxl_context *ctx,
323 u64 cmd, u64 pe_state)
324{
325 u64 state;
a98e6e9f 326 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
9bcf28cd
IM		 327 int rc = 0;
328
329 trace_cxl_llcmd(ctx, cmd);
f204e0b8
IM		 330
331 WARN_ON(!ctx->afu->enabled);
332
333 ctx->elem->software_state = cpu_to_be32(pe_state);
334 smp_wmb();
335 *(ctx->afu->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
336 smp_mb();
337 cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
338 while (1) {
a98e6e9f
IM		 339 if (time_after_eq(jiffies, timeout)) {
340 dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n");
9bcf28cd
IM		 341 rc = -EBUSY;
342 goto out;
a98e6e9f 343 }
0b3f9c75
DA		 344 if (!cxl_adapter_link_ok(ctx->afu->adapter)) {
345 dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n");
346 rc = -EIO;
347 goto out;
348 }
f204e0b8
IM		 349 state = be64_to_cpup(ctx->afu->sw_command_status);
350 if (state == ~0ULL) {
351 pr_err("cxl: Error adding process element to AFU\n");
9bcf28cd
IM		 352 rc = -1;
353 goto out;
f204e0b8
IM		 354 }
355 if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) ==
356 (cmd | (cmd >> 16) | ctx->pe))
357 break;
358 /*
359 * The command won't finish in the PSL if there are
360 * outstanding DSIs. Hence we need to yield here in
361 * case there are outstanding DSIs that we need to
362 * service. Tuning possiblity: we could wait for a
363 * while before sched
364 */
365 schedule();
366
367 }
9bcf28cd
IM		 368out:
369 trace_cxl_llcmd_done(ctx, cmd, rc);
370 return rc;
f204e0b8
IM		 371}
372
373static int add_process_element(struct cxl_context *ctx)
374{
375 int rc = 0;
376
377 mutex_lock(&ctx->afu->spa_mutex);
378 pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
379 if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V)))
380 ctx->pe_inserted = true;
381 pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
382 mutex_unlock(&ctx->afu->spa_mutex);
383 return rc;
384}
385
386static int terminate_process_element(struct cxl_context *ctx)
387{
388 int rc = 0;
389
390 /* fast path terminate if it's already invalid */
391 if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V)))
392 return rc;
393
394 mutex_lock(&ctx->afu->spa_mutex);
395 pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
0b3f9c75
DA		 396 /* We could be asked to terminate when the hw is down. That
397 * should always succeed: it's not running if the hw has gone
398 * away and is being reset.
399 */
400 if (cxl_adapter_link_ok(ctx->afu->adapter))
401 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,
402 CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T);
f204e0b8
IM		 403 ctx->elem->software_state = 0; /* Remove Valid bit */
404 pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
405 mutex_unlock(&ctx->afu->spa_mutex);
406 return rc;
407}
408
409static int remove_process_element(struct cxl_context *ctx)
410{
411 int rc = 0;
412
413 mutex_lock(&ctx->afu->spa_mutex);
414 pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
0b3f9c75
DA		 415
416 /* We could be asked to remove when the hw is down. Again, if
417 * the hw is down, the PE is gone, so we succeed.
418 */
419 if (cxl_adapter_link_ok(ctx->afu->adapter))
420 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0);
421
422 if (!rc)
f204e0b8
IM		 423 ctx->pe_inserted = false;
424 slb_invalid(ctx);
425 pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
426 mutex_unlock(&ctx->afu->spa_mutex);
427
428 return rc;
429}
430
431
1a1a94b8 432void cxl_assign_psn_space(struct cxl_context *ctx)
f204e0b8
IM		 433{
434 if (!ctx->afu->pp_size || ctx->master) {
435 ctx->psn_phys = ctx->afu->psn_phys;
436 ctx->psn_size = ctx->afu->adapter->ps_size;
437 } else {
438 ctx->psn_phys = ctx->afu->psn_phys +
439 (ctx->afu->pp_offset + ctx->afu->pp_size * ctx->pe);
440 ctx->psn_size = ctx->afu->pp_size;
441 }
442}
443
444static int activate_afu_directed(struct cxl_afu *afu)
445{
446 int rc;
447
448 dev_info(&afu->dev, "Activating AFU directed mode\n");
449
450 if (alloc_spa(afu))
451 return -ENOMEM;
452
453 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);
454 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
455 cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
456
457 afu->current_mode = CXL_MODE_DIRECTED;
458 afu->num_procs = afu->max_procs_virtualised;
459
460 if ((rc = cxl_chardev_m_afu_add(afu)))
461 return rc;
462
463 if ((rc = cxl_sysfs_afu_m_add(afu)))
464 goto err;
465
466 if ((rc = cxl_chardev_s_afu_add(afu)))
467 goto err1;
468
469 return 0;
470err1:
471 cxl_sysfs_afu_m_remove(afu);
472err:
473 cxl_chardev_afu_remove(afu);
474 return rc;
475}
476
477#ifdef CONFIG_CPU_LITTLE_ENDIAN
478#define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE)
479#else
480#define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
481#endif
482
2f663527
MN		 483static u64 calculate_sr(struct cxl_context *ctx)
484{
485 u64 sr = 0;
486
487 if (ctx->master)
488 sr |= CXL_PSL_SR_An_MP;
489 if (mfspr(SPRN_LPCR) & LPCR_TC)
490 sr |= CXL_PSL_SR_An_TC;
491 if (ctx->kernel) {
492 sr |= CXL_PSL_SR_An_R | (mfmsr() & MSR_SF);
493 sr |= CXL_PSL_SR_An_HV;
494 } else {
495 sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
496 set_endian(sr);
497 sr &= ~(CXL_PSL_SR_An_HV);
498 if (!test_tsk_thread_flag(current, TIF_32BIT))
499 sr |= CXL_PSL_SR_An_SF;
500 }
501 return sr;
502}
503
f204e0b8
IM		 504static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)
505{
2f663527 506 u32 pid;
f204e0b8
IM		 507 int r, result;
508
1a1a94b8 509 cxl_assign_psn_space(ctx);
f204e0b8
IM		 510
511 ctx->elem->ctxtime = 0; /* disable */
512 ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
513 ctx->elem->haurp = 0; /* disable */
514 ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1));
515
2f663527
MN		 516 pid = current->pid;
517 if (ctx->kernel)
518 pid = 0;
f204e0b8 519 ctx->elem->common.tid = 0;
2f663527
MN		 520 ctx->elem->common.pid = cpu_to_be32(pid);
521
522 ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
f204e0b8
IM		 523
524 ctx->elem->common.csrp = 0; /* disable */
525 ctx->elem->common.aurp0 = 0; /* disable */
526 ctx->elem->common.aurp1 = 0; /* disable */
527
528 cxl_prefault(ctx, wed);
529
530 ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0);
531 ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1);
532
533 for (r = 0; r < CXL_IRQ_RANGES; r++) {
534 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
535 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
536 }
537
538 ctx->elem->common.amr = cpu_to_be64(amr);
539 ctx->elem->common.wed = cpu_to_be64(wed);
540
541 /* first guy needs to enable */
1a1a94b8 542 if ((result = cxl_afu_check_and_enable(ctx->afu)))
f204e0b8
IM		 543 return result;
544
368857c1 545 return add_process_element(ctx);
f204e0b8
IM		 546}
547
548static int deactivate_afu_directed(struct cxl_afu *afu)
549{
550 dev_info(&afu->dev, "Deactivating AFU directed mode\n");
551
552 afu->current_mode = 0;
553 afu->num_procs = 0;
554
555 cxl_sysfs_afu_m_remove(afu);
556 cxl_chardev_afu_remove(afu);
557
b12994fb 558 __cxl_afu_reset(afu);
f204e0b8
IM		 559 cxl_afu_disable(afu);
560 cxl_psl_purge(afu);
561
562 release_spa(afu);
563
564 return 0;
565}
566
567static int activate_dedicated_process(struct cxl_afu *afu)
568{
569 dev_info(&afu->dev, "Activating dedicated process mode\n");
570
571 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
572
573 cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */
574 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */
575 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
576 cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID));
577 cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */
578 cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1));
579
580 cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */
581 cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */
582 cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */
583
584 afu->current_mode = CXL_MODE_DEDICATED;
585 afu->num_procs = 1;
586
587 return cxl_chardev_d_afu_add(afu);
588}
589
590static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr)
591{
592 struct cxl_afu *afu = ctx->afu;
2f663527 593 u64 pid;
f204e0b8
IM		 594 int rc;
595
2f663527
MN		 596 pid = (u64)current->pid << 32;
597 if (ctx->kernel)
598 pid = 0;
599 cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid);
600
601 cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx));
f204e0b8
IM		 602
603 if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
604 return rc;
605
606 cxl_prefault(ctx, wed);
607
608 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An,
609 (((u64)ctx->irqs.offset[0] & 0xffff) << 48) |
610 (((u64)ctx->irqs.offset[1] & 0xffff) << 32) |
611 (((u64)ctx->irqs.offset[2] & 0xffff) << 16) |
612 ((u64)ctx->irqs.offset[3] & 0xffff));
613 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64)
614 (((u64)ctx->irqs.range[0] & 0xffff) << 48) |
615 (((u64)ctx->irqs.range[1] & 0xffff) << 32) |
616 (((u64)ctx->irqs.range[2] & 0xffff) << 16) |
617 ((u64)ctx->irqs.range[3] & 0xffff));
618
619 cxl_p2n_write(afu, CXL_PSL_AMR_An, amr);
620
621 /* master only context for dedicated */
1a1a94b8 622 cxl_assign_psn_space(ctx);
f204e0b8 623
b12994fb 624 if ((rc = __cxl_afu_reset(afu)))
f204e0b8
IM		 625 return rc;
626
627 cxl_p2n_write(afu, CXL_PSL_WED_An, wed);
628
629 return afu_enable(afu);
630}
631
632static int deactivate_dedicated_process(struct cxl_afu *afu)
633{
634 dev_info(&afu->dev, "Deactivating dedicated process mode\n");
635
636 afu->current_mode = 0;
637 afu->num_procs = 0;
638
639 cxl_chardev_afu_remove(afu);
640
641 return 0;
642}
643
644int _cxl_afu_deactivate_mode(struct cxl_afu *afu, int mode)
645{
646 if (mode == CXL_MODE_DIRECTED)
647 return deactivate_afu_directed(afu);
648 if (mode == CXL_MODE_DEDICATED)
649 return deactivate_dedicated_process(afu);
650 return 0;
651}
652
653int cxl_afu_deactivate_mode(struct cxl_afu *afu)
654{
655 return _cxl_afu_deactivate_mode(afu, afu->current_mode);
656}
657
658int cxl_afu_activate_mode(struct cxl_afu *afu, int mode)
659{
660 if (!mode)
661 return 0;
662 if (!(mode & afu->modes_supported))
663 return -EINVAL;
664
0b3f9c75
DA		 665 if (!cxl_adapter_link_ok(afu->adapter)) {
666 WARN(1, "Device link is down, refusing to activate!\n");
667 return -EIO;
668 }
669
f204e0b8
IM		 670 if (mode == CXL_MODE_DIRECTED)
671 return activate_afu_directed(afu);
672 if (mode == CXL_MODE_DEDICATED)
673 return activate_dedicated_process(afu);
674
675 return -EINVAL;
676}
677
678int cxl_attach_process(struct cxl_context *ctx, bool kernel, u64 wed, u64 amr)
679{
0b3f9c75
DA		 680 if (!cxl_adapter_link_ok(ctx->afu->adapter)) {
681 WARN(1, "Device link is down, refusing to attach process!\n");
682 return -EIO;
683 }
684
f204e0b8
IM		 685 ctx->kernel = kernel;
686 if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
687 return attach_afu_directed(ctx, wed, amr);
688
689 if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
690 return attach_dedicated(ctx, wed, amr);
691
692 return -EINVAL;
693}
694
695static inline int detach_process_native_dedicated(struct cxl_context *ctx)
696{
b12994fb 697 __cxl_afu_reset(ctx->afu);
f204e0b8
IM		 698 cxl_afu_disable(ctx->afu);
699 cxl_psl_purge(ctx->afu);
700 return 0;
701}
702
f204e0b8
IM		 703static inline int detach_process_native_afu_directed(struct cxl_context *ctx)
704{
705 if (!ctx->pe_inserted)
706 return 0;
707 if (terminate_process_element(ctx))
708 return -1;
709 if (remove_process_element(ctx))
710 return -1;
711
712 return 0;
713}
714
715int cxl_detach_process(struct cxl_context *ctx)
716{
9bcf28cd
IM		 717 trace_cxl_detach(ctx);
718
f204e0b8
IM		 719 if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
720 return detach_process_native_dedicated(ctx);
721
722 return detach_process_native_afu_directed(ctx);
723}
724
bc78b05b 725int cxl_get_irq(struct cxl_afu *afu, struct cxl_irq_info *info)
f204e0b8
IM		 726{
727 u64 pidtid;
728
0b3f9c75
DA		 729 /* If the adapter has gone away, we can't get any meaningful
730 * information.
731 */
732 if (!cxl_adapter_link_ok(afu->adapter))
733 return -EIO;
734
bc78b05b
IM		 735 info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
736 info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
737 info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);
738 pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An);
f204e0b8
IM		 739 info->pid = pidtid >> 32;
740 info->tid = pidtid & 0xffffffff;
bc78b05b
IM		 741 info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An);
742 info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
f204e0b8
IM		 743
744 return 0;
745}
746
747static void recover_psl_err(struct cxl_afu *afu, u64 errstat)
748{
749 u64 dsisr;
750
de369538 751 pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat);
f204e0b8
IM		 752
753 /* Clear PSL_DSISR[PE] */
754 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
755 cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE);
756
757 /* Write 1s to clear error status bits */
758 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat);
759}
760
761int cxl_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
762{
9bcf28cd 763 trace_cxl_psl_irq_ack(ctx, tfc);
f204e0b8
IM		 764 if (tfc)
765 cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc);
766 if (psl_reset_mask)
767 recover_psl_err(ctx->afu, psl_reset_mask);
768
769 return 0;
770}
771
772int cxl_check_error(struct cxl_afu *afu)
773{
774 return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL);
775}
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