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Commit | Line | Data |
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f204e0b8 IM |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/spinlock.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/sched.h> | |
14 | #include <linux/mutex.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/uaccess.h> | |
17 | #include <asm/synch.h> | |
ec249dd8 | 18 | #include <misc/cxl-base.h> |
f204e0b8 IM |
19 | |
20 | #include "cxl.h" | |
9bcf28cd | 21 | #include "trace.h" |
f204e0b8 IM |
22 | |
23 | static int afu_control(struct cxl_afu *afu, u64 command, | |
24 | u64 result, u64 mask, bool enabled) | |
25 | { | |
26 | u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
27 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
9bcf28cd | 28 | int rc = 0; |
f204e0b8 IM |
29 | |
30 | spin_lock(&afu->afu_cntl_lock); | |
31 | pr_devel("AFU command starting: %llx\n", command); | |
32 | ||
9bcf28cd IM |
33 | trace_cxl_afu_ctrl(afu, command); |
34 | ||
f204e0b8 IM |
35 | cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl | command); |
36 | ||
37 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
38 | while ((AFU_Cntl & mask) != result) { | |
39 | if (time_after_eq(jiffies, timeout)) { | |
40 | dev_warn(&afu->dev, "WARNING: AFU control timed out!\n"); | |
9bcf28cd IM |
41 | rc = -EBUSY; |
42 | goto out; | |
f204e0b8 | 43 | } |
0b3f9c75 | 44 | |
0d400f77 | 45 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
46 | afu->enabled = enabled; |
47 | rc = -EIO; | |
48 | goto out; | |
49 | } | |
50 | ||
de369538 | 51 | pr_devel_ratelimited("AFU control... (0x%016llx)\n", |
f204e0b8 IM |
52 | AFU_Cntl | command); |
53 | cpu_relax(); | |
54 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
55 | }; | |
56 | pr_devel("AFU command complete: %llx\n", command); | |
57 | afu->enabled = enabled; | |
9bcf28cd IM |
58 | out: |
59 | trace_cxl_afu_ctrl_done(afu, command, rc); | |
f204e0b8 IM |
60 | spin_unlock(&afu->afu_cntl_lock); |
61 | ||
9bcf28cd | 62 | return rc; |
f204e0b8 IM |
63 | } |
64 | ||
65 | static int afu_enable(struct cxl_afu *afu) | |
66 | { | |
67 | pr_devel("AFU enable request\n"); | |
68 | ||
69 | return afu_control(afu, CXL_AFU_Cntl_An_E, | |
70 | CXL_AFU_Cntl_An_ES_Enabled, | |
71 | CXL_AFU_Cntl_An_ES_MASK, true); | |
72 | } | |
73 | ||
74 | int cxl_afu_disable(struct cxl_afu *afu) | |
75 | { | |
76 | pr_devel("AFU disable request\n"); | |
77 | ||
78 | return afu_control(afu, 0, CXL_AFU_Cntl_An_ES_Disabled, | |
79 | CXL_AFU_Cntl_An_ES_MASK, false); | |
80 | } | |
81 | ||
82 | /* This will disable as well as reset */ | |
2b04cf31 | 83 | static int native_afu_reset(struct cxl_afu *afu) |
f204e0b8 IM |
84 | { |
85 | pr_devel("AFU reset request\n"); | |
86 | ||
87 | return afu_control(afu, CXL_AFU_Cntl_An_RA, | |
88 | CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled, | |
89 | CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK, | |
90 | false); | |
91 | } | |
92 | ||
2b04cf31 | 93 | static int native_afu_check_and_enable(struct cxl_afu *afu) |
f204e0b8 | 94 | { |
0d400f77 | 95 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
96 | WARN(1, "Refusing to enable afu while link down!\n"); |
97 | return -EIO; | |
98 | } | |
f204e0b8 IM |
99 | if (afu->enabled) |
100 | return 0; | |
101 | return afu_enable(afu); | |
102 | } | |
103 | ||
104 | int cxl_psl_purge(struct cxl_afu *afu) | |
105 | { | |
106 | u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
107 | u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
108 | u64 dsisr, dar; | |
109 | u64 start, end; | |
110 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
9bcf28cd IM |
111 | int rc = 0; |
112 | ||
113 | trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc); | |
f204e0b8 IM |
114 | |
115 | pr_devel("PSL purge request\n"); | |
116 | ||
0d400f77 | 117 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
118 | dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n"); |
119 | rc = -EIO; | |
120 | goto out; | |
121 | } | |
122 | ||
f204e0b8 IM |
123 | if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { |
124 | WARN(1, "psl_purge request while AFU not disabled!\n"); | |
125 | cxl_afu_disable(afu); | |
126 | } | |
127 | ||
128 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, | |
129 | PSL_CNTL | CXL_PSL_SCNTL_An_Pc); | |
130 | start = local_clock(); | |
131 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
132 | while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK) | |
133 | == CXL_PSL_SCNTL_An_Ps_Pending) { | |
134 | if (time_after_eq(jiffies, timeout)) { | |
135 | dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n"); | |
9bcf28cd IM |
136 | rc = -EBUSY; |
137 | goto out; | |
f204e0b8 | 138 | } |
0d400f77 | 139 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
140 | rc = -EIO; |
141 | goto out; | |
142 | } | |
143 | ||
f204e0b8 | 144 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
de369538 | 145 | pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr); |
f204e0b8 IM |
146 | if (dsisr & CXL_PSL_DSISR_TRANS) { |
147 | dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); | |
de369538 | 148 | dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar); |
f204e0b8 IM |
149 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); |
150 | } else if (dsisr) { | |
de369538 | 151 | dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr); |
f204e0b8 IM |
152 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); |
153 | } else { | |
154 | cpu_relax(); | |
155 | } | |
156 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
157 | }; | |
158 | end = local_clock(); | |
159 | pr_devel("PSL purged in %lld ns\n", end - start); | |
160 | ||
161 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, | |
162 | PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc); | |
9bcf28cd IM |
163 | out: |
164 | trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc); | |
165 | return rc; | |
f204e0b8 IM |
166 | } |
167 | ||
168 | static int spa_max_procs(int spa_size) | |
169 | { | |
170 | /* | |
171 | * From the CAIA: | |
172 | * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255 | |
173 | * Most of that junk is really just an overly-complicated way of saying | |
174 | * the last 256 bytes are __aligned(128), so it's really: | |
175 | * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255 | |
176 | * and | |
177 | * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1 | |
178 | * so | |
179 | * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256 | |
180 | * Ignore the alignment (which is safe in this case as long as we are | |
181 | * careful with our rounding) and solve for n: | |
182 | */ | |
183 | return ((spa_size / 8) - 96) / 17; | |
184 | } | |
185 | ||
05155772 | 186 | int cxl_alloc_spa(struct cxl_afu *afu) |
f204e0b8 | 187 | { |
895a7980 IM |
188 | unsigned spa_size; |
189 | ||
f204e0b8 | 190 | /* Work out how many pages to allocate */ |
cbffa3a5 | 191 | afu->native->spa_order = 0; |
f204e0b8 | 192 | do { |
cbffa3a5 | 193 | afu->native->spa_order++; |
895a7980 IM |
194 | spa_size = (1 << afu->native->spa_order) * PAGE_SIZE; |
195 | ||
196 | if (spa_size > 0x100000) { | |
197 | dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n", | |
198 | afu->native->spa_max_procs, afu->native->spa_size); | |
199 | afu->num_procs = afu->native->spa_max_procs; | |
200 | break; | |
201 | } | |
202 | ||
203 | afu->native->spa_size = spa_size; | |
cbffa3a5 CL |
204 | afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size); |
205 | } while (afu->native->spa_max_procs < afu->num_procs); | |
f204e0b8 | 206 | |
cbffa3a5 CL |
207 | if (!(afu->native->spa = (struct cxl_process_element *) |
208 | __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) { | |
f204e0b8 IM |
209 | pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n"); |
210 | return -ENOMEM; | |
211 | } | |
212 | pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n", | |
cbffa3a5 | 213 | 1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs); |
f204e0b8 | 214 | |
05155772 DA |
215 | return 0; |
216 | } | |
217 | ||
218 | static void attach_spa(struct cxl_afu *afu) | |
219 | { | |
220 | u64 spap; | |
221 | ||
cbffa3a5 CL |
222 | afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa + |
223 | ((afu->native->spa_max_procs + 3) * 128)); | |
f204e0b8 | 224 | |
cbffa3a5 CL |
225 | spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr; |
226 | spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size; | |
f204e0b8 | 227 | spap |= CXL_PSL_SPAP_V; |
cbffa3a5 CL |
228 | pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", |
229 | afu->native->spa, afu->native->spa_max_procs, | |
230 | afu->native->sw_command_status, spap); | |
f204e0b8 | 231 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap); |
f204e0b8 IM |
232 | } |
233 | ||
05155772 | 234 | static inline void detach_spa(struct cxl_afu *afu) |
f204e0b8 | 235 | { |
db7933f3 | 236 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); |
05155772 DA |
237 | } |
238 | ||
239 | void cxl_release_spa(struct cxl_afu *afu) | |
240 | { | |
cbffa3a5 CL |
241 | if (afu->native->spa) { |
242 | free_pages((unsigned long) afu->native->spa, | |
243 | afu->native->spa_order); | |
244 | afu->native->spa = NULL; | |
05155772 | 245 | } |
f204e0b8 IM |
246 | } |
247 | ||
248 | int cxl_tlb_slb_invalidate(struct cxl *adapter) | |
249 | { | |
250 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
251 | ||
252 | pr_devel("CXL adapter wide TLBIA & SLBIA\n"); | |
253 | ||
254 | cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A); | |
255 | ||
256 | cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL); | |
257 | while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) { | |
258 | if (time_after_eq(jiffies, timeout)) { | |
259 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n"); | |
260 | return -EBUSY; | |
261 | } | |
0d400f77 | 262 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 263 | return -EIO; |
f204e0b8 IM |
264 | cpu_relax(); |
265 | } | |
266 | ||
267 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL); | |
268 | while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) { | |
269 | if (time_after_eq(jiffies, timeout)) { | |
270 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n"); | |
271 | return -EBUSY; | |
272 | } | |
0d400f77 | 273 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 274 | return -EIO; |
f204e0b8 IM |
275 | cpu_relax(); |
276 | } | |
277 | return 0; | |
278 | } | |
279 | ||
f204e0b8 IM |
280 | static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1) |
281 | { | |
282 | int rc; | |
283 | ||
284 | /* 1. Disable SSTP by writing 0 to SSTP1[V] */ | |
285 | cxl_p2n_write(afu, CXL_SSTP1_An, 0); | |
286 | ||
287 | /* 2. Invalidate all SLB entries */ | |
288 | if ((rc = cxl_afu_slbia(afu))) | |
289 | return rc; | |
290 | ||
291 | /* 3. Set SSTP0_An */ | |
292 | cxl_p2n_write(afu, CXL_SSTP0_An, sstp0); | |
293 | ||
294 | /* 4. Set SSTP1_An */ | |
295 | cxl_p2n_write(afu, CXL_SSTP1_An, sstp1); | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | /* Using per slice version may improve performance here. (ie. SLBIA_An) */ | |
301 | static void slb_invalid(struct cxl_context *ctx) | |
302 | { | |
303 | struct cxl *adapter = ctx->afu->adapter; | |
304 | u64 slbia; | |
305 | ||
cbffa3a5 | 306 | WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex)); |
f204e0b8 IM |
307 | |
308 | cxl_p1_write(adapter, CXL_PSL_LBISEL, | |
309 | ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) | | |
310 | be32_to_cpu(ctx->elem->lpid)); | |
311 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID); | |
312 | ||
313 | while (1) { | |
0d400f77 | 314 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 315 | break; |
f204e0b8 IM |
316 | slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA); |
317 | if (!(slbia & CXL_TLB_SLB_P)) | |
318 | break; | |
319 | cpu_relax(); | |
320 | } | |
321 | } | |
322 | ||
323 | static int do_process_element_cmd(struct cxl_context *ctx, | |
324 | u64 cmd, u64 pe_state) | |
325 | { | |
326 | u64 state; | |
a98e6e9f | 327 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
9bcf28cd IM |
328 | int rc = 0; |
329 | ||
330 | trace_cxl_llcmd(ctx, cmd); | |
f204e0b8 IM |
331 | |
332 | WARN_ON(!ctx->afu->enabled); | |
333 | ||
334 | ctx->elem->software_state = cpu_to_be32(pe_state); | |
335 | smp_wmb(); | |
cbffa3a5 | 336 | *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe); |
f204e0b8 IM |
337 | smp_mb(); |
338 | cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe); | |
339 | while (1) { | |
a98e6e9f IM |
340 | if (time_after_eq(jiffies, timeout)) { |
341 | dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n"); | |
9bcf28cd IM |
342 | rc = -EBUSY; |
343 | goto out; | |
a98e6e9f | 344 | } |
0d400f77 | 345 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
0b3f9c75 DA |
346 | dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n"); |
347 | rc = -EIO; | |
348 | goto out; | |
349 | } | |
cbffa3a5 | 350 | state = be64_to_cpup(ctx->afu->native->sw_command_status); |
f204e0b8 IM |
351 | if (state == ~0ULL) { |
352 | pr_err("cxl: Error adding process element to AFU\n"); | |
9bcf28cd IM |
353 | rc = -1; |
354 | goto out; | |
f204e0b8 IM |
355 | } |
356 | if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) == | |
357 | (cmd | (cmd >> 16) | ctx->pe)) | |
358 | break; | |
359 | /* | |
360 | * The command won't finish in the PSL if there are | |
361 | * outstanding DSIs. Hence we need to yield here in | |
362 | * case there are outstanding DSIs that we need to | |
363 | * service. Tuning possiblity: we could wait for a | |
364 | * while before sched | |
365 | */ | |
366 | schedule(); | |
367 | ||
368 | } | |
9bcf28cd IM |
369 | out: |
370 | trace_cxl_llcmd_done(ctx, cmd, rc); | |
371 | return rc; | |
f204e0b8 IM |
372 | } |
373 | ||
374 | static int add_process_element(struct cxl_context *ctx) | |
375 | { | |
376 | int rc = 0; | |
377 | ||
cbffa3a5 | 378 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
379 | pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe); |
380 | if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V))) | |
381 | ctx->pe_inserted = true; | |
382 | pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 383 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
384 | return rc; |
385 | } | |
386 | ||
387 | static int terminate_process_element(struct cxl_context *ctx) | |
388 | { | |
389 | int rc = 0; | |
390 | ||
391 | /* fast path terminate if it's already invalid */ | |
392 | if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V))) | |
393 | return rc; | |
394 | ||
cbffa3a5 | 395 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 | 396 | pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe); |
0b3f9c75 DA |
397 | /* We could be asked to terminate when the hw is down. That |
398 | * should always succeed: it's not running if the hw has gone | |
399 | * away and is being reset. | |
400 | */ | |
0d400f77 | 401 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
0b3f9c75 DA |
402 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE, |
403 | CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T); | |
f204e0b8 IM |
404 | ctx->elem->software_state = 0; /* Remove Valid bit */ |
405 | pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 406 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
407 | return rc; |
408 | } | |
409 | ||
410 | static int remove_process_element(struct cxl_context *ctx) | |
411 | { | |
412 | int rc = 0; | |
413 | ||
cbffa3a5 | 414 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 | 415 | pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe); |
0b3f9c75 DA |
416 | |
417 | /* We could be asked to remove when the hw is down. Again, if | |
418 | * the hw is down, the PE is gone, so we succeed. | |
419 | */ | |
0d400f77 | 420 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
0b3f9c75 DA |
421 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0); |
422 | ||
423 | if (!rc) | |
f204e0b8 IM |
424 | ctx->pe_inserted = false; |
425 | slb_invalid(ctx); | |
426 | pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 427 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
428 | |
429 | return rc; | |
430 | } | |
431 | ||
432 | ||
1a1a94b8 | 433 | void cxl_assign_psn_space(struct cxl_context *ctx) |
f204e0b8 IM |
434 | { |
435 | if (!ctx->afu->pp_size || ctx->master) { | |
436 | ctx->psn_phys = ctx->afu->psn_phys; | |
437 | ctx->psn_size = ctx->afu->adapter->ps_size; | |
438 | } else { | |
439 | ctx->psn_phys = ctx->afu->psn_phys + | |
cbffa3a5 | 440 | (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe); |
f204e0b8 IM |
441 | ctx->psn_size = ctx->afu->pp_size; |
442 | } | |
443 | } | |
444 | ||
445 | static int activate_afu_directed(struct cxl_afu *afu) | |
446 | { | |
447 | int rc; | |
448 | ||
449 | dev_info(&afu->dev, "Activating AFU directed mode\n"); | |
450 | ||
4108efb0 | 451 | afu->num_procs = afu->max_procs_virtualised; |
cbffa3a5 | 452 | if (afu->native->spa == NULL) { |
05155772 DA |
453 | if (cxl_alloc_spa(afu)) |
454 | return -ENOMEM; | |
455 | } | |
456 | attach_spa(afu); | |
f204e0b8 IM |
457 | |
458 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU); | |
459 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); | |
460 | cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L); | |
461 | ||
462 | afu->current_mode = CXL_MODE_DIRECTED; | |
f204e0b8 IM |
463 | |
464 | if ((rc = cxl_chardev_m_afu_add(afu))) | |
465 | return rc; | |
466 | ||
467 | if ((rc = cxl_sysfs_afu_m_add(afu))) | |
468 | goto err; | |
469 | ||
470 | if ((rc = cxl_chardev_s_afu_add(afu))) | |
471 | goto err1; | |
472 | ||
473 | return 0; | |
474 | err1: | |
475 | cxl_sysfs_afu_m_remove(afu); | |
476 | err: | |
477 | cxl_chardev_afu_remove(afu); | |
478 | return rc; | |
479 | } | |
480 | ||
481 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
482 | #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE) | |
483 | #else | |
484 | #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE)) | |
485 | #endif | |
486 | ||
2f663527 MN |
487 | static u64 calculate_sr(struct cxl_context *ctx) |
488 | { | |
489 | u64 sr = 0; | |
490 | ||
e606e035 | 491 | set_endian(sr); |
2f663527 MN |
492 | if (ctx->master) |
493 | sr |= CXL_PSL_SR_An_MP; | |
494 | if (mfspr(SPRN_LPCR) & LPCR_TC) | |
495 | sr |= CXL_PSL_SR_An_TC; | |
496 | if (ctx->kernel) { | |
497 | sr |= CXL_PSL_SR_An_R | (mfmsr() & MSR_SF); | |
498 | sr |= CXL_PSL_SR_An_HV; | |
499 | } else { | |
500 | sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; | |
2f663527 MN |
501 | sr &= ~(CXL_PSL_SR_An_HV); |
502 | if (!test_tsk_thread_flag(current, TIF_32BIT)) | |
503 | sr |= CXL_PSL_SR_An_SF; | |
504 | } | |
505 | return sr; | |
506 | } | |
507 | ||
f204e0b8 IM |
508 | static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr) |
509 | { | |
2f663527 | 510 | u32 pid; |
f204e0b8 IM |
511 | int r, result; |
512 | ||
1a1a94b8 | 513 | cxl_assign_psn_space(ctx); |
f204e0b8 IM |
514 | |
515 | ctx->elem->ctxtime = 0; /* disable */ | |
516 | ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID)); | |
517 | ctx->elem->haurp = 0; /* disable */ | |
518 | ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1)); | |
519 | ||
2f663527 MN |
520 | pid = current->pid; |
521 | if (ctx->kernel) | |
522 | pid = 0; | |
f204e0b8 | 523 | ctx->elem->common.tid = 0; |
2f663527 MN |
524 | ctx->elem->common.pid = cpu_to_be32(pid); |
525 | ||
526 | ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); | |
f204e0b8 IM |
527 | |
528 | ctx->elem->common.csrp = 0; /* disable */ | |
529 | ctx->elem->common.aurp0 = 0; /* disable */ | |
530 | ctx->elem->common.aurp1 = 0; /* disable */ | |
531 | ||
532 | cxl_prefault(ctx, wed); | |
533 | ||
534 | ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0); | |
535 | ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1); | |
536 | ||
537 | for (r = 0; r < CXL_IRQ_RANGES; r++) { | |
538 | ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]); | |
539 | ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]); | |
540 | } | |
541 | ||
542 | ctx->elem->common.amr = cpu_to_be64(amr); | |
543 | ctx->elem->common.wed = cpu_to_be64(wed); | |
544 | ||
545 | /* first guy needs to enable */ | |
5be587b1 | 546 | if ((result = cxl_ops->afu_check_and_enable(ctx->afu))) |
f204e0b8 IM |
547 | return result; |
548 | ||
368857c1 | 549 | return add_process_element(ctx); |
f204e0b8 IM |
550 | } |
551 | ||
552 | static int deactivate_afu_directed(struct cxl_afu *afu) | |
553 | { | |
554 | dev_info(&afu->dev, "Deactivating AFU directed mode\n"); | |
555 | ||
556 | afu->current_mode = 0; | |
557 | afu->num_procs = 0; | |
558 | ||
559 | cxl_sysfs_afu_m_remove(afu); | |
560 | cxl_chardev_afu_remove(afu); | |
561 | ||
5be587b1 | 562 | cxl_ops->afu_reset(afu); |
f204e0b8 IM |
563 | cxl_afu_disable(afu); |
564 | cxl_psl_purge(afu); | |
565 | ||
f204e0b8 IM |
566 | return 0; |
567 | } | |
568 | ||
569 | static int activate_dedicated_process(struct cxl_afu *afu) | |
570 | { | |
571 | dev_info(&afu->dev, "Activating dedicated process mode\n"); | |
572 | ||
573 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process); | |
574 | ||
575 | cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */ | |
576 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */ | |
577 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); | |
578 | cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID)); | |
579 | cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */ | |
580 | cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1)); | |
581 | ||
582 | cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */ | |
583 | cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */ | |
584 | cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */ | |
585 | ||
586 | afu->current_mode = CXL_MODE_DEDICATED; | |
587 | afu->num_procs = 1; | |
588 | ||
589 | return cxl_chardev_d_afu_add(afu); | |
590 | } | |
591 | ||
592 | static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr) | |
593 | { | |
594 | struct cxl_afu *afu = ctx->afu; | |
2f663527 | 595 | u64 pid; |
f204e0b8 IM |
596 | int rc; |
597 | ||
2f663527 MN |
598 | pid = (u64)current->pid << 32; |
599 | if (ctx->kernel) | |
600 | pid = 0; | |
601 | cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid); | |
602 | ||
603 | cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx)); | |
f204e0b8 IM |
604 | |
605 | if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1))) | |
606 | return rc; | |
607 | ||
608 | cxl_prefault(ctx, wed); | |
609 | ||
610 | cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, | |
611 | (((u64)ctx->irqs.offset[0] & 0xffff) << 48) | | |
612 | (((u64)ctx->irqs.offset[1] & 0xffff) << 32) | | |
613 | (((u64)ctx->irqs.offset[2] & 0xffff) << 16) | | |
614 | ((u64)ctx->irqs.offset[3] & 0xffff)); | |
615 | cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64) | |
616 | (((u64)ctx->irqs.range[0] & 0xffff) << 48) | | |
617 | (((u64)ctx->irqs.range[1] & 0xffff) << 32) | | |
618 | (((u64)ctx->irqs.range[2] & 0xffff) << 16) | | |
619 | ((u64)ctx->irqs.range[3] & 0xffff)); | |
620 | ||
621 | cxl_p2n_write(afu, CXL_PSL_AMR_An, amr); | |
622 | ||
623 | /* master only context for dedicated */ | |
1a1a94b8 | 624 | cxl_assign_psn_space(ctx); |
f204e0b8 | 625 | |
5be587b1 | 626 | if ((rc = cxl_ops->afu_reset(afu))) |
f204e0b8 IM |
627 | return rc; |
628 | ||
629 | cxl_p2n_write(afu, CXL_PSL_WED_An, wed); | |
630 | ||
631 | return afu_enable(afu); | |
632 | } | |
633 | ||
634 | static int deactivate_dedicated_process(struct cxl_afu *afu) | |
635 | { | |
636 | dev_info(&afu->dev, "Deactivating dedicated process mode\n"); | |
637 | ||
638 | afu->current_mode = 0; | |
639 | afu->num_procs = 0; | |
640 | ||
641 | cxl_chardev_afu_remove(afu); | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
2b04cf31 | 646 | static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode) |
f204e0b8 IM |
647 | { |
648 | if (mode == CXL_MODE_DIRECTED) | |
649 | return deactivate_afu_directed(afu); | |
650 | if (mode == CXL_MODE_DEDICATED) | |
651 | return deactivate_dedicated_process(afu); | |
652 | return 0; | |
653 | } | |
654 | ||
2b04cf31 | 655 | static int native_afu_activate_mode(struct cxl_afu *afu, int mode) |
f204e0b8 IM |
656 | { |
657 | if (!mode) | |
658 | return 0; | |
659 | if (!(mode & afu->modes_supported)) | |
660 | return -EINVAL; | |
661 | ||
0d400f77 | 662 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
663 | WARN(1, "Device link is down, refusing to activate!\n"); |
664 | return -EIO; | |
665 | } | |
666 | ||
f204e0b8 IM |
667 | if (mode == CXL_MODE_DIRECTED) |
668 | return activate_afu_directed(afu); | |
669 | if (mode == CXL_MODE_DEDICATED) | |
670 | return activate_dedicated_process(afu); | |
671 | ||
672 | return -EINVAL; | |
673 | } | |
674 | ||
2b04cf31 FB |
675 | static int native_attach_process(struct cxl_context *ctx, bool kernel, |
676 | u64 wed, u64 amr) | |
f204e0b8 | 677 | { |
0d400f77 | 678 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
0b3f9c75 DA |
679 | WARN(1, "Device link is down, refusing to attach process!\n"); |
680 | return -EIO; | |
681 | } | |
682 | ||
f204e0b8 IM |
683 | ctx->kernel = kernel; |
684 | if (ctx->afu->current_mode == CXL_MODE_DIRECTED) | |
685 | return attach_afu_directed(ctx, wed, amr); | |
686 | ||
687 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) | |
688 | return attach_dedicated(ctx, wed, amr); | |
689 | ||
690 | return -EINVAL; | |
691 | } | |
692 | ||
693 | static inline int detach_process_native_dedicated(struct cxl_context *ctx) | |
694 | { | |
5be587b1 | 695 | cxl_ops->afu_reset(ctx->afu); |
f204e0b8 IM |
696 | cxl_afu_disable(ctx->afu); |
697 | cxl_psl_purge(ctx->afu); | |
698 | return 0; | |
699 | } | |
700 | ||
f204e0b8 IM |
701 | static inline int detach_process_native_afu_directed(struct cxl_context *ctx) |
702 | { | |
703 | if (!ctx->pe_inserted) | |
704 | return 0; | |
705 | if (terminate_process_element(ctx)) | |
706 | return -1; | |
707 | if (remove_process_element(ctx)) | |
708 | return -1; | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
2b04cf31 | 713 | static int native_detach_process(struct cxl_context *ctx) |
f204e0b8 | 714 | { |
9bcf28cd IM |
715 | trace_cxl_detach(ctx); |
716 | ||
f204e0b8 IM |
717 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) |
718 | return detach_process_native_dedicated(ctx); | |
719 | ||
720 | return detach_process_native_afu_directed(ctx); | |
721 | } | |
722 | ||
2b04cf31 | 723 | static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info) |
f204e0b8 IM |
724 | { |
725 | u64 pidtid; | |
726 | ||
0b3f9c75 DA |
727 | /* If the adapter has gone away, we can't get any meaningful |
728 | * information. | |
729 | */ | |
0d400f77 | 730 | if (!cxl_ops->link_ok(afu->adapter, afu)) |
0b3f9c75 DA |
731 | return -EIO; |
732 | ||
bc78b05b IM |
733 | info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
734 | info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); | |
735 | info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An); | |
736 | pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An); | |
f204e0b8 IM |
737 | info->pid = pidtid >> 32; |
738 | info->tid = pidtid & 0xffffffff; | |
bc78b05b IM |
739 | info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An); |
740 | info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
444c4ba4 | 741 | info->proc_handle = 0; |
f204e0b8 IM |
742 | |
743 | return 0; | |
744 | } | |
745 | ||
2b04cf31 FB |
746 | static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx, |
747 | u64 dsisr, u64 errstat) | |
d56d301b FB |
748 | { |
749 | u64 fir1, fir2, fir_slice, serr, afu_debug; | |
750 | ||
751 | fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1); | |
752 | fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2); | |
753 | fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An); | |
754 | serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An); | |
755 | afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An); | |
756 | ||
757 | dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat); | |
758 | dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1); | |
759 | dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2); | |
760 | dev_crit(&ctx->afu->dev, "PSL_SERR_An: 0x%016llx\n", serr); | |
761 | dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); | |
762 | dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); | |
763 | ||
764 | dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n"); | |
765 | cxl_stop_trace(ctx->afu->adapter); | |
766 | ||
5be587b1 | 767 | return cxl_ops->ack_irq(ctx, 0, errstat); |
d56d301b FB |
768 | } |
769 | ||
770 | static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info) | |
771 | { | |
772 | if (irq_info->dsisr & CXL_PSL_DSISR_TRANS) | |
773 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); | |
774 | else | |
775 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); | |
776 | ||
777 | return IRQ_HANDLED; | |
778 | } | |
779 | ||
2b04cf31 | 780 | static irqreturn_t native_irq_multiplexed(int irq, void *data) |
d56d301b FB |
781 | { |
782 | struct cxl_afu *afu = data; | |
783 | struct cxl_context *ctx; | |
784 | struct cxl_irq_info irq_info; | |
785 | int ph = cxl_p2n_read(afu, CXL_PSL_PEHandle_An) & 0xffff; | |
786 | int ret; | |
787 | ||
2b04cf31 | 788 | if ((ret = native_get_irq_info(afu, &irq_info))) { |
d56d301b FB |
789 | WARN(1, "Unable to get CXL IRQ Info: %i\n", ret); |
790 | return fail_psl_irq(afu, &irq_info); | |
791 | } | |
792 | ||
793 | rcu_read_lock(); | |
794 | ctx = idr_find(&afu->contexts_idr, ph); | |
795 | if (ctx) { | |
796 | ret = cxl_irq(irq, ctx, &irq_info); | |
797 | rcu_read_unlock(); | |
798 | return ret; | |
799 | } | |
800 | rcu_read_unlock(); | |
801 | ||
802 | WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR" | |
803 | " %016llx\n(Possible AFU HW issue - was a term/remove acked" | |
804 | " with outstanding transactions?)\n", ph, irq_info.dsisr, | |
805 | irq_info.dar); | |
806 | return fail_psl_irq(afu, &irq_info); | |
807 | } | |
808 | ||
2b04cf31 | 809 | static irqreturn_t native_slice_irq_err(int irq, void *data) |
d56d301b FB |
810 | { |
811 | struct cxl_afu *afu = data; | |
812 | u64 fir_slice, errstat, serr, afu_debug; | |
813 | ||
814 | WARN(irq, "CXL SLICE ERROR interrupt %i\n", irq); | |
815 | ||
816 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
817 | fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An); | |
818 | errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
819 | afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An); | |
820 | dev_crit(&afu->dev, "PSL_SERR_An: 0x%016llx\n", serr); | |
821 | dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); | |
822 | dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat); | |
823 | dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); | |
824 | ||
825 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); | |
826 | ||
827 | return IRQ_HANDLED; | |
828 | } | |
829 | ||
2b04cf31 | 830 | static irqreturn_t native_irq_err(int irq, void *data) |
d56d301b FB |
831 | { |
832 | struct cxl *adapter = data; | |
833 | u64 fir1, fir2, err_ivte; | |
834 | ||
835 | WARN(1, "CXL ERROR interrupt %i\n", irq); | |
836 | ||
837 | err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE); | |
838 | dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte); | |
839 | ||
840 | dev_crit(&adapter->dev, "STOPPING CXL TRACE\n"); | |
841 | cxl_stop_trace(adapter); | |
842 | ||
843 | fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1); | |
844 | fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2); | |
845 | ||
846 | dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2); | |
847 | ||
848 | return IRQ_HANDLED; | |
849 | } | |
850 | ||
2b04cf31 | 851 | int cxl_native_register_psl_err_irq(struct cxl *adapter) |
d56d301b FB |
852 | { |
853 | int rc; | |
854 | ||
855 | adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", | |
856 | dev_name(&adapter->dev)); | |
857 | if (!adapter->irq_name) | |
858 | return -ENOMEM; | |
859 | ||
2b04cf31 | 860 | if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter, |
cbffa3a5 CL |
861 | &adapter->native->err_hwirq, |
862 | &adapter->native->err_virq, | |
d56d301b FB |
863 | adapter->irq_name))) { |
864 | kfree(adapter->irq_name); | |
865 | adapter->irq_name = NULL; | |
866 | return rc; | |
867 | } | |
868 | ||
cbffa3a5 | 869 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff); |
d56d301b FB |
870 | |
871 | return 0; | |
872 | } | |
873 | ||
2b04cf31 | 874 | void cxl_native_release_psl_err_irq(struct cxl *adapter) |
d56d301b | 875 | { |
cbffa3a5 | 876 | if (adapter->native->err_virq != irq_find_mapping(NULL, adapter->native->err_hwirq)) |
d56d301b FB |
877 | return; |
878 | ||
879 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000); | |
cbffa3a5 CL |
880 | cxl_unmap_irq(adapter->native->err_virq, adapter); |
881 | cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq); | |
d56d301b FB |
882 | kfree(adapter->irq_name); |
883 | } | |
884 | ||
2b04cf31 | 885 | int cxl_native_register_serr_irq(struct cxl_afu *afu) |
d56d301b FB |
886 | { |
887 | u64 serr; | |
888 | int rc; | |
889 | ||
890 | afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", | |
891 | dev_name(&afu->dev)); | |
892 | if (!afu->err_irq_name) | |
893 | return -ENOMEM; | |
894 | ||
2b04cf31 | 895 | if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu, |
d56d301b FB |
896 | &afu->serr_hwirq, |
897 | &afu->serr_virq, afu->err_irq_name))) { | |
898 | kfree(afu->err_irq_name); | |
899 | afu->err_irq_name = NULL; | |
900 | return rc; | |
901 | } | |
902 | ||
903 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
904 | serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff); | |
905 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); | |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
2b04cf31 | 910 | void cxl_native_release_serr_irq(struct cxl_afu *afu) |
d56d301b FB |
911 | { |
912 | if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq)) | |
913 | return; | |
914 | ||
915 | cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000); | |
916 | cxl_unmap_irq(afu->serr_virq, afu); | |
5be587b1 | 917 | cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq); |
d56d301b FB |
918 | kfree(afu->err_irq_name); |
919 | } | |
920 | ||
2b04cf31 | 921 | int cxl_native_register_psl_irq(struct cxl_afu *afu) |
d56d301b FB |
922 | { |
923 | int rc; | |
924 | ||
925 | afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s", | |
926 | dev_name(&afu->dev)); | |
927 | if (!afu->psl_irq_name) | |
928 | return -ENOMEM; | |
929 | ||
cbffa3a5 CL |
930 | if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed, |
931 | afu, &afu->native->psl_hwirq, &afu->native->psl_virq, | |
d56d301b FB |
932 | afu->psl_irq_name))) { |
933 | kfree(afu->psl_irq_name); | |
934 | afu->psl_irq_name = NULL; | |
935 | } | |
936 | return rc; | |
937 | } | |
938 | ||
2b04cf31 | 939 | void cxl_native_release_psl_irq(struct cxl_afu *afu) |
d56d301b | 940 | { |
cbffa3a5 | 941 | if (afu->native->psl_virq != irq_find_mapping(NULL, afu->native->psl_hwirq)) |
d56d301b FB |
942 | return; |
943 | ||
cbffa3a5 CL |
944 | cxl_unmap_irq(afu->native->psl_virq, afu); |
945 | cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq); | |
d56d301b FB |
946 | kfree(afu->psl_irq_name); |
947 | } | |
948 | ||
f204e0b8 IM |
949 | static void recover_psl_err(struct cxl_afu *afu, u64 errstat) |
950 | { | |
951 | u64 dsisr; | |
952 | ||
de369538 | 953 | pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat); |
f204e0b8 IM |
954 | |
955 | /* Clear PSL_DSISR[PE] */ | |
956 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
957 | cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE); | |
958 | ||
959 | /* Write 1s to clear error status bits */ | |
960 | cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat); | |
961 | } | |
962 | ||
2b04cf31 | 963 | static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask) |
f204e0b8 | 964 | { |
9bcf28cd | 965 | trace_cxl_psl_irq_ack(ctx, tfc); |
f204e0b8 IM |
966 | if (tfc) |
967 | cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc); | |
968 | if (psl_reset_mask) | |
969 | recover_psl_err(ctx->afu, psl_reset_mask); | |
970 | ||
971 | return 0; | |
972 | } | |
973 | ||
974 | int cxl_check_error(struct cxl_afu *afu) | |
975 | { | |
976 | return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL); | |
977 | } | |
d56d301b | 978 | |
4752876c CL |
979 | static bool native_support_attributes(const char *attr_name, |
980 | enum cxl_attrs type) | |
981 | { | |
982 | return true; | |
983 | } | |
984 | ||
2b04cf31 | 985 | static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out) |
d56d301b | 986 | { |
0d400f77 | 987 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
5be587b1 FB |
988 | return -EIO; |
989 | if (unlikely(off >= afu->crs_len)) | |
990 | return -ERANGE; | |
cbffa3a5 | 991 | *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset + |
5be587b1 FB |
992 | (cr * afu->crs_len) + off); |
993 | return 0; | |
d56d301b FB |
994 | } |
995 | ||
2b04cf31 | 996 | static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out) |
d56d301b | 997 | { |
0d400f77 | 998 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
5be587b1 FB |
999 | return -EIO; |
1000 | if (unlikely(off >= afu->crs_len)) | |
1001 | return -ERANGE; | |
cbffa3a5 | 1002 | *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset + |
5be587b1 FB |
1003 | (cr * afu->crs_len) + off); |
1004 | return 0; | |
d56d301b FB |
1005 | } |
1006 | ||
2b04cf31 | 1007 | static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out) |
d56d301b FB |
1008 | { |
1009 | u64 aligned_off = off & ~0x3L; | |
1010 | u32 val; | |
5be587b1 | 1011 | int rc; |
d56d301b | 1012 | |
2b04cf31 | 1013 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
5be587b1 FB |
1014 | if (!rc) |
1015 | *out = (val >> ((off & 0x3) * 8)) & 0xffff; | |
1016 | return rc; | |
d56d301b FB |
1017 | } |
1018 | ||
2b04cf31 | 1019 | static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out) |
d56d301b FB |
1020 | { |
1021 | u64 aligned_off = off & ~0x3L; | |
1022 | u32 val; | |
5be587b1 | 1023 | int rc; |
d56d301b | 1024 | |
2b04cf31 | 1025 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
5be587b1 FB |
1026 | if (!rc) |
1027 | *out = (val >> ((off & 0x3) * 8)) & 0xff; | |
1028 | return rc; | |
d56d301b | 1029 | } |
5be587b1 | 1030 | |
d601ea91 FB |
1031 | static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in) |
1032 | { | |
0d400f77 | 1033 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
d601ea91 FB |
1034 | return -EIO; |
1035 | if (unlikely(off >= afu->crs_len)) | |
1036 | return -ERANGE; | |
1037 | out_le32(afu->native->afu_desc_mmio + afu->crs_offset + | |
1038 | (cr * afu->crs_len) + off, in); | |
1039 | return 0; | |
1040 | } | |
1041 | ||
1042 | static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in) | |
1043 | { | |
1044 | u64 aligned_off = off & ~0x3L; | |
1045 | u32 val32, mask, shift; | |
1046 | int rc; | |
1047 | ||
1048 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); | |
1049 | if (rc) | |
1050 | return rc; | |
1051 | shift = (off & 0x3) * 8; | |
1052 | WARN_ON(shift == 24); | |
1053 | mask = 0xffff << shift; | |
1054 | val32 = (val32 & ~mask) | (in << shift); | |
1055 | ||
1056 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); | |
1057 | return rc; | |
1058 | } | |
1059 | ||
1060 | static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in) | |
1061 | { | |
1062 | u64 aligned_off = off & ~0x3L; | |
1063 | u32 val32, mask, shift; | |
1064 | int rc; | |
1065 | ||
1066 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); | |
1067 | if (rc) | |
1068 | return rc; | |
1069 | shift = (off & 0x3) * 8; | |
1070 | mask = 0xff << shift; | |
1071 | val32 = (val32 & ~mask) | (in << shift); | |
1072 | ||
1073 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); | |
1074 | return rc; | |
1075 | } | |
1076 | ||
5be587b1 FB |
1077 | const struct cxl_backend_ops cxl_native_ops = { |
1078 | .module = THIS_MODULE, | |
2b04cf31 FB |
1079 | .adapter_reset = cxl_pci_reset, |
1080 | .alloc_one_irq = cxl_pci_alloc_one_irq, | |
1081 | .release_one_irq = cxl_pci_release_one_irq, | |
1082 | .alloc_irq_ranges = cxl_pci_alloc_irq_ranges, | |
1083 | .release_irq_ranges = cxl_pci_release_irq_ranges, | |
1084 | .setup_irq = cxl_pci_setup_irq, | |
1085 | .handle_psl_slice_error = native_handle_psl_slice_error, | |
5be587b1 | 1086 | .psl_interrupt = NULL, |
2b04cf31 FB |
1087 | .ack_irq = native_ack_irq, |
1088 | .attach_process = native_attach_process, | |
1089 | .detach_process = native_detach_process, | |
4752876c | 1090 | .support_attributes = native_support_attributes, |
5be587b1 | 1091 | .link_ok = cxl_adapter_link_ok, |
2b04cf31 FB |
1092 | .release_afu = cxl_pci_release_afu, |
1093 | .afu_read_err_buffer = cxl_pci_afu_read_err_buffer, | |
1094 | .afu_check_and_enable = native_afu_check_and_enable, | |
1095 | .afu_activate_mode = native_afu_activate_mode, | |
1096 | .afu_deactivate_mode = native_afu_deactivate_mode, | |
1097 | .afu_reset = native_afu_reset, | |
1098 | .afu_cr_read8 = native_afu_cr_read8, | |
1099 | .afu_cr_read16 = native_afu_cr_read16, | |
1100 | .afu_cr_read32 = native_afu_cr_read32, | |
1101 | .afu_cr_read64 = native_afu_cr_read64, | |
d601ea91 FB |
1102 | .afu_cr_write8 = native_afu_cr_write8, |
1103 | .afu_cr_write16 = native_afu_cr_write16, | |
1104 | .afu_cr_write32 = native_afu_cr_write32, | |
1105 | .read_adapter_vpd = cxl_pci_read_adapter_vpd, | |
5be587b1 | 1106 | }; |