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Commit | Line | Data |
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f204e0b8 IM |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/spinlock.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/sched.h> | |
14 | #include <linux/mutex.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/uaccess.h> | |
2bc79ffc | 17 | #include <linux/delay.h> |
f204e0b8 | 18 | #include <asm/synch.h> |
ec249dd8 | 19 | #include <misc/cxl-base.h> |
f204e0b8 IM |
20 | |
21 | #include "cxl.h" | |
9bcf28cd | 22 | #include "trace.h" |
f204e0b8 IM |
23 | |
24 | static int afu_control(struct cxl_afu *afu, u64 command, | |
25 | u64 result, u64 mask, bool enabled) | |
26 | { | |
27 | u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
28 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
9bcf28cd | 29 | int rc = 0; |
f204e0b8 IM |
30 | |
31 | spin_lock(&afu->afu_cntl_lock); | |
32 | pr_devel("AFU command starting: %llx\n", command); | |
33 | ||
9bcf28cd IM |
34 | trace_cxl_afu_ctrl(afu, command); |
35 | ||
f204e0b8 IM |
36 | cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl | command); |
37 | ||
38 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
39 | while ((AFU_Cntl & mask) != result) { | |
40 | if (time_after_eq(jiffies, timeout)) { | |
41 | dev_warn(&afu->dev, "WARNING: AFU control timed out!\n"); | |
9bcf28cd IM |
42 | rc = -EBUSY; |
43 | goto out; | |
f204e0b8 | 44 | } |
0b3f9c75 | 45 | |
0d400f77 | 46 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
47 | afu->enabled = enabled; |
48 | rc = -EIO; | |
49 | goto out; | |
50 | } | |
51 | ||
de369538 | 52 | pr_devel_ratelimited("AFU control... (0x%016llx)\n", |
f204e0b8 IM |
53 | AFU_Cntl | command); |
54 | cpu_relax(); | |
55 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
56 | }; | |
57 | pr_devel("AFU command complete: %llx\n", command); | |
58 | afu->enabled = enabled; | |
9bcf28cd IM |
59 | out: |
60 | trace_cxl_afu_ctrl_done(afu, command, rc); | |
f204e0b8 IM |
61 | spin_unlock(&afu->afu_cntl_lock); |
62 | ||
9bcf28cd | 63 | return rc; |
f204e0b8 IM |
64 | } |
65 | ||
66 | static int afu_enable(struct cxl_afu *afu) | |
67 | { | |
68 | pr_devel("AFU enable request\n"); | |
69 | ||
70 | return afu_control(afu, CXL_AFU_Cntl_An_E, | |
71 | CXL_AFU_Cntl_An_ES_Enabled, | |
72 | CXL_AFU_Cntl_An_ES_MASK, true); | |
73 | } | |
74 | ||
75 | int cxl_afu_disable(struct cxl_afu *afu) | |
76 | { | |
77 | pr_devel("AFU disable request\n"); | |
78 | ||
79 | return afu_control(afu, 0, CXL_AFU_Cntl_An_ES_Disabled, | |
80 | CXL_AFU_Cntl_An_ES_MASK, false); | |
81 | } | |
82 | ||
83 | /* This will disable as well as reset */ | |
2b04cf31 | 84 | static int native_afu_reset(struct cxl_afu *afu) |
f204e0b8 IM |
85 | { |
86 | pr_devel("AFU reset request\n"); | |
87 | ||
88 | return afu_control(afu, CXL_AFU_Cntl_An_RA, | |
89 | CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled, | |
90 | CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK, | |
91 | false); | |
92 | } | |
93 | ||
2b04cf31 | 94 | static int native_afu_check_and_enable(struct cxl_afu *afu) |
f204e0b8 | 95 | { |
0d400f77 | 96 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
97 | WARN(1, "Refusing to enable afu while link down!\n"); |
98 | return -EIO; | |
99 | } | |
f204e0b8 IM |
100 | if (afu->enabled) |
101 | return 0; | |
102 | return afu_enable(afu); | |
103 | } | |
104 | ||
105 | int cxl_psl_purge(struct cxl_afu *afu) | |
106 | { | |
107 | u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
108 | u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
109 | u64 dsisr, dar; | |
110 | u64 start, end; | |
111 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
9bcf28cd IM |
112 | int rc = 0; |
113 | ||
114 | trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc); | |
f204e0b8 IM |
115 | |
116 | pr_devel("PSL purge request\n"); | |
117 | ||
0d400f77 | 118 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
119 | dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n"); |
120 | rc = -EIO; | |
121 | goto out; | |
122 | } | |
123 | ||
f204e0b8 IM |
124 | if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { |
125 | WARN(1, "psl_purge request while AFU not disabled!\n"); | |
126 | cxl_afu_disable(afu); | |
127 | } | |
128 | ||
129 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, | |
130 | PSL_CNTL | CXL_PSL_SCNTL_An_Pc); | |
131 | start = local_clock(); | |
132 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
133 | while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK) | |
134 | == CXL_PSL_SCNTL_An_Ps_Pending) { | |
135 | if (time_after_eq(jiffies, timeout)) { | |
136 | dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n"); | |
9bcf28cd IM |
137 | rc = -EBUSY; |
138 | goto out; | |
f204e0b8 | 139 | } |
0d400f77 | 140 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
141 | rc = -EIO; |
142 | goto out; | |
143 | } | |
144 | ||
f204e0b8 | 145 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
de369538 | 146 | pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr); |
f204e0b8 IM |
147 | if (dsisr & CXL_PSL_DSISR_TRANS) { |
148 | dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); | |
de369538 | 149 | dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar); |
f204e0b8 IM |
150 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); |
151 | } else if (dsisr) { | |
de369538 | 152 | dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr); |
f204e0b8 IM |
153 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); |
154 | } else { | |
155 | cpu_relax(); | |
156 | } | |
157 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
158 | }; | |
159 | end = local_clock(); | |
160 | pr_devel("PSL purged in %lld ns\n", end - start); | |
161 | ||
162 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, | |
163 | PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc); | |
9bcf28cd IM |
164 | out: |
165 | trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc); | |
166 | return rc; | |
f204e0b8 IM |
167 | } |
168 | ||
169 | static int spa_max_procs(int spa_size) | |
170 | { | |
171 | /* | |
172 | * From the CAIA: | |
173 | * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255 | |
174 | * Most of that junk is really just an overly-complicated way of saying | |
175 | * the last 256 bytes are __aligned(128), so it's really: | |
176 | * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255 | |
177 | * and | |
178 | * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1 | |
179 | * so | |
180 | * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256 | |
181 | * Ignore the alignment (which is safe in this case as long as we are | |
182 | * careful with our rounding) and solve for n: | |
183 | */ | |
184 | return ((spa_size / 8) - 96) / 17; | |
185 | } | |
186 | ||
05155772 | 187 | int cxl_alloc_spa(struct cxl_afu *afu) |
f204e0b8 | 188 | { |
895a7980 IM |
189 | unsigned spa_size; |
190 | ||
f204e0b8 | 191 | /* Work out how many pages to allocate */ |
2224b671 | 192 | afu->native->spa_order = -1; |
f204e0b8 | 193 | do { |
cbffa3a5 | 194 | afu->native->spa_order++; |
895a7980 IM |
195 | spa_size = (1 << afu->native->spa_order) * PAGE_SIZE; |
196 | ||
197 | if (spa_size > 0x100000) { | |
198 | dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n", | |
199 | afu->native->spa_max_procs, afu->native->spa_size); | |
200 | afu->num_procs = afu->native->spa_max_procs; | |
201 | break; | |
202 | } | |
203 | ||
204 | afu->native->spa_size = spa_size; | |
cbffa3a5 CL |
205 | afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size); |
206 | } while (afu->native->spa_max_procs < afu->num_procs); | |
f204e0b8 | 207 | |
cbffa3a5 CL |
208 | if (!(afu->native->spa = (struct cxl_process_element *) |
209 | __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) { | |
f204e0b8 IM |
210 | pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n"); |
211 | return -ENOMEM; | |
212 | } | |
213 | pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n", | |
cbffa3a5 | 214 | 1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs); |
f204e0b8 | 215 | |
05155772 DA |
216 | return 0; |
217 | } | |
218 | ||
219 | static void attach_spa(struct cxl_afu *afu) | |
220 | { | |
221 | u64 spap; | |
222 | ||
cbffa3a5 CL |
223 | afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa + |
224 | ((afu->native->spa_max_procs + 3) * 128)); | |
f204e0b8 | 225 | |
cbffa3a5 CL |
226 | spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr; |
227 | spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size; | |
f204e0b8 | 228 | spap |= CXL_PSL_SPAP_V; |
cbffa3a5 CL |
229 | pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", |
230 | afu->native->spa, afu->native->spa_max_procs, | |
231 | afu->native->sw_command_status, spap); | |
f204e0b8 | 232 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap); |
f204e0b8 IM |
233 | } |
234 | ||
05155772 | 235 | static inline void detach_spa(struct cxl_afu *afu) |
f204e0b8 | 236 | { |
db7933f3 | 237 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); |
05155772 DA |
238 | } |
239 | ||
240 | void cxl_release_spa(struct cxl_afu *afu) | |
241 | { | |
cbffa3a5 CL |
242 | if (afu->native->spa) { |
243 | free_pages((unsigned long) afu->native->spa, | |
244 | afu->native->spa_order); | |
245 | afu->native->spa = NULL; | |
05155772 | 246 | } |
f204e0b8 IM |
247 | } |
248 | ||
249 | int cxl_tlb_slb_invalidate(struct cxl *adapter) | |
250 | { | |
251 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
252 | ||
253 | pr_devel("CXL adapter wide TLBIA & SLBIA\n"); | |
254 | ||
255 | cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A); | |
256 | ||
257 | cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL); | |
258 | while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) { | |
259 | if (time_after_eq(jiffies, timeout)) { | |
260 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n"); | |
261 | return -EBUSY; | |
262 | } | |
0d400f77 | 263 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 264 | return -EIO; |
f204e0b8 IM |
265 | cpu_relax(); |
266 | } | |
267 | ||
268 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL); | |
269 | while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) { | |
270 | if (time_after_eq(jiffies, timeout)) { | |
271 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n"); | |
272 | return -EBUSY; | |
273 | } | |
0d400f77 | 274 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 275 | return -EIO; |
f204e0b8 IM |
276 | cpu_relax(); |
277 | } | |
278 | return 0; | |
279 | } | |
280 | ||
f204e0b8 IM |
281 | static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1) |
282 | { | |
283 | int rc; | |
284 | ||
285 | /* 1. Disable SSTP by writing 0 to SSTP1[V] */ | |
286 | cxl_p2n_write(afu, CXL_SSTP1_An, 0); | |
287 | ||
288 | /* 2. Invalidate all SLB entries */ | |
289 | if ((rc = cxl_afu_slbia(afu))) | |
290 | return rc; | |
291 | ||
292 | /* 3. Set SSTP0_An */ | |
293 | cxl_p2n_write(afu, CXL_SSTP0_An, sstp0); | |
294 | ||
295 | /* 4. Set SSTP1_An */ | |
296 | cxl_p2n_write(afu, CXL_SSTP1_An, sstp1); | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
301 | /* Using per slice version may improve performance here. (ie. SLBIA_An) */ | |
302 | static void slb_invalid(struct cxl_context *ctx) | |
303 | { | |
304 | struct cxl *adapter = ctx->afu->adapter; | |
305 | u64 slbia; | |
306 | ||
cbffa3a5 | 307 | WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex)); |
f204e0b8 IM |
308 | |
309 | cxl_p1_write(adapter, CXL_PSL_LBISEL, | |
310 | ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) | | |
311 | be32_to_cpu(ctx->elem->lpid)); | |
312 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID); | |
313 | ||
314 | while (1) { | |
0d400f77 | 315 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 316 | break; |
f204e0b8 IM |
317 | slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA); |
318 | if (!(slbia & CXL_TLB_SLB_P)) | |
319 | break; | |
320 | cpu_relax(); | |
321 | } | |
322 | } | |
323 | ||
324 | static int do_process_element_cmd(struct cxl_context *ctx, | |
325 | u64 cmd, u64 pe_state) | |
326 | { | |
327 | u64 state; | |
a98e6e9f | 328 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
9bcf28cd IM |
329 | int rc = 0; |
330 | ||
331 | trace_cxl_llcmd(ctx, cmd); | |
f204e0b8 IM |
332 | |
333 | WARN_ON(!ctx->afu->enabled); | |
334 | ||
335 | ctx->elem->software_state = cpu_to_be32(pe_state); | |
336 | smp_wmb(); | |
cbffa3a5 | 337 | *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe); |
f204e0b8 IM |
338 | smp_mb(); |
339 | cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe); | |
340 | while (1) { | |
a98e6e9f IM |
341 | if (time_after_eq(jiffies, timeout)) { |
342 | dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n"); | |
9bcf28cd IM |
343 | rc = -EBUSY; |
344 | goto out; | |
a98e6e9f | 345 | } |
0d400f77 | 346 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
0b3f9c75 DA |
347 | dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n"); |
348 | rc = -EIO; | |
349 | goto out; | |
350 | } | |
cbffa3a5 | 351 | state = be64_to_cpup(ctx->afu->native->sw_command_status); |
f204e0b8 IM |
352 | if (state == ~0ULL) { |
353 | pr_err("cxl: Error adding process element to AFU\n"); | |
9bcf28cd IM |
354 | rc = -1; |
355 | goto out; | |
f204e0b8 IM |
356 | } |
357 | if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) == | |
358 | (cmd | (cmd >> 16) | ctx->pe)) | |
359 | break; | |
360 | /* | |
361 | * The command won't finish in the PSL if there are | |
362 | * outstanding DSIs. Hence we need to yield here in | |
363 | * case there are outstanding DSIs that we need to | |
364 | * service. Tuning possiblity: we could wait for a | |
365 | * while before sched | |
366 | */ | |
367 | schedule(); | |
368 | ||
369 | } | |
9bcf28cd IM |
370 | out: |
371 | trace_cxl_llcmd_done(ctx, cmd, rc); | |
372 | return rc; | |
f204e0b8 IM |
373 | } |
374 | ||
375 | static int add_process_element(struct cxl_context *ctx) | |
376 | { | |
377 | int rc = 0; | |
378 | ||
cbffa3a5 | 379 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
380 | pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe); |
381 | if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V))) | |
382 | ctx->pe_inserted = true; | |
383 | pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 384 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
385 | return rc; |
386 | } | |
387 | ||
388 | static int terminate_process_element(struct cxl_context *ctx) | |
389 | { | |
390 | int rc = 0; | |
391 | ||
392 | /* fast path terminate if it's already invalid */ | |
393 | if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V))) | |
394 | return rc; | |
395 | ||
cbffa3a5 | 396 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 | 397 | pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe); |
0b3f9c75 DA |
398 | /* We could be asked to terminate when the hw is down. That |
399 | * should always succeed: it's not running if the hw has gone | |
400 | * away and is being reset. | |
401 | */ | |
0d400f77 | 402 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
0b3f9c75 DA |
403 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE, |
404 | CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T); | |
f204e0b8 IM |
405 | ctx->elem->software_state = 0; /* Remove Valid bit */ |
406 | pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 407 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
408 | return rc; |
409 | } | |
410 | ||
411 | static int remove_process_element(struct cxl_context *ctx) | |
412 | { | |
413 | int rc = 0; | |
414 | ||
cbffa3a5 | 415 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 | 416 | pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe); |
0b3f9c75 DA |
417 | |
418 | /* We could be asked to remove when the hw is down. Again, if | |
419 | * the hw is down, the PE is gone, so we succeed. | |
420 | */ | |
0d400f77 | 421 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
0b3f9c75 DA |
422 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0); |
423 | ||
424 | if (!rc) | |
f204e0b8 IM |
425 | ctx->pe_inserted = false; |
426 | slb_invalid(ctx); | |
427 | pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 428 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
429 | |
430 | return rc; | |
431 | } | |
432 | ||
1a1a94b8 | 433 | void cxl_assign_psn_space(struct cxl_context *ctx) |
f204e0b8 IM |
434 | { |
435 | if (!ctx->afu->pp_size || ctx->master) { | |
436 | ctx->psn_phys = ctx->afu->psn_phys; | |
437 | ctx->psn_size = ctx->afu->adapter->ps_size; | |
438 | } else { | |
439 | ctx->psn_phys = ctx->afu->psn_phys + | |
cbffa3a5 | 440 | (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe); |
f204e0b8 IM |
441 | ctx->psn_size = ctx->afu->pp_size; |
442 | } | |
443 | } | |
444 | ||
445 | static int activate_afu_directed(struct cxl_afu *afu) | |
446 | { | |
447 | int rc; | |
448 | ||
449 | dev_info(&afu->dev, "Activating AFU directed mode\n"); | |
450 | ||
4108efb0 | 451 | afu->num_procs = afu->max_procs_virtualised; |
cbffa3a5 | 452 | if (afu->native->spa == NULL) { |
05155772 DA |
453 | if (cxl_alloc_spa(afu)) |
454 | return -ENOMEM; | |
455 | } | |
456 | attach_spa(afu); | |
f204e0b8 IM |
457 | |
458 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU); | |
459 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); | |
460 | cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L); | |
461 | ||
462 | afu->current_mode = CXL_MODE_DIRECTED; | |
f204e0b8 IM |
463 | |
464 | if ((rc = cxl_chardev_m_afu_add(afu))) | |
465 | return rc; | |
466 | ||
467 | if ((rc = cxl_sysfs_afu_m_add(afu))) | |
468 | goto err; | |
469 | ||
470 | if ((rc = cxl_chardev_s_afu_add(afu))) | |
471 | goto err1; | |
472 | ||
473 | return 0; | |
474 | err1: | |
475 | cxl_sysfs_afu_m_remove(afu); | |
476 | err: | |
477 | cxl_chardev_afu_remove(afu); | |
478 | return rc; | |
479 | } | |
480 | ||
481 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
482 | #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE) | |
483 | #else | |
484 | #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE)) | |
485 | #endif | |
486 | ||
2f663527 MN |
487 | static u64 calculate_sr(struct cxl_context *ctx) |
488 | { | |
489 | u64 sr = 0; | |
490 | ||
e606e035 | 491 | set_endian(sr); |
2f663527 MN |
492 | if (ctx->master) |
493 | sr |= CXL_PSL_SR_An_MP; | |
494 | if (mfspr(SPRN_LPCR) & LPCR_TC) | |
495 | sr |= CXL_PSL_SR_An_TC; | |
496 | if (ctx->kernel) { | |
7a0d85d3 IM |
497 | if (!ctx->real_mode) |
498 | sr |= CXL_PSL_SR_An_R; | |
499 | sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV; | |
2f663527 MN |
500 | } else { |
501 | sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; | |
2f663527 MN |
502 | sr &= ~(CXL_PSL_SR_An_HV); |
503 | if (!test_tsk_thread_flag(current, TIF_32BIT)) | |
504 | sr |= CXL_PSL_SR_An_SF; | |
505 | } | |
506 | return sr; | |
507 | } | |
508 | ||
292841b0 IM |
509 | static void update_ivtes_directed(struct cxl_context *ctx) |
510 | { | |
511 | bool need_update = (ctx->status == STARTED); | |
512 | int r; | |
513 | ||
514 | if (need_update) { | |
515 | WARN_ON(terminate_process_element(ctx)); | |
516 | WARN_ON(remove_process_element(ctx)); | |
517 | } | |
518 | ||
519 | for (r = 0; r < CXL_IRQ_RANGES; r++) { | |
520 | ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]); | |
521 | ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]); | |
522 | } | |
523 | ||
524 | /* | |
525 | * Theoretically we could use the update llcmd, instead of a | |
526 | * terminate/remove/add (or if an atomic update was required we could | |
527 | * do a suspend/update/resume), however it seems there might be issues | |
528 | * with the update llcmd on some cards (including those using an XSL on | |
529 | * an ASIC) so for now it's safest to go with the commands that are | |
530 | * known to work. In the future if we come across a situation where the | |
531 | * card may be performing transactions using the same PE while we are | |
532 | * doing this update we might need to revisit this. | |
533 | */ | |
534 | if (need_update) | |
535 | WARN_ON(add_process_element(ctx)); | |
536 | } | |
537 | ||
f204e0b8 IM |
538 | static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr) |
539 | { | |
2f663527 | 540 | u32 pid; |
292841b0 | 541 | int result; |
f204e0b8 | 542 | |
1a1a94b8 | 543 | cxl_assign_psn_space(ctx); |
f204e0b8 IM |
544 | |
545 | ctx->elem->ctxtime = 0; /* disable */ | |
546 | ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID)); | |
547 | ctx->elem->haurp = 0; /* disable */ | |
548 | ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1)); | |
549 | ||
2f663527 MN |
550 | pid = current->pid; |
551 | if (ctx->kernel) | |
552 | pid = 0; | |
f204e0b8 | 553 | ctx->elem->common.tid = 0; |
2f663527 MN |
554 | ctx->elem->common.pid = cpu_to_be32(pid); |
555 | ||
556 | ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); | |
f204e0b8 IM |
557 | |
558 | ctx->elem->common.csrp = 0; /* disable */ | |
559 | ctx->elem->common.aurp0 = 0; /* disable */ | |
560 | ctx->elem->common.aurp1 = 0; /* disable */ | |
561 | ||
562 | cxl_prefault(ctx, wed); | |
563 | ||
564 | ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0); | |
565 | ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1); | |
566 | ||
3c206fa7 IM |
567 | /* |
568 | * Ensure we have the multiplexed PSL interrupt set up to take faults | |
569 | * for kernel contexts that may not have allocated any AFU IRQs at all: | |
570 | */ | |
571 | if (ctx->irqs.range[0] == 0) { | |
572 | ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq; | |
573 | ctx->irqs.range[0] = 1; | |
574 | } | |
575 | ||
292841b0 | 576 | update_ivtes_directed(ctx); |
f204e0b8 IM |
577 | |
578 | ctx->elem->common.amr = cpu_to_be64(amr); | |
579 | ctx->elem->common.wed = cpu_to_be64(wed); | |
580 | ||
581 | /* first guy needs to enable */ | |
5be587b1 | 582 | if ((result = cxl_ops->afu_check_and_enable(ctx->afu))) |
f204e0b8 IM |
583 | return result; |
584 | ||
368857c1 | 585 | return add_process_element(ctx); |
f204e0b8 IM |
586 | } |
587 | ||
588 | static int deactivate_afu_directed(struct cxl_afu *afu) | |
589 | { | |
590 | dev_info(&afu->dev, "Deactivating AFU directed mode\n"); | |
591 | ||
592 | afu->current_mode = 0; | |
593 | afu->num_procs = 0; | |
594 | ||
595 | cxl_sysfs_afu_m_remove(afu); | |
596 | cxl_chardev_afu_remove(afu); | |
597 | ||
5be587b1 | 598 | cxl_ops->afu_reset(afu); |
f204e0b8 IM |
599 | cxl_afu_disable(afu); |
600 | cxl_psl_purge(afu); | |
601 | ||
f204e0b8 IM |
602 | return 0; |
603 | } | |
604 | ||
605 | static int activate_dedicated_process(struct cxl_afu *afu) | |
606 | { | |
607 | dev_info(&afu->dev, "Activating dedicated process mode\n"); | |
608 | ||
609 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process); | |
610 | ||
611 | cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */ | |
612 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */ | |
613 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); | |
614 | cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID)); | |
615 | cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */ | |
616 | cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1)); | |
617 | ||
618 | cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */ | |
619 | cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */ | |
620 | cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */ | |
621 | ||
622 | afu->current_mode = CXL_MODE_DEDICATED; | |
623 | afu->num_procs = 1; | |
624 | ||
625 | return cxl_chardev_d_afu_add(afu); | |
626 | } | |
627 | ||
292841b0 IM |
628 | static void update_ivtes_dedicated(struct cxl_context *ctx) |
629 | { | |
630 | struct cxl_afu *afu = ctx->afu; | |
631 | ||
632 | cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, | |
633 | (((u64)ctx->irqs.offset[0] & 0xffff) << 48) | | |
634 | (((u64)ctx->irqs.offset[1] & 0xffff) << 32) | | |
635 | (((u64)ctx->irqs.offset[2] & 0xffff) << 16) | | |
636 | ((u64)ctx->irqs.offset[3] & 0xffff)); | |
637 | cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64) | |
638 | (((u64)ctx->irqs.range[0] & 0xffff) << 48) | | |
639 | (((u64)ctx->irqs.range[1] & 0xffff) << 32) | | |
640 | (((u64)ctx->irqs.range[2] & 0xffff) << 16) | | |
641 | ((u64)ctx->irqs.range[3] & 0xffff)); | |
642 | } | |
643 | ||
f204e0b8 IM |
644 | static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr) |
645 | { | |
646 | struct cxl_afu *afu = ctx->afu; | |
2f663527 | 647 | u64 pid; |
f204e0b8 IM |
648 | int rc; |
649 | ||
2f663527 MN |
650 | pid = (u64)current->pid << 32; |
651 | if (ctx->kernel) | |
652 | pid = 0; | |
653 | cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid); | |
654 | ||
655 | cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx)); | |
f204e0b8 IM |
656 | |
657 | if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1))) | |
658 | return rc; | |
659 | ||
660 | cxl_prefault(ctx, wed); | |
661 | ||
292841b0 | 662 | update_ivtes_dedicated(ctx); |
f204e0b8 IM |
663 | |
664 | cxl_p2n_write(afu, CXL_PSL_AMR_An, amr); | |
665 | ||
666 | /* master only context for dedicated */ | |
1a1a94b8 | 667 | cxl_assign_psn_space(ctx); |
f204e0b8 | 668 | |
5be587b1 | 669 | if ((rc = cxl_ops->afu_reset(afu))) |
f204e0b8 IM |
670 | return rc; |
671 | ||
672 | cxl_p2n_write(afu, CXL_PSL_WED_An, wed); | |
673 | ||
674 | return afu_enable(afu); | |
675 | } | |
676 | ||
677 | static int deactivate_dedicated_process(struct cxl_afu *afu) | |
678 | { | |
679 | dev_info(&afu->dev, "Deactivating dedicated process mode\n"); | |
680 | ||
681 | afu->current_mode = 0; | |
682 | afu->num_procs = 0; | |
683 | ||
684 | cxl_chardev_afu_remove(afu); | |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
2b04cf31 | 689 | static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode) |
f204e0b8 IM |
690 | { |
691 | if (mode == CXL_MODE_DIRECTED) | |
692 | return deactivate_afu_directed(afu); | |
693 | if (mode == CXL_MODE_DEDICATED) | |
694 | return deactivate_dedicated_process(afu); | |
695 | return 0; | |
696 | } | |
697 | ||
2b04cf31 | 698 | static int native_afu_activate_mode(struct cxl_afu *afu, int mode) |
f204e0b8 IM |
699 | { |
700 | if (!mode) | |
701 | return 0; | |
702 | if (!(mode & afu->modes_supported)) | |
703 | return -EINVAL; | |
704 | ||
0d400f77 | 705 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
706 | WARN(1, "Device link is down, refusing to activate!\n"); |
707 | return -EIO; | |
708 | } | |
709 | ||
f204e0b8 IM |
710 | if (mode == CXL_MODE_DIRECTED) |
711 | return activate_afu_directed(afu); | |
712 | if (mode == CXL_MODE_DEDICATED) | |
713 | return activate_dedicated_process(afu); | |
714 | ||
715 | return -EINVAL; | |
716 | } | |
717 | ||
2b04cf31 FB |
718 | static int native_attach_process(struct cxl_context *ctx, bool kernel, |
719 | u64 wed, u64 amr) | |
f204e0b8 | 720 | { |
0d400f77 | 721 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
0b3f9c75 DA |
722 | WARN(1, "Device link is down, refusing to attach process!\n"); |
723 | return -EIO; | |
724 | } | |
725 | ||
f204e0b8 IM |
726 | ctx->kernel = kernel; |
727 | if (ctx->afu->current_mode == CXL_MODE_DIRECTED) | |
728 | return attach_afu_directed(ctx, wed, amr); | |
729 | ||
730 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) | |
731 | return attach_dedicated(ctx, wed, amr); | |
732 | ||
733 | return -EINVAL; | |
734 | } | |
735 | ||
736 | static inline int detach_process_native_dedicated(struct cxl_context *ctx) | |
737 | { | |
5be587b1 | 738 | cxl_ops->afu_reset(ctx->afu); |
f204e0b8 IM |
739 | cxl_afu_disable(ctx->afu); |
740 | cxl_psl_purge(ctx->afu); | |
741 | return 0; | |
742 | } | |
743 | ||
292841b0 IM |
744 | static void native_update_ivtes(struct cxl_context *ctx) |
745 | { | |
746 | if (ctx->afu->current_mode == CXL_MODE_DIRECTED) | |
747 | return update_ivtes_directed(ctx); | |
748 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) | |
749 | return update_ivtes_dedicated(ctx); | |
750 | WARN(1, "native_update_ivtes: Bad mode\n"); | |
751 | } | |
752 | ||
f204e0b8 IM |
753 | static inline int detach_process_native_afu_directed(struct cxl_context *ctx) |
754 | { | |
755 | if (!ctx->pe_inserted) | |
756 | return 0; | |
757 | if (terminate_process_element(ctx)) | |
758 | return -1; | |
759 | if (remove_process_element(ctx)) | |
760 | return -1; | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
2b04cf31 | 765 | static int native_detach_process(struct cxl_context *ctx) |
f204e0b8 | 766 | { |
9bcf28cd IM |
767 | trace_cxl_detach(ctx); |
768 | ||
f204e0b8 IM |
769 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) |
770 | return detach_process_native_dedicated(ctx); | |
771 | ||
772 | return detach_process_native_afu_directed(ctx); | |
773 | } | |
774 | ||
2b04cf31 | 775 | static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info) |
f204e0b8 IM |
776 | { |
777 | u64 pidtid; | |
778 | ||
0b3f9c75 DA |
779 | /* If the adapter has gone away, we can't get any meaningful |
780 | * information. | |
781 | */ | |
0d400f77 | 782 | if (!cxl_ops->link_ok(afu->adapter, afu)) |
0b3f9c75 DA |
783 | return -EIO; |
784 | ||
bc78b05b IM |
785 | info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
786 | info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); | |
787 | info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An); | |
788 | pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An); | |
f204e0b8 IM |
789 | info->pid = pidtid >> 32; |
790 | info->tid = pidtid & 0xffffffff; | |
bc78b05b IM |
791 | info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An); |
792 | info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
444c4ba4 | 793 | info->proc_handle = 0; |
f204e0b8 IM |
794 | |
795 | return 0; | |
796 | } | |
797 | ||
6d382616 | 798 | void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx) |
d56d301b FB |
799 | { |
800 | u64 fir1, fir2, fir_slice, serr, afu_debug; | |
801 | ||
802 | fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1); | |
803 | fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2); | |
804 | fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An); | |
d56d301b FB |
805 | afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An); |
806 | ||
d56d301b FB |
807 | dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1); |
808 | dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2); | |
6d382616 FB |
809 | if (ctx->afu->adapter->native->sl_ops->register_serr_irq) { |
810 | serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An); | |
811 | dev_crit(&ctx->afu->dev, "PSL_SERR_An: 0x%016llx\n", serr); | |
812 | } | |
d56d301b FB |
813 | dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); |
814 | dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); | |
6d382616 FB |
815 | } |
816 | ||
817 | static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx, | |
818 | u64 dsisr, u64 errstat) | |
819 | { | |
820 | ||
821 | dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat); | |
d56d301b | 822 | |
6d382616 FB |
823 | if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers) |
824 | ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx); | |
825 | ||
826 | if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) { | |
827 | dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n"); | |
828 | ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter); | |
829 | } | |
d56d301b | 830 | |
5be587b1 | 831 | return cxl_ops->ack_irq(ctx, 0, errstat); |
d56d301b FB |
832 | } |
833 | ||
834 | static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info) | |
835 | { | |
836 | if (irq_info->dsisr & CXL_PSL_DSISR_TRANS) | |
837 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); | |
838 | else | |
839 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); | |
840 | ||
841 | return IRQ_HANDLED; | |
842 | } | |
843 | ||
2b04cf31 | 844 | static irqreturn_t native_irq_multiplexed(int irq, void *data) |
d56d301b FB |
845 | { |
846 | struct cxl_afu *afu = data; | |
847 | struct cxl_context *ctx; | |
848 | struct cxl_irq_info irq_info; | |
849 | int ph = cxl_p2n_read(afu, CXL_PSL_PEHandle_An) & 0xffff; | |
850 | int ret; | |
851 | ||
2b04cf31 | 852 | if ((ret = native_get_irq_info(afu, &irq_info))) { |
d56d301b FB |
853 | WARN(1, "Unable to get CXL IRQ Info: %i\n", ret); |
854 | return fail_psl_irq(afu, &irq_info); | |
855 | } | |
856 | ||
857 | rcu_read_lock(); | |
858 | ctx = idr_find(&afu->contexts_idr, ph); | |
859 | if (ctx) { | |
860 | ret = cxl_irq(irq, ctx, &irq_info); | |
861 | rcu_read_unlock(); | |
862 | return ret; | |
863 | } | |
864 | rcu_read_unlock(); | |
865 | ||
866 | WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR" | |
867 | " %016llx\n(Possible AFU HW issue - was a term/remove acked" | |
868 | " with outstanding transactions?)\n", ph, irq_info.dsisr, | |
869 | irq_info.dar); | |
870 | return fail_psl_irq(afu, &irq_info); | |
871 | } | |
872 | ||
2bc79ffc MN |
873 | void native_irq_wait(struct cxl_context *ctx) |
874 | { | |
875 | u64 dsisr; | |
876 | int timeout = 1000; | |
877 | int ph; | |
878 | ||
879 | /* | |
880 | * Wait until no further interrupts are presented by the PSL | |
881 | * for this context. | |
882 | */ | |
883 | while (timeout--) { | |
884 | ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff; | |
885 | if (ph != ctx->pe) | |
886 | return; | |
887 | dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An); | |
888 | if ((dsisr & CXL_PSL_DSISR_PENDING) == 0) | |
889 | return; | |
890 | /* | |
891 | * We are waiting for the workqueue to process our | |
892 | * irq, so need to let that run here. | |
893 | */ | |
894 | msleep(1); | |
895 | } | |
896 | ||
897 | dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i" | |
898 | " DSISR %016llx!\n", ph, dsisr); | |
899 | return; | |
900 | } | |
901 | ||
2b04cf31 | 902 | static irqreturn_t native_slice_irq_err(int irq, void *data) |
d56d301b FB |
903 | { |
904 | struct cxl_afu *afu = data; | |
905 | u64 fir_slice, errstat, serr, afu_debug; | |
906 | ||
6d382616 FB |
907 | /* |
908 | * slice err interrupt is only used with full PSL (no XSL) | |
909 | */ | |
d56d301b FB |
910 | WARN(irq, "CXL SLICE ERROR interrupt %i\n", irq); |
911 | ||
912 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
913 | fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An); | |
914 | errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
915 | afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An); | |
916 | dev_crit(&afu->dev, "PSL_SERR_An: 0x%016llx\n", serr); | |
917 | dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); | |
918 | dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat); | |
919 | dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); | |
920 | ||
921 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); | |
922 | ||
923 | return IRQ_HANDLED; | |
924 | } | |
925 | ||
6d382616 FB |
926 | void cxl_native_err_irq_dump_regs(struct cxl *adapter) |
927 | { | |
928 | u64 fir1, fir2; | |
929 | ||
930 | fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1); | |
931 | fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2); | |
932 | ||
933 | dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2); | |
934 | } | |
935 | ||
2b04cf31 | 936 | static irqreturn_t native_irq_err(int irq, void *data) |
d56d301b FB |
937 | { |
938 | struct cxl *adapter = data; | |
6d382616 | 939 | u64 err_ivte; |
d56d301b FB |
940 | |
941 | WARN(1, "CXL ERROR interrupt %i\n", irq); | |
942 | ||
943 | err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE); | |
944 | dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte); | |
945 | ||
6d382616 FB |
946 | if (adapter->native->sl_ops->debugfs_stop_trace) { |
947 | dev_crit(&adapter->dev, "STOPPING CXL TRACE\n"); | |
948 | adapter->native->sl_ops->debugfs_stop_trace(adapter); | |
949 | } | |
d56d301b | 950 | |
6d382616 FB |
951 | if (adapter->native->sl_ops->err_irq_dump_registers) |
952 | adapter->native->sl_ops->err_irq_dump_registers(adapter); | |
d56d301b FB |
953 | |
954 | return IRQ_HANDLED; | |
955 | } | |
956 | ||
2b04cf31 | 957 | int cxl_native_register_psl_err_irq(struct cxl *adapter) |
d56d301b FB |
958 | { |
959 | int rc; | |
960 | ||
961 | adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", | |
962 | dev_name(&adapter->dev)); | |
963 | if (!adapter->irq_name) | |
964 | return -ENOMEM; | |
965 | ||
2b04cf31 | 966 | if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter, |
cbffa3a5 CL |
967 | &adapter->native->err_hwirq, |
968 | &adapter->native->err_virq, | |
d56d301b FB |
969 | adapter->irq_name))) { |
970 | kfree(adapter->irq_name); | |
971 | adapter->irq_name = NULL; | |
972 | return rc; | |
973 | } | |
974 | ||
cbffa3a5 | 975 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff); |
d56d301b FB |
976 | |
977 | return 0; | |
978 | } | |
979 | ||
2b04cf31 | 980 | void cxl_native_release_psl_err_irq(struct cxl *adapter) |
d56d301b | 981 | { |
cbffa3a5 | 982 | if (adapter->native->err_virq != irq_find_mapping(NULL, adapter->native->err_hwirq)) |
d56d301b FB |
983 | return; |
984 | ||
985 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000); | |
cbffa3a5 CL |
986 | cxl_unmap_irq(adapter->native->err_virq, adapter); |
987 | cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq); | |
d56d301b FB |
988 | kfree(adapter->irq_name); |
989 | } | |
990 | ||
2b04cf31 | 991 | int cxl_native_register_serr_irq(struct cxl_afu *afu) |
d56d301b FB |
992 | { |
993 | u64 serr; | |
994 | int rc; | |
995 | ||
996 | afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", | |
997 | dev_name(&afu->dev)); | |
998 | if (!afu->err_irq_name) | |
999 | return -ENOMEM; | |
1000 | ||
2b04cf31 | 1001 | if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu, |
d56d301b FB |
1002 | &afu->serr_hwirq, |
1003 | &afu->serr_virq, afu->err_irq_name))) { | |
1004 | kfree(afu->err_irq_name); | |
1005 | afu->err_irq_name = NULL; | |
1006 | return rc; | |
1007 | } | |
1008 | ||
1009 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
1010 | serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff); | |
1011 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
2b04cf31 | 1016 | void cxl_native_release_serr_irq(struct cxl_afu *afu) |
d56d301b FB |
1017 | { |
1018 | if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq)) | |
1019 | return; | |
1020 | ||
1021 | cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000); | |
1022 | cxl_unmap_irq(afu->serr_virq, afu); | |
5be587b1 | 1023 | cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq); |
d56d301b FB |
1024 | kfree(afu->err_irq_name); |
1025 | } | |
1026 | ||
2b04cf31 | 1027 | int cxl_native_register_psl_irq(struct cxl_afu *afu) |
d56d301b FB |
1028 | { |
1029 | int rc; | |
1030 | ||
1031 | afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s", | |
1032 | dev_name(&afu->dev)); | |
1033 | if (!afu->psl_irq_name) | |
1034 | return -ENOMEM; | |
1035 | ||
cbffa3a5 CL |
1036 | if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed, |
1037 | afu, &afu->native->psl_hwirq, &afu->native->psl_virq, | |
d56d301b FB |
1038 | afu->psl_irq_name))) { |
1039 | kfree(afu->psl_irq_name); | |
1040 | afu->psl_irq_name = NULL; | |
1041 | } | |
1042 | return rc; | |
1043 | } | |
1044 | ||
2b04cf31 | 1045 | void cxl_native_release_psl_irq(struct cxl_afu *afu) |
d56d301b | 1046 | { |
cbffa3a5 | 1047 | if (afu->native->psl_virq != irq_find_mapping(NULL, afu->native->psl_hwirq)) |
d56d301b FB |
1048 | return; |
1049 | ||
cbffa3a5 CL |
1050 | cxl_unmap_irq(afu->native->psl_virq, afu); |
1051 | cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq); | |
d56d301b FB |
1052 | kfree(afu->psl_irq_name); |
1053 | } | |
1054 | ||
f204e0b8 IM |
1055 | static void recover_psl_err(struct cxl_afu *afu, u64 errstat) |
1056 | { | |
1057 | u64 dsisr; | |
1058 | ||
de369538 | 1059 | pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat); |
f204e0b8 IM |
1060 | |
1061 | /* Clear PSL_DSISR[PE] */ | |
1062 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
1063 | cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE); | |
1064 | ||
1065 | /* Write 1s to clear error status bits */ | |
1066 | cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat); | |
1067 | } | |
1068 | ||
2b04cf31 | 1069 | static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask) |
f204e0b8 | 1070 | { |
9bcf28cd | 1071 | trace_cxl_psl_irq_ack(ctx, tfc); |
f204e0b8 IM |
1072 | if (tfc) |
1073 | cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc); | |
1074 | if (psl_reset_mask) | |
1075 | recover_psl_err(ctx->afu, psl_reset_mask); | |
1076 | ||
1077 | return 0; | |
1078 | } | |
1079 | ||
1080 | int cxl_check_error(struct cxl_afu *afu) | |
1081 | { | |
1082 | return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL); | |
1083 | } | |
d56d301b | 1084 | |
4752876c CL |
1085 | static bool native_support_attributes(const char *attr_name, |
1086 | enum cxl_attrs type) | |
1087 | { | |
1088 | return true; | |
1089 | } | |
1090 | ||
2b04cf31 | 1091 | static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out) |
d56d301b | 1092 | { |
0d400f77 | 1093 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
5be587b1 FB |
1094 | return -EIO; |
1095 | if (unlikely(off >= afu->crs_len)) | |
1096 | return -ERANGE; | |
cbffa3a5 | 1097 | *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset + |
5be587b1 FB |
1098 | (cr * afu->crs_len) + off); |
1099 | return 0; | |
d56d301b FB |
1100 | } |
1101 | ||
2b04cf31 | 1102 | static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out) |
d56d301b | 1103 | { |
0d400f77 | 1104 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
5be587b1 FB |
1105 | return -EIO; |
1106 | if (unlikely(off >= afu->crs_len)) | |
1107 | return -ERANGE; | |
cbffa3a5 | 1108 | *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset + |
5be587b1 FB |
1109 | (cr * afu->crs_len) + off); |
1110 | return 0; | |
d56d301b FB |
1111 | } |
1112 | ||
2b04cf31 | 1113 | static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out) |
d56d301b FB |
1114 | { |
1115 | u64 aligned_off = off & ~0x3L; | |
1116 | u32 val; | |
5be587b1 | 1117 | int rc; |
d56d301b | 1118 | |
2b04cf31 | 1119 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
5be587b1 FB |
1120 | if (!rc) |
1121 | *out = (val >> ((off & 0x3) * 8)) & 0xffff; | |
1122 | return rc; | |
d56d301b FB |
1123 | } |
1124 | ||
2b04cf31 | 1125 | static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out) |
d56d301b FB |
1126 | { |
1127 | u64 aligned_off = off & ~0x3L; | |
1128 | u32 val; | |
5be587b1 | 1129 | int rc; |
d56d301b | 1130 | |
2b04cf31 | 1131 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
5be587b1 FB |
1132 | if (!rc) |
1133 | *out = (val >> ((off & 0x3) * 8)) & 0xff; | |
1134 | return rc; | |
d56d301b | 1135 | } |
5be587b1 | 1136 | |
d601ea91 FB |
1137 | static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in) |
1138 | { | |
0d400f77 | 1139 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
d601ea91 FB |
1140 | return -EIO; |
1141 | if (unlikely(off >= afu->crs_len)) | |
1142 | return -ERANGE; | |
1143 | out_le32(afu->native->afu_desc_mmio + afu->crs_offset + | |
1144 | (cr * afu->crs_len) + off, in); | |
1145 | return 0; | |
1146 | } | |
1147 | ||
1148 | static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in) | |
1149 | { | |
1150 | u64 aligned_off = off & ~0x3L; | |
1151 | u32 val32, mask, shift; | |
1152 | int rc; | |
1153 | ||
1154 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); | |
1155 | if (rc) | |
1156 | return rc; | |
1157 | shift = (off & 0x3) * 8; | |
1158 | WARN_ON(shift == 24); | |
1159 | mask = 0xffff << shift; | |
1160 | val32 = (val32 & ~mask) | (in << shift); | |
1161 | ||
1162 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); | |
1163 | return rc; | |
1164 | } | |
1165 | ||
1166 | static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in) | |
1167 | { | |
1168 | u64 aligned_off = off & ~0x3L; | |
1169 | u32 val32, mask, shift; | |
1170 | int rc; | |
1171 | ||
1172 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); | |
1173 | if (rc) | |
1174 | return rc; | |
1175 | shift = (off & 0x3) * 8; | |
1176 | mask = 0xff << shift; | |
1177 | val32 = (val32 & ~mask) | (in << shift); | |
1178 | ||
1179 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); | |
1180 | return rc; | |
1181 | } | |
1182 | ||
5be587b1 FB |
1183 | const struct cxl_backend_ops cxl_native_ops = { |
1184 | .module = THIS_MODULE, | |
2b04cf31 FB |
1185 | .adapter_reset = cxl_pci_reset, |
1186 | .alloc_one_irq = cxl_pci_alloc_one_irq, | |
1187 | .release_one_irq = cxl_pci_release_one_irq, | |
1188 | .alloc_irq_ranges = cxl_pci_alloc_irq_ranges, | |
1189 | .release_irq_ranges = cxl_pci_release_irq_ranges, | |
1190 | .setup_irq = cxl_pci_setup_irq, | |
1191 | .handle_psl_slice_error = native_handle_psl_slice_error, | |
5be587b1 | 1192 | .psl_interrupt = NULL, |
2b04cf31 | 1193 | .ack_irq = native_ack_irq, |
2bc79ffc | 1194 | .irq_wait = native_irq_wait, |
2b04cf31 FB |
1195 | .attach_process = native_attach_process, |
1196 | .detach_process = native_detach_process, | |
292841b0 | 1197 | .update_ivtes = native_update_ivtes, |
4752876c | 1198 | .support_attributes = native_support_attributes, |
5be587b1 | 1199 | .link_ok = cxl_adapter_link_ok, |
2b04cf31 FB |
1200 | .release_afu = cxl_pci_release_afu, |
1201 | .afu_read_err_buffer = cxl_pci_afu_read_err_buffer, | |
1202 | .afu_check_and_enable = native_afu_check_and_enable, | |
1203 | .afu_activate_mode = native_afu_activate_mode, | |
1204 | .afu_deactivate_mode = native_afu_deactivate_mode, | |
1205 | .afu_reset = native_afu_reset, | |
1206 | .afu_cr_read8 = native_afu_cr_read8, | |
1207 | .afu_cr_read16 = native_afu_cr_read16, | |
1208 | .afu_cr_read32 = native_afu_cr_read32, | |
1209 | .afu_cr_read64 = native_afu_cr_read64, | |
d601ea91 FB |
1210 | .afu_cr_write8 = native_afu_cr_write8, |
1211 | .afu_cr_write16 = native_afu_cr_write16, | |
1212 | .afu_cr_write32 = native_afu_cr_write32, | |
1213 | .read_adapter_vpd = cxl_pci_read_adapter_vpd, | |
5be587b1 | 1214 | }; |