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Commit | Line | Data |
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f204e0b8 IM |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/spinlock.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/sched.h> | |
14 | #include <linux/mutex.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/uaccess.h> | |
2bc79ffc | 17 | #include <linux/delay.h> |
f204e0b8 | 18 | #include <asm/synch.h> |
ec249dd8 | 19 | #include <misc/cxl-base.h> |
f204e0b8 IM |
20 | |
21 | #include "cxl.h" | |
9bcf28cd | 22 | #include "trace.h" |
f204e0b8 | 23 | |
5e7823c9 | 24 | static int afu_control(struct cxl_afu *afu, u64 command, u64 clear, |
f204e0b8 IM |
25 | u64 result, u64 mask, bool enabled) |
26 | { | |
5e7823c9 | 27 | u64 AFU_Cntl; |
f204e0b8 | 28 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
9bcf28cd | 29 | int rc = 0; |
f204e0b8 IM |
30 | |
31 | spin_lock(&afu->afu_cntl_lock); | |
32 | pr_devel("AFU command starting: %llx\n", command); | |
33 | ||
9bcf28cd IM |
34 | trace_cxl_afu_ctrl(afu, command); |
35 | ||
5e7823c9 IM |
36 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); |
37 | cxl_p2n_write(afu, CXL_AFU_Cntl_An, (AFU_Cntl & ~clear) | command); | |
f204e0b8 IM |
38 | |
39 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
40 | while ((AFU_Cntl & mask) != result) { | |
41 | if (time_after_eq(jiffies, timeout)) { | |
42 | dev_warn(&afu->dev, "WARNING: AFU control timed out!\n"); | |
9bcf28cd IM |
43 | rc = -EBUSY; |
44 | goto out; | |
f204e0b8 | 45 | } |
0b3f9c75 | 46 | |
0d400f77 | 47 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
48 | afu->enabled = enabled; |
49 | rc = -EIO; | |
50 | goto out; | |
51 | } | |
52 | ||
de369538 | 53 | pr_devel_ratelimited("AFU control... (0x%016llx)\n", |
f204e0b8 IM |
54 | AFU_Cntl | command); |
55 | cpu_relax(); | |
56 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
57 | }; | |
58 | pr_devel("AFU command complete: %llx\n", command); | |
59 | afu->enabled = enabled; | |
9bcf28cd IM |
60 | out: |
61 | trace_cxl_afu_ctrl_done(afu, command, rc); | |
f204e0b8 IM |
62 | spin_unlock(&afu->afu_cntl_lock); |
63 | ||
9bcf28cd | 64 | return rc; |
f204e0b8 IM |
65 | } |
66 | ||
67 | static int afu_enable(struct cxl_afu *afu) | |
68 | { | |
69 | pr_devel("AFU enable request\n"); | |
70 | ||
5e7823c9 | 71 | return afu_control(afu, CXL_AFU_Cntl_An_E, 0, |
f204e0b8 IM |
72 | CXL_AFU_Cntl_An_ES_Enabled, |
73 | CXL_AFU_Cntl_An_ES_MASK, true); | |
74 | } | |
75 | ||
76 | int cxl_afu_disable(struct cxl_afu *afu) | |
77 | { | |
78 | pr_devel("AFU disable request\n"); | |
79 | ||
5e7823c9 IM |
80 | return afu_control(afu, 0, CXL_AFU_Cntl_An_E, |
81 | CXL_AFU_Cntl_An_ES_Disabled, | |
f204e0b8 IM |
82 | CXL_AFU_Cntl_An_ES_MASK, false); |
83 | } | |
84 | ||
85 | /* This will disable as well as reset */ | |
2b04cf31 | 86 | static int native_afu_reset(struct cxl_afu *afu) |
f204e0b8 IM |
87 | { |
88 | pr_devel("AFU reset request\n"); | |
89 | ||
5e7823c9 | 90 | return afu_control(afu, CXL_AFU_Cntl_An_RA, 0, |
f204e0b8 IM |
91 | CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled, |
92 | CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK, | |
93 | false); | |
94 | } | |
95 | ||
2b04cf31 | 96 | static int native_afu_check_and_enable(struct cxl_afu *afu) |
f204e0b8 | 97 | { |
0d400f77 | 98 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
99 | WARN(1, "Refusing to enable afu while link down!\n"); |
100 | return -EIO; | |
101 | } | |
f204e0b8 IM |
102 | if (afu->enabled) |
103 | return 0; | |
104 | return afu_enable(afu); | |
105 | } | |
106 | ||
107 | int cxl_psl_purge(struct cxl_afu *afu) | |
108 | { | |
109 | u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
110 | u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
111 | u64 dsisr, dar; | |
112 | u64 start, end; | |
113 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
9bcf28cd IM |
114 | int rc = 0; |
115 | ||
116 | trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc); | |
f204e0b8 IM |
117 | |
118 | pr_devel("PSL purge request\n"); | |
119 | ||
0d400f77 | 120 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
121 | dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n"); |
122 | rc = -EIO; | |
123 | goto out; | |
124 | } | |
125 | ||
f204e0b8 IM |
126 | if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { |
127 | WARN(1, "psl_purge request while AFU not disabled!\n"); | |
128 | cxl_afu_disable(afu); | |
129 | } | |
130 | ||
131 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, | |
132 | PSL_CNTL | CXL_PSL_SCNTL_An_Pc); | |
133 | start = local_clock(); | |
134 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
135 | while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK) | |
136 | == CXL_PSL_SCNTL_An_Ps_Pending) { | |
137 | if (time_after_eq(jiffies, timeout)) { | |
138 | dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n"); | |
9bcf28cd IM |
139 | rc = -EBUSY; |
140 | goto out; | |
f204e0b8 | 141 | } |
0d400f77 | 142 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
143 | rc = -EIO; |
144 | goto out; | |
145 | } | |
146 | ||
f204e0b8 | 147 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
de369538 | 148 | pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr); |
f204e0b8 IM |
149 | if (dsisr & CXL_PSL_DSISR_TRANS) { |
150 | dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); | |
de369538 | 151 | dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar); |
f204e0b8 IM |
152 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); |
153 | } else if (dsisr) { | |
de369538 | 154 | dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr); |
f204e0b8 IM |
155 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); |
156 | } else { | |
157 | cpu_relax(); | |
158 | } | |
159 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
160 | }; | |
161 | end = local_clock(); | |
162 | pr_devel("PSL purged in %lld ns\n", end - start); | |
163 | ||
164 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, | |
165 | PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc); | |
9bcf28cd IM |
166 | out: |
167 | trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc); | |
168 | return rc; | |
f204e0b8 IM |
169 | } |
170 | ||
171 | static int spa_max_procs(int spa_size) | |
172 | { | |
173 | /* | |
174 | * From the CAIA: | |
175 | * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255 | |
176 | * Most of that junk is really just an overly-complicated way of saying | |
177 | * the last 256 bytes are __aligned(128), so it's really: | |
178 | * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255 | |
179 | * and | |
180 | * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1 | |
181 | * so | |
182 | * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256 | |
183 | * Ignore the alignment (which is safe in this case as long as we are | |
184 | * careful with our rounding) and solve for n: | |
185 | */ | |
186 | return ((spa_size / 8) - 96) / 17; | |
187 | } | |
188 | ||
05155772 | 189 | int cxl_alloc_spa(struct cxl_afu *afu) |
f204e0b8 | 190 | { |
895a7980 IM |
191 | unsigned spa_size; |
192 | ||
f204e0b8 | 193 | /* Work out how many pages to allocate */ |
2224b671 | 194 | afu->native->spa_order = -1; |
f204e0b8 | 195 | do { |
cbffa3a5 | 196 | afu->native->spa_order++; |
895a7980 IM |
197 | spa_size = (1 << afu->native->spa_order) * PAGE_SIZE; |
198 | ||
199 | if (spa_size > 0x100000) { | |
200 | dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n", | |
201 | afu->native->spa_max_procs, afu->native->spa_size); | |
202 | afu->num_procs = afu->native->spa_max_procs; | |
203 | break; | |
204 | } | |
205 | ||
206 | afu->native->spa_size = spa_size; | |
cbffa3a5 CL |
207 | afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size); |
208 | } while (afu->native->spa_max_procs < afu->num_procs); | |
f204e0b8 | 209 | |
cbffa3a5 CL |
210 | if (!(afu->native->spa = (struct cxl_process_element *) |
211 | __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) { | |
f204e0b8 IM |
212 | pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n"); |
213 | return -ENOMEM; | |
214 | } | |
215 | pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n", | |
cbffa3a5 | 216 | 1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs); |
f204e0b8 | 217 | |
05155772 DA |
218 | return 0; |
219 | } | |
220 | ||
221 | static void attach_spa(struct cxl_afu *afu) | |
222 | { | |
223 | u64 spap; | |
224 | ||
cbffa3a5 CL |
225 | afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa + |
226 | ((afu->native->spa_max_procs + 3) * 128)); | |
f204e0b8 | 227 | |
cbffa3a5 CL |
228 | spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr; |
229 | spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size; | |
f204e0b8 | 230 | spap |= CXL_PSL_SPAP_V; |
cbffa3a5 CL |
231 | pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", |
232 | afu->native->spa, afu->native->spa_max_procs, | |
233 | afu->native->sw_command_status, spap); | |
f204e0b8 | 234 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap); |
f204e0b8 IM |
235 | } |
236 | ||
05155772 | 237 | static inline void detach_spa(struct cxl_afu *afu) |
f204e0b8 | 238 | { |
db7933f3 | 239 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); |
05155772 DA |
240 | } |
241 | ||
242 | void cxl_release_spa(struct cxl_afu *afu) | |
243 | { | |
cbffa3a5 CL |
244 | if (afu->native->spa) { |
245 | free_pages((unsigned long) afu->native->spa, | |
246 | afu->native->spa_order); | |
247 | afu->native->spa = NULL; | |
05155772 | 248 | } |
f204e0b8 IM |
249 | } |
250 | ||
251 | int cxl_tlb_slb_invalidate(struct cxl *adapter) | |
252 | { | |
253 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
254 | ||
255 | pr_devel("CXL adapter wide TLBIA & SLBIA\n"); | |
256 | ||
257 | cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A); | |
258 | ||
259 | cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL); | |
260 | while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) { | |
261 | if (time_after_eq(jiffies, timeout)) { | |
262 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n"); | |
263 | return -EBUSY; | |
264 | } | |
0d400f77 | 265 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 266 | return -EIO; |
f204e0b8 IM |
267 | cpu_relax(); |
268 | } | |
269 | ||
270 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL); | |
271 | while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) { | |
272 | if (time_after_eq(jiffies, timeout)) { | |
273 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n"); | |
274 | return -EBUSY; | |
275 | } | |
0d400f77 | 276 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 277 | return -EIO; |
f204e0b8 IM |
278 | cpu_relax(); |
279 | } | |
280 | return 0; | |
281 | } | |
282 | ||
f204e0b8 IM |
283 | static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1) |
284 | { | |
285 | int rc; | |
286 | ||
287 | /* 1. Disable SSTP by writing 0 to SSTP1[V] */ | |
288 | cxl_p2n_write(afu, CXL_SSTP1_An, 0); | |
289 | ||
290 | /* 2. Invalidate all SLB entries */ | |
291 | if ((rc = cxl_afu_slbia(afu))) | |
292 | return rc; | |
293 | ||
294 | /* 3. Set SSTP0_An */ | |
295 | cxl_p2n_write(afu, CXL_SSTP0_An, sstp0); | |
296 | ||
297 | /* 4. Set SSTP1_An */ | |
298 | cxl_p2n_write(afu, CXL_SSTP1_An, sstp1); | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | /* Using per slice version may improve performance here. (ie. SLBIA_An) */ | |
304 | static void slb_invalid(struct cxl_context *ctx) | |
305 | { | |
306 | struct cxl *adapter = ctx->afu->adapter; | |
307 | u64 slbia; | |
308 | ||
cbffa3a5 | 309 | WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex)); |
f204e0b8 IM |
310 | |
311 | cxl_p1_write(adapter, CXL_PSL_LBISEL, | |
312 | ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) | | |
313 | be32_to_cpu(ctx->elem->lpid)); | |
314 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID); | |
315 | ||
316 | while (1) { | |
0d400f77 | 317 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 318 | break; |
f204e0b8 IM |
319 | slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA); |
320 | if (!(slbia & CXL_TLB_SLB_P)) | |
321 | break; | |
322 | cpu_relax(); | |
323 | } | |
324 | } | |
325 | ||
326 | static int do_process_element_cmd(struct cxl_context *ctx, | |
327 | u64 cmd, u64 pe_state) | |
328 | { | |
329 | u64 state; | |
a98e6e9f | 330 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
9bcf28cd IM |
331 | int rc = 0; |
332 | ||
333 | trace_cxl_llcmd(ctx, cmd); | |
f204e0b8 IM |
334 | |
335 | WARN_ON(!ctx->afu->enabled); | |
336 | ||
337 | ctx->elem->software_state = cpu_to_be32(pe_state); | |
338 | smp_wmb(); | |
cbffa3a5 | 339 | *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe); |
f204e0b8 IM |
340 | smp_mb(); |
341 | cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe); | |
342 | while (1) { | |
a98e6e9f IM |
343 | if (time_after_eq(jiffies, timeout)) { |
344 | dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n"); | |
9bcf28cd IM |
345 | rc = -EBUSY; |
346 | goto out; | |
a98e6e9f | 347 | } |
0d400f77 | 348 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
0b3f9c75 DA |
349 | dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n"); |
350 | rc = -EIO; | |
351 | goto out; | |
352 | } | |
cbffa3a5 | 353 | state = be64_to_cpup(ctx->afu->native->sw_command_status); |
f204e0b8 IM |
354 | if (state == ~0ULL) { |
355 | pr_err("cxl: Error adding process element to AFU\n"); | |
9bcf28cd IM |
356 | rc = -1; |
357 | goto out; | |
f204e0b8 IM |
358 | } |
359 | if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) == | |
360 | (cmd | (cmd >> 16) | ctx->pe)) | |
361 | break; | |
362 | /* | |
363 | * The command won't finish in the PSL if there are | |
364 | * outstanding DSIs. Hence we need to yield here in | |
365 | * case there are outstanding DSIs that we need to | |
366 | * service. Tuning possiblity: we could wait for a | |
367 | * while before sched | |
368 | */ | |
369 | schedule(); | |
370 | ||
371 | } | |
9bcf28cd IM |
372 | out: |
373 | trace_cxl_llcmd_done(ctx, cmd, rc); | |
374 | return rc; | |
f204e0b8 IM |
375 | } |
376 | ||
377 | static int add_process_element(struct cxl_context *ctx) | |
378 | { | |
379 | int rc = 0; | |
380 | ||
cbffa3a5 | 381 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
382 | pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe); |
383 | if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V))) | |
384 | ctx->pe_inserted = true; | |
385 | pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 386 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
387 | return rc; |
388 | } | |
389 | ||
390 | static int terminate_process_element(struct cxl_context *ctx) | |
391 | { | |
392 | int rc = 0; | |
393 | ||
394 | /* fast path terminate if it's already invalid */ | |
395 | if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V))) | |
396 | return rc; | |
397 | ||
cbffa3a5 | 398 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 | 399 | pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe); |
0b3f9c75 DA |
400 | /* We could be asked to terminate when the hw is down. That |
401 | * should always succeed: it's not running if the hw has gone | |
402 | * away and is being reset. | |
403 | */ | |
0d400f77 | 404 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
0b3f9c75 DA |
405 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE, |
406 | CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T); | |
f204e0b8 IM |
407 | ctx->elem->software_state = 0; /* Remove Valid bit */ |
408 | pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 409 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
410 | return rc; |
411 | } | |
412 | ||
413 | static int remove_process_element(struct cxl_context *ctx) | |
414 | { | |
415 | int rc = 0; | |
416 | ||
cbffa3a5 | 417 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 | 418 | pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe); |
0b3f9c75 DA |
419 | |
420 | /* We could be asked to remove when the hw is down. Again, if | |
421 | * the hw is down, the PE is gone, so we succeed. | |
422 | */ | |
0d400f77 | 423 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
0b3f9c75 DA |
424 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0); |
425 | ||
426 | if (!rc) | |
f204e0b8 IM |
427 | ctx->pe_inserted = false; |
428 | slb_invalid(ctx); | |
429 | pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 430 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
431 | |
432 | return rc; | |
433 | } | |
434 | ||
1a1a94b8 | 435 | void cxl_assign_psn_space(struct cxl_context *ctx) |
f204e0b8 IM |
436 | { |
437 | if (!ctx->afu->pp_size || ctx->master) { | |
438 | ctx->psn_phys = ctx->afu->psn_phys; | |
439 | ctx->psn_size = ctx->afu->adapter->ps_size; | |
440 | } else { | |
441 | ctx->psn_phys = ctx->afu->psn_phys + | |
cbffa3a5 | 442 | (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe); |
f204e0b8 IM |
443 | ctx->psn_size = ctx->afu->pp_size; |
444 | } | |
445 | } | |
446 | ||
447 | static int activate_afu_directed(struct cxl_afu *afu) | |
448 | { | |
449 | int rc; | |
450 | ||
451 | dev_info(&afu->dev, "Activating AFU directed mode\n"); | |
452 | ||
4108efb0 | 453 | afu->num_procs = afu->max_procs_virtualised; |
cbffa3a5 | 454 | if (afu->native->spa == NULL) { |
05155772 DA |
455 | if (cxl_alloc_spa(afu)) |
456 | return -ENOMEM; | |
457 | } | |
458 | attach_spa(afu); | |
f204e0b8 IM |
459 | |
460 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU); | |
461 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); | |
462 | cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L); | |
463 | ||
464 | afu->current_mode = CXL_MODE_DIRECTED; | |
f204e0b8 IM |
465 | |
466 | if ((rc = cxl_chardev_m_afu_add(afu))) | |
467 | return rc; | |
468 | ||
469 | if ((rc = cxl_sysfs_afu_m_add(afu))) | |
470 | goto err; | |
471 | ||
472 | if ((rc = cxl_chardev_s_afu_add(afu))) | |
473 | goto err1; | |
474 | ||
475 | return 0; | |
476 | err1: | |
477 | cxl_sysfs_afu_m_remove(afu); | |
478 | err: | |
479 | cxl_chardev_afu_remove(afu); | |
480 | return rc; | |
481 | } | |
482 | ||
483 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
484 | #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE) | |
485 | #else | |
486 | #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE)) | |
487 | #endif | |
488 | ||
2f663527 MN |
489 | static u64 calculate_sr(struct cxl_context *ctx) |
490 | { | |
491 | u64 sr = 0; | |
492 | ||
e606e035 | 493 | set_endian(sr); |
2f663527 MN |
494 | if (ctx->master) |
495 | sr |= CXL_PSL_SR_An_MP; | |
496 | if (mfspr(SPRN_LPCR) & LPCR_TC) | |
497 | sr |= CXL_PSL_SR_An_TC; | |
498 | if (ctx->kernel) { | |
7a0d85d3 IM |
499 | if (!ctx->real_mode) |
500 | sr |= CXL_PSL_SR_An_R; | |
501 | sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV; | |
2f663527 MN |
502 | } else { |
503 | sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; | |
2f663527 MN |
504 | sr &= ~(CXL_PSL_SR_An_HV); |
505 | if (!test_tsk_thread_flag(current, TIF_32BIT)) | |
506 | sr |= CXL_PSL_SR_An_SF; | |
507 | } | |
508 | return sr; | |
509 | } | |
510 | ||
292841b0 IM |
511 | static void update_ivtes_directed(struct cxl_context *ctx) |
512 | { | |
513 | bool need_update = (ctx->status == STARTED); | |
514 | int r; | |
515 | ||
516 | if (need_update) { | |
517 | WARN_ON(terminate_process_element(ctx)); | |
518 | WARN_ON(remove_process_element(ctx)); | |
519 | } | |
520 | ||
521 | for (r = 0; r < CXL_IRQ_RANGES; r++) { | |
522 | ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]); | |
523 | ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]); | |
524 | } | |
525 | ||
526 | /* | |
527 | * Theoretically we could use the update llcmd, instead of a | |
528 | * terminate/remove/add (or if an atomic update was required we could | |
529 | * do a suspend/update/resume), however it seems there might be issues | |
530 | * with the update llcmd on some cards (including those using an XSL on | |
531 | * an ASIC) so for now it's safest to go with the commands that are | |
532 | * known to work. In the future if we come across a situation where the | |
533 | * card may be performing transactions using the same PE while we are | |
534 | * doing this update we might need to revisit this. | |
535 | */ | |
536 | if (need_update) | |
537 | WARN_ON(add_process_element(ctx)); | |
538 | } | |
539 | ||
f204e0b8 IM |
540 | static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr) |
541 | { | |
2f663527 | 542 | u32 pid; |
292841b0 | 543 | int result; |
f204e0b8 | 544 | |
1a1a94b8 | 545 | cxl_assign_psn_space(ctx); |
f204e0b8 IM |
546 | |
547 | ctx->elem->ctxtime = 0; /* disable */ | |
548 | ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID)); | |
549 | ctx->elem->haurp = 0; /* disable */ | |
550 | ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1)); | |
551 | ||
2f663527 MN |
552 | pid = current->pid; |
553 | if (ctx->kernel) | |
554 | pid = 0; | |
f204e0b8 | 555 | ctx->elem->common.tid = 0; |
2f663527 MN |
556 | ctx->elem->common.pid = cpu_to_be32(pid); |
557 | ||
558 | ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); | |
f204e0b8 IM |
559 | |
560 | ctx->elem->common.csrp = 0; /* disable */ | |
561 | ctx->elem->common.aurp0 = 0; /* disable */ | |
562 | ctx->elem->common.aurp1 = 0; /* disable */ | |
563 | ||
564 | cxl_prefault(ctx, wed); | |
565 | ||
566 | ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0); | |
567 | ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1); | |
568 | ||
3c206fa7 IM |
569 | /* |
570 | * Ensure we have the multiplexed PSL interrupt set up to take faults | |
571 | * for kernel contexts that may not have allocated any AFU IRQs at all: | |
572 | */ | |
573 | if (ctx->irqs.range[0] == 0) { | |
574 | ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq; | |
575 | ctx->irqs.range[0] = 1; | |
576 | } | |
577 | ||
292841b0 | 578 | update_ivtes_directed(ctx); |
f204e0b8 IM |
579 | |
580 | ctx->elem->common.amr = cpu_to_be64(amr); | |
581 | ctx->elem->common.wed = cpu_to_be64(wed); | |
582 | ||
583 | /* first guy needs to enable */ | |
5be587b1 | 584 | if ((result = cxl_ops->afu_check_and_enable(ctx->afu))) |
f204e0b8 IM |
585 | return result; |
586 | ||
368857c1 | 587 | return add_process_element(ctx); |
f204e0b8 IM |
588 | } |
589 | ||
590 | static int deactivate_afu_directed(struct cxl_afu *afu) | |
591 | { | |
592 | dev_info(&afu->dev, "Deactivating AFU directed mode\n"); | |
593 | ||
594 | afu->current_mode = 0; | |
595 | afu->num_procs = 0; | |
596 | ||
597 | cxl_sysfs_afu_m_remove(afu); | |
598 | cxl_chardev_afu_remove(afu); | |
599 | ||
5e7823c9 IM |
600 | /* |
601 | * The CAIA section 2.2.1 indicates that the procedure for starting and | |
602 | * stopping an AFU in AFU directed mode is AFU specific, which is not | |
603 | * ideal since this code is generic and with one exception has no | |
604 | * knowledge of the AFU. This is in contrast to the procedure for | |
605 | * disabling a dedicated process AFU, which is documented to just | |
606 | * require a reset. The architecture does indicate that both an AFU | |
607 | * reset and an AFU disable should result in the AFU being disabled and | |
608 | * we do both followed by a PSL purge for safety. | |
609 | * | |
610 | * Notably we used to have some issues with the disable sequence on PSL | |
611 | * cards, which is why we ended up using this heavy weight procedure in | |
612 | * the first place, however a bug was discovered that had rendered the | |
613 | * disable operation ineffective, so it is conceivable that was the | |
614 | * sole explanation for those difficulties. Careful regression testing | |
615 | * is recommended if anyone attempts to remove or reorder these | |
616 | * operations. | |
617 | * | |
618 | * The XSL on the Mellanox CX4 behaves a little differently from the | |
619 | * PSL based cards and will time out an AFU reset if the AFU is still | |
620 | * enabled. That card is special in that we do have a means to identify | |
621 | * it from this code, so in that case we skip the reset and just use a | |
622 | * disable/purge to avoid the timeout and corresponding noise in the | |
623 | * kernel log. | |
624 | */ | |
625 | if (afu->adapter->native->sl_ops->needs_reset_before_disable) | |
626 | cxl_ops->afu_reset(afu); | |
f204e0b8 IM |
627 | cxl_afu_disable(afu); |
628 | cxl_psl_purge(afu); | |
629 | ||
f204e0b8 IM |
630 | return 0; |
631 | } | |
632 | ||
633 | static int activate_dedicated_process(struct cxl_afu *afu) | |
634 | { | |
635 | dev_info(&afu->dev, "Activating dedicated process mode\n"); | |
636 | ||
637 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process); | |
638 | ||
639 | cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */ | |
640 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */ | |
641 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); | |
642 | cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID)); | |
643 | cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */ | |
644 | cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1)); | |
645 | ||
646 | cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */ | |
647 | cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */ | |
648 | cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */ | |
649 | ||
650 | afu->current_mode = CXL_MODE_DEDICATED; | |
651 | afu->num_procs = 1; | |
652 | ||
653 | return cxl_chardev_d_afu_add(afu); | |
654 | } | |
655 | ||
292841b0 IM |
656 | static void update_ivtes_dedicated(struct cxl_context *ctx) |
657 | { | |
658 | struct cxl_afu *afu = ctx->afu; | |
659 | ||
660 | cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, | |
661 | (((u64)ctx->irqs.offset[0] & 0xffff) << 48) | | |
662 | (((u64)ctx->irqs.offset[1] & 0xffff) << 32) | | |
663 | (((u64)ctx->irqs.offset[2] & 0xffff) << 16) | | |
664 | ((u64)ctx->irqs.offset[3] & 0xffff)); | |
665 | cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64) | |
666 | (((u64)ctx->irqs.range[0] & 0xffff) << 48) | | |
667 | (((u64)ctx->irqs.range[1] & 0xffff) << 32) | | |
668 | (((u64)ctx->irqs.range[2] & 0xffff) << 16) | | |
669 | ((u64)ctx->irqs.range[3] & 0xffff)); | |
670 | } | |
671 | ||
f204e0b8 IM |
672 | static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr) |
673 | { | |
674 | struct cxl_afu *afu = ctx->afu; | |
2f663527 | 675 | u64 pid; |
f204e0b8 IM |
676 | int rc; |
677 | ||
2f663527 MN |
678 | pid = (u64)current->pid << 32; |
679 | if (ctx->kernel) | |
680 | pid = 0; | |
681 | cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid); | |
682 | ||
683 | cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx)); | |
f204e0b8 IM |
684 | |
685 | if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1))) | |
686 | return rc; | |
687 | ||
688 | cxl_prefault(ctx, wed); | |
689 | ||
292841b0 | 690 | update_ivtes_dedicated(ctx); |
f204e0b8 IM |
691 | |
692 | cxl_p2n_write(afu, CXL_PSL_AMR_An, amr); | |
693 | ||
694 | /* master only context for dedicated */ | |
1a1a94b8 | 695 | cxl_assign_psn_space(ctx); |
f204e0b8 | 696 | |
5be587b1 | 697 | if ((rc = cxl_ops->afu_reset(afu))) |
f204e0b8 IM |
698 | return rc; |
699 | ||
700 | cxl_p2n_write(afu, CXL_PSL_WED_An, wed); | |
701 | ||
702 | return afu_enable(afu); | |
703 | } | |
704 | ||
705 | static int deactivate_dedicated_process(struct cxl_afu *afu) | |
706 | { | |
707 | dev_info(&afu->dev, "Deactivating dedicated process mode\n"); | |
708 | ||
709 | afu->current_mode = 0; | |
710 | afu->num_procs = 0; | |
711 | ||
712 | cxl_chardev_afu_remove(afu); | |
713 | ||
714 | return 0; | |
715 | } | |
716 | ||
2b04cf31 | 717 | static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode) |
f204e0b8 IM |
718 | { |
719 | if (mode == CXL_MODE_DIRECTED) | |
720 | return deactivate_afu_directed(afu); | |
721 | if (mode == CXL_MODE_DEDICATED) | |
722 | return deactivate_dedicated_process(afu); | |
723 | return 0; | |
724 | } | |
725 | ||
2b04cf31 | 726 | static int native_afu_activate_mode(struct cxl_afu *afu, int mode) |
f204e0b8 IM |
727 | { |
728 | if (!mode) | |
729 | return 0; | |
730 | if (!(mode & afu->modes_supported)) | |
731 | return -EINVAL; | |
732 | ||
0d400f77 | 733 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
734 | WARN(1, "Device link is down, refusing to activate!\n"); |
735 | return -EIO; | |
736 | } | |
737 | ||
f204e0b8 IM |
738 | if (mode == CXL_MODE_DIRECTED) |
739 | return activate_afu_directed(afu); | |
740 | if (mode == CXL_MODE_DEDICATED) | |
741 | return activate_dedicated_process(afu); | |
742 | ||
743 | return -EINVAL; | |
744 | } | |
745 | ||
2b04cf31 FB |
746 | static int native_attach_process(struct cxl_context *ctx, bool kernel, |
747 | u64 wed, u64 amr) | |
f204e0b8 | 748 | { |
0d400f77 | 749 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
0b3f9c75 DA |
750 | WARN(1, "Device link is down, refusing to attach process!\n"); |
751 | return -EIO; | |
752 | } | |
753 | ||
f204e0b8 IM |
754 | ctx->kernel = kernel; |
755 | if (ctx->afu->current_mode == CXL_MODE_DIRECTED) | |
756 | return attach_afu_directed(ctx, wed, amr); | |
757 | ||
758 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) | |
759 | return attach_dedicated(ctx, wed, amr); | |
760 | ||
761 | return -EINVAL; | |
762 | } | |
763 | ||
764 | static inline int detach_process_native_dedicated(struct cxl_context *ctx) | |
765 | { | |
5e7823c9 IM |
766 | /* |
767 | * The CAIA section 2.1.1 indicates that we need to do an AFU reset to | |
768 | * stop the AFU in dedicated mode (we therefore do not make that | |
769 | * optional like we do in the afu directed path). It does not indicate | |
770 | * that we need to do an explicit disable (which should occur | |
771 | * implicitly as part of the reset) or purge, but we do these as well | |
772 | * to be on the safe side. | |
773 | * | |
774 | * Notably we used to have some issues with the disable sequence | |
775 | * (before the sequence was spelled out in the architecture) which is | |
776 | * why we were so heavy weight in the first place, however a bug was | |
777 | * discovered that had rendered the disable operation ineffective, so | |
778 | * it is conceivable that was the sole explanation for those | |
779 | * difficulties. Point is, we should be careful and do some regression | |
780 | * testing if we ever attempt to remove any part of this procedure. | |
781 | */ | |
5be587b1 | 782 | cxl_ops->afu_reset(ctx->afu); |
f204e0b8 IM |
783 | cxl_afu_disable(ctx->afu); |
784 | cxl_psl_purge(ctx->afu); | |
785 | return 0; | |
786 | } | |
787 | ||
292841b0 IM |
788 | static void native_update_ivtes(struct cxl_context *ctx) |
789 | { | |
790 | if (ctx->afu->current_mode == CXL_MODE_DIRECTED) | |
791 | return update_ivtes_directed(ctx); | |
792 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) | |
793 | return update_ivtes_dedicated(ctx); | |
794 | WARN(1, "native_update_ivtes: Bad mode\n"); | |
795 | } | |
796 | ||
f204e0b8 IM |
797 | static inline int detach_process_native_afu_directed(struct cxl_context *ctx) |
798 | { | |
799 | if (!ctx->pe_inserted) | |
800 | return 0; | |
801 | if (terminate_process_element(ctx)) | |
802 | return -1; | |
803 | if (remove_process_element(ctx)) | |
804 | return -1; | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
2b04cf31 | 809 | static int native_detach_process(struct cxl_context *ctx) |
f204e0b8 | 810 | { |
9bcf28cd IM |
811 | trace_cxl_detach(ctx); |
812 | ||
f204e0b8 IM |
813 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) |
814 | return detach_process_native_dedicated(ctx); | |
815 | ||
816 | return detach_process_native_afu_directed(ctx); | |
817 | } | |
818 | ||
2b04cf31 | 819 | static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info) |
f204e0b8 IM |
820 | { |
821 | u64 pidtid; | |
822 | ||
0b3f9c75 DA |
823 | /* If the adapter has gone away, we can't get any meaningful |
824 | * information. | |
825 | */ | |
0d400f77 | 826 | if (!cxl_ops->link_ok(afu->adapter, afu)) |
0b3f9c75 DA |
827 | return -EIO; |
828 | ||
bc78b05b IM |
829 | info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
830 | info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); | |
831 | info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An); | |
832 | pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An); | |
f204e0b8 IM |
833 | info->pid = pidtid >> 32; |
834 | info->tid = pidtid & 0xffffffff; | |
bc78b05b IM |
835 | info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An); |
836 | info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
444c4ba4 | 837 | info->proc_handle = 0; |
f204e0b8 IM |
838 | |
839 | return 0; | |
840 | } | |
841 | ||
6d382616 | 842 | void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx) |
d56d301b FB |
843 | { |
844 | u64 fir1, fir2, fir_slice, serr, afu_debug; | |
845 | ||
846 | fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1); | |
847 | fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2); | |
848 | fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An); | |
d56d301b FB |
849 | afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An); |
850 | ||
d56d301b FB |
851 | dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1); |
852 | dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2); | |
6d382616 FB |
853 | if (ctx->afu->adapter->native->sl_ops->register_serr_irq) { |
854 | serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An); | |
855 | dev_crit(&ctx->afu->dev, "PSL_SERR_An: 0x%016llx\n", serr); | |
856 | } | |
d56d301b FB |
857 | dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); |
858 | dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); | |
6d382616 FB |
859 | } |
860 | ||
861 | static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx, | |
862 | u64 dsisr, u64 errstat) | |
863 | { | |
864 | ||
865 | dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat); | |
d56d301b | 866 | |
6d382616 FB |
867 | if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers) |
868 | ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx); | |
869 | ||
870 | if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) { | |
871 | dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n"); | |
872 | ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter); | |
873 | } | |
d56d301b | 874 | |
5be587b1 | 875 | return cxl_ops->ack_irq(ctx, 0, errstat); |
d56d301b FB |
876 | } |
877 | ||
878 | static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info) | |
879 | { | |
880 | if (irq_info->dsisr & CXL_PSL_DSISR_TRANS) | |
881 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); | |
882 | else | |
883 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); | |
884 | ||
885 | return IRQ_HANDLED; | |
886 | } | |
887 | ||
2b04cf31 | 888 | static irqreturn_t native_irq_multiplexed(int irq, void *data) |
d56d301b FB |
889 | { |
890 | struct cxl_afu *afu = data; | |
891 | struct cxl_context *ctx; | |
892 | struct cxl_irq_info irq_info; | |
893 | int ph = cxl_p2n_read(afu, CXL_PSL_PEHandle_An) & 0xffff; | |
894 | int ret; | |
895 | ||
2b04cf31 | 896 | if ((ret = native_get_irq_info(afu, &irq_info))) { |
d56d301b FB |
897 | WARN(1, "Unable to get CXL IRQ Info: %i\n", ret); |
898 | return fail_psl_irq(afu, &irq_info); | |
899 | } | |
900 | ||
901 | rcu_read_lock(); | |
902 | ctx = idr_find(&afu->contexts_idr, ph); | |
903 | if (ctx) { | |
904 | ret = cxl_irq(irq, ctx, &irq_info); | |
905 | rcu_read_unlock(); | |
906 | return ret; | |
907 | } | |
908 | rcu_read_unlock(); | |
909 | ||
910 | WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR" | |
911 | " %016llx\n(Possible AFU HW issue - was a term/remove acked" | |
912 | " with outstanding transactions?)\n", ph, irq_info.dsisr, | |
913 | irq_info.dar); | |
914 | return fail_psl_irq(afu, &irq_info); | |
915 | } | |
916 | ||
2bc79ffc MN |
917 | void native_irq_wait(struct cxl_context *ctx) |
918 | { | |
919 | u64 dsisr; | |
920 | int timeout = 1000; | |
921 | int ph; | |
922 | ||
923 | /* | |
924 | * Wait until no further interrupts are presented by the PSL | |
925 | * for this context. | |
926 | */ | |
927 | while (timeout--) { | |
928 | ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff; | |
929 | if (ph != ctx->pe) | |
930 | return; | |
931 | dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An); | |
932 | if ((dsisr & CXL_PSL_DSISR_PENDING) == 0) | |
933 | return; | |
934 | /* | |
935 | * We are waiting for the workqueue to process our | |
936 | * irq, so need to let that run here. | |
937 | */ | |
938 | msleep(1); | |
939 | } | |
940 | ||
941 | dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i" | |
942 | " DSISR %016llx!\n", ph, dsisr); | |
943 | return; | |
944 | } | |
945 | ||
2b04cf31 | 946 | static irqreturn_t native_slice_irq_err(int irq, void *data) |
d56d301b FB |
947 | { |
948 | struct cxl_afu *afu = data; | |
949 | u64 fir_slice, errstat, serr, afu_debug; | |
950 | ||
6d382616 FB |
951 | /* |
952 | * slice err interrupt is only used with full PSL (no XSL) | |
953 | */ | |
d56d301b FB |
954 | WARN(irq, "CXL SLICE ERROR interrupt %i\n", irq); |
955 | ||
956 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
957 | fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An); | |
958 | errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
959 | afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An); | |
960 | dev_crit(&afu->dev, "PSL_SERR_An: 0x%016llx\n", serr); | |
961 | dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); | |
962 | dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat); | |
963 | dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); | |
964 | ||
965 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); | |
966 | ||
967 | return IRQ_HANDLED; | |
968 | } | |
969 | ||
6d382616 FB |
970 | void cxl_native_err_irq_dump_regs(struct cxl *adapter) |
971 | { | |
972 | u64 fir1, fir2; | |
973 | ||
974 | fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1); | |
975 | fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2); | |
976 | ||
977 | dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2); | |
978 | } | |
979 | ||
2b04cf31 | 980 | static irqreturn_t native_irq_err(int irq, void *data) |
d56d301b FB |
981 | { |
982 | struct cxl *adapter = data; | |
6d382616 | 983 | u64 err_ivte; |
d56d301b FB |
984 | |
985 | WARN(1, "CXL ERROR interrupt %i\n", irq); | |
986 | ||
987 | err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE); | |
988 | dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte); | |
989 | ||
6d382616 FB |
990 | if (adapter->native->sl_ops->debugfs_stop_trace) { |
991 | dev_crit(&adapter->dev, "STOPPING CXL TRACE\n"); | |
992 | adapter->native->sl_ops->debugfs_stop_trace(adapter); | |
993 | } | |
d56d301b | 994 | |
6d382616 FB |
995 | if (adapter->native->sl_ops->err_irq_dump_registers) |
996 | adapter->native->sl_ops->err_irq_dump_registers(adapter); | |
d56d301b FB |
997 | |
998 | return IRQ_HANDLED; | |
999 | } | |
1000 | ||
2b04cf31 | 1001 | int cxl_native_register_psl_err_irq(struct cxl *adapter) |
d56d301b FB |
1002 | { |
1003 | int rc; | |
1004 | ||
1005 | adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", | |
1006 | dev_name(&adapter->dev)); | |
1007 | if (!adapter->irq_name) | |
1008 | return -ENOMEM; | |
1009 | ||
2b04cf31 | 1010 | if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter, |
cbffa3a5 CL |
1011 | &adapter->native->err_hwirq, |
1012 | &adapter->native->err_virq, | |
d56d301b FB |
1013 | adapter->irq_name))) { |
1014 | kfree(adapter->irq_name); | |
1015 | adapter->irq_name = NULL; | |
1016 | return rc; | |
1017 | } | |
1018 | ||
cbffa3a5 | 1019 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff); |
d56d301b FB |
1020 | |
1021 | return 0; | |
1022 | } | |
1023 | ||
2b04cf31 | 1024 | void cxl_native_release_psl_err_irq(struct cxl *adapter) |
d56d301b | 1025 | { |
cbffa3a5 | 1026 | if (adapter->native->err_virq != irq_find_mapping(NULL, adapter->native->err_hwirq)) |
d56d301b FB |
1027 | return; |
1028 | ||
1029 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000); | |
cbffa3a5 CL |
1030 | cxl_unmap_irq(adapter->native->err_virq, adapter); |
1031 | cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq); | |
d56d301b FB |
1032 | kfree(adapter->irq_name); |
1033 | } | |
1034 | ||
2b04cf31 | 1035 | int cxl_native_register_serr_irq(struct cxl_afu *afu) |
d56d301b FB |
1036 | { |
1037 | u64 serr; | |
1038 | int rc; | |
1039 | ||
1040 | afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", | |
1041 | dev_name(&afu->dev)); | |
1042 | if (!afu->err_irq_name) | |
1043 | return -ENOMEM; | |
1044 | ||
2b04cf31 | 1045 | if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu, |
d56d301b FB |
1046 | &afu->serr_hwirq, |
1047 | &afu->serr_virq, afu->err_irq_name))) { | |
1048 | kfree(afu->err_irq_name); | |
1049 | afu->err_irq_name = NULL; | |
1050 | return rc; | |
1051 | } | |
1052 | ||
1053 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
1054 | serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff); | |
1055 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
2b04cf31 | 1060 | void cxl_native_release_serr_irq(struct cxl_afu *afu) |
d56d301b FB |
1061 | { |
1062 | if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq)) | |
1063 | return; | |
1064 | ||
1065 | cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000); | |
1066 | cxl_unmap_irq(afu->serr_virq, afu); | |
5be587b1 | 1067 | cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq); |
d56d301b FB |
1068 | kfree(afu->err_irq_name); |
1069 | } | |
1070 | ||
2b04cf31 | 1071 | int cxl_native_register_psl_irq(struct cxl_afu *afu) |
d56d301b FB |
1072 | { |
1073 | int rc; | |
1074 | ||
1075 | afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s", | |
1076 | dev_name(&afu->dev)); | |
1077 | if (!afu->psl_irq_name) | |
1078 | return -ENOMEM; | |
1079 | ||
cbffa3a5 CL |
1080 | if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed, |
1081 | afu, &afu->native->psl_hwirq, &afu->native->psl_virq, | |
d56d301b FB |
1082 | afu->psl_irq_name))) { |
1083 | kfree(afu->psl_irq_name); | |
1084 | afu->psl_irq_name = NULL; | |
1085 | } | |
1086 | return rc; | |
1087 | } | |
1088 | ||
2b04cf31 | 1089 | void cxl_native_release_psl_irq(struct cxl_afu *afu) |
d56d301b | 1090 | { |
cbffa3a5 | 1091 | if (afu->native->psl_virq != irq_find_mapping(NULL, afu->native->psl_hwirq)) |
d56d301b FB |
1092 | return; |
1093 | ||
cbffa3a5 CL |
1094 | cxl_unmap_irq(afu->native->psl_virq, afu); |
1095 | cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq); | |
d56d301b FB |
1096 | kfree(afu->psl_irq_name); |
1097 | } | |
1098 | ||
f204e0b8 IM |
1099 | static void recover_psl_err(struct cxl_afu *afu, u64 errstat) |
1100 | { | |
1101 | u64 dsisr; | |
1102 | ||
de369538 | 1103 | pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat); |
f204e0b8 IM |
1104 | |
1105 | /* Clear PSL_DSISR[PE] */ | |
1106 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
1107 | cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE); | |
1108 | ||
1109 | /* Write 1s to clear error status bits */ | |
1110 | cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat); | |
1111 | } | |
1112 | ||
2b04cf31 | 1113 | static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask) |
f204e0b8 | 1114 | { |
9bcf28cd | 1115 | trace_cxl_psl_irq_ack(ctx, tfc); |
f204e0b8 IM |
1116 | if (tfc) |
1117 | cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc); | |
1118 | if (psl_reset_mask) | |
1119 | recover_psl_err(ctx->afu, psl_reset_mask); | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | int cxl_check_error(struct cxl_afu *afu) | |
1125 | { | |
1126 | return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL); | |
1127 | } | |
d56d301b | 1128 | |
4752876c CL |
1129 | static bool native_support_attributes(const char *attr_name, |
1130 | enum cxl_attrs type) | |
1131 | { | |
1132 | return true; | |
1133 | } | |
1134 | ||
2b04cf31 | 1135 | static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out) |
d56d301b | 1136 | { |
0d400f77 | 1137 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
5be587b1 FB |
1138 | return -EIO; |
1139 | if (unlikely(off >= afu->crs_len)) | |
1140 | return -ERANGE; | |
cbffa3a5 | 1141 | *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset + |
5be587b1 FB |
1142 | (cr * afu->crs_len) + off); |
1143 | return 0; | |
d56d301b FB |
1144 | } |
1145 | ||
2b04cf31 | 1146 | static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out) |
d56d301b | 1147 | { |
0d400f77 | 1148 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
5be587b1 FB |
1149 | return -EIO; |
1150 | if (unlikely(off >= afu->crs_len)) | |
1151 | return -ERANGE; | |
cbffa3a5 | 1152 | *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset + |
5be587b1 FB |
1153 | (cr * afu->crs_len) + off); |
1154 | return 0; | |
d56d301b FB |
1155 | } |
1156 | ||
2b04cf31 | 1157 | static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out) |
d56d301b FB |
1158 | { |
1159 | u64 aligned_off = off & ~0x3L; | |
1160 | u32 val; | |
5be587b1 | 1161 | int rc; |
d56d301b | 1162 | |
2b04cf31 | 1163 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
5be587b1 FB |
1164 | if (!rc) |
1165 | *out = (val >> ((off & 0x3) * 8)) & 0xffff; | |
1166 | return rc; | |
d56d301b FB |
1167 | } |
1168 | ||
2b04cf31 | 1169 | static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out) |
d56d301b FB |
1170 | { |
1171 | u64 aligned_off = off & ~0x3L; | |
1172 | u32 val; | |
5be587b1 | 1173 | int rc; |
d56d301b | 1174 | |
2b04cf31 | 1175 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
5be587b1 FB |
1176 | if (!rc) |
1177 | *out = (val >> ((off & 0x3) * 8)) & 0xff; | |
1178 | return rc; | |
d56d301b | 1179 | } |
5be587b1 | 1180 | |
d601ea91 FB |
1181 | static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in) |
1182 | { | |
0d400f77 | 1183 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
d601ea91 FB |
1184 | return -EIO; |
1185 | if (unlikely(off >= afu->crs_len)) | |
1186 | return -ERANGE; | |
1187 | out_le32(afu->native->afu_desc_mmio + afu->crs_offset + | |
1188 | (cr * afu->crs_len) + off, in); | |
1189 | return 0; | |
1190 | } | |
1191 | ||
1192 | static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in) | |
1193 | { | |
1194 | u64 aligned_off = off & ~0x3L; | |
1195 | u32 val32, mask, shift; | |
1196 | int rc; | |
1197 | ||
1198 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); | |
1199 | if (rc) | |
1200 | return rc; | |
1201 | shift = (off & 0x3) * 8; | |
1202 | WARN_ON(shift == 24); | |
1203 | mask = 0xffff << shift; | |
1204 | val32 = (val32 & ~mask) | (in << shift); | |
1205 | ||
1206 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); | |
1207 | return rc; | |
1208 | } | |
1209 | ||
1210 | static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in) | |
1211 | { | |
1212 | u64 aligned_off = off & ~0x3L; | |
1213 | u32 val32, mask, shift; | |
1214 | int rc; | |
1215 | ||
1216 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); | |
1217 | if (rc) | |
1218 | return rc; | |
1219 | shift = (off & 0x3) * 8; | |
1220 | mask = 0xff << shift; | |
1221 | val32 = (val32 & ~mask) | (in << shift); | |
1222 | ||
1223 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); | |
1224 | return rc; | |
1225 | } | |
1226 | ||
5be587b1 FB |
1227 | const struct cxl_backend_ops cxl_native_ops = { |
1228 | .module = THIS_MODULE, | |
2b04cf31 FB |
1229 | .adapter_reset = cxl_pci_reset, |
1230 | .alloc_one_irq = cxl_pci_alloc_one_irq, | |
1231 | .release_one_irq = cxl_pci_release_one_irq, | |
1232 | .alloc_irq_ranges = cxl_pci_alloc_irq_ranges, | |
1233 | .release_irq_ranges = cxl_pci_release_irq_ranges, | |
1234 | .setup_irq = cxl_pci_setup_irq, | |
1235 | .handle_psl_slice_error = native_handle_psl_slice_error, | |
5be587b1 | 1236 | .psl_interrupt = NULL, |
2b04cf31 | 1237 | .ack_irq = native_ack_irq, |
2bc79ffc | 1238 | .irq_wait = native_irq_wait, |
2b04cf31 FB |
1239 | .attach_process = native_attach_process, |
1240 | .detach_process = native_detach_process, | |
292841b0 | 1241 | .update_ivtes = native_update_ivtes, |
4752876c | 1242 | .support_attributes = native_support_attributes, |
5be587b1 | 1243 | .link_ok = cxl_adapter_link_ok, |
2b04cf31 FB |
1244 | .release_afu = cxl_pci_release_afu, |
1245 | .afu_read_err_buffer = cxl_pci_afu_read_err_buffer, | |
1246 | .afu_check_and_enable = native_afu_check_and_enable, | |
1247 | .afu_activate_mode = native_afu_activate_mode, | |
1248 | .afu_deactivate_mode = native_afu_deactivate_mode, | |
1249 | .afu_reset = native_afu_reset, | |
1250 | .afu_cr_read8 = native_afu_cr_read8, | |
1251 | .afu_cr_read16 = native_afu_cr_read16, | |
1252 | .afu_cr_read32 = native_afu_cr_read32, | |
1253 | .afu_cr_read64 = native_afu_cr_read64, | |
d601ea91 FB |
1254 | .afu_cr_write8 = native_afu_cr_write8, |
1255 | .afu_cr_write16 = native_afu_cr_write16, | |
1256 | .afu_cr_write32 = native_afu_cr_write32, | |
1257 | .read_adapter_vpd = cxl_pci_read_adapter_vpd, | |
5be587b1 | 1258 | }; |