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Commit | Line | Data |
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f204e0b8 IM |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/spinlock.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/slab.h> | |
f204e0b8 IM |
13 | #include <linux/mutex.h> |
14 | #include <linux/mm.h> | |
15 | #include <linux/uaccess.h> | |
2bc79ffc | 16 | #include <linux/delay.h> |
f204e0b8 | 17 | #include <asm/synch.h> |
ec249dd8 | 18 | #include <misc/cxl-base.h> |
f204e0b8 IM |
19 | |
20 | #include "cxl.h" | |
9bcf28cd | 21 | #include "trace.h" |
f204e0b8 | 22 | |
5e7823c9 | 23 | static int afu_control(struct cxl_afu *afu, u64 command, u64 clear, |
f204e0b8 IM |
24 | u64 result, u64 mask, bool enabled) |
25 | { | |
5e7823c9 | 26 | u64 AFU_Cntl; |
f204e0b8 | 27 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
9bcf28cd | 28 | int rc = 0; |
f204e0b8 IM |
29 | |
30 | spin_lock(&afu->afu_cntl_lock); | |
31 | pr_devel("AFU command starting: %llx\n", command); | |
32 | ||
9bcf28cd IM |
33 | trace_cxl_afu_ctrl(afu, command); |
34 | ||
5e7823c9 IM |
35 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); |
36 | cxl_p2n_write(afu, CXL_AFU_Cntl_An, (AFU_Cntl & ~clear) | command); | |
f204e0b8 IM |
37 | |
38 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
39 | while ((AFU_Cntl & mask) != result) { | |
40 | if (time_after_eq(jiffies, timeout)) { | |
41 | dev_warn(&afu->dev, "WARNING: AFU control timed out!\n"); | |
9bcf28cd IM |
42 | rc = -EBUSY; |
43 | goto out; | |
f204e0b8 | 44 | } |
0b3f9c75 | 45 | |
0d400f77 | 46 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
47 | afu->enabled = enabled; |
48 | rc = -EIO; | |
49 | goto out; | |
50 | } | |
51 | ||
de369538 | 52 | pr_devel_ratelimited("AFU control... (0x%016llx)\n", |
f204e0b8 IM |
53 | AFU_Cntl | command); |
54 | cpu_relax(); | |
55 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
3382a622 | 56 | } |
2a4f667a IM |
57 | |
58 | if (AFU_Cntl & CXL_AFU_Cntl_An_RA) { | |
59 | /* | |
60 | * Workaround for a bug in the XSL used in the Mellanox CX4 | |
61 | * that fails to clear the RA bit after an AFU reset, | |
62 | * preventing subsequent AFU resets from working. | |
63 | */ | |
64 | cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl & ~CXL_AFU_Cntl_An_RA); | |
65 | } | |
66 | ||
f204e0b8 IM |
67 | pr_devel("AFU command complete: %llx\n", command); |
68 | afu->enabled = enabled; | |
9bcf28cd IM |
69 | out: |
70 | trace_cxl_afu_ctrl_done(afu, command, rc); | |
f204e0b8 IM |
71 | spin_unlock(&afu->afu_cntl_lock); |
72 | ||
9bcf28cd | 73 | return rc; |
f204e0b8 IM |
74 | } |
75 | ||
76 | static int afu_enable(struct cxl_afu *afu) | |
77 | { | |
78 | pr_devel("AFU enable request\n"); | |
79 | ||
5e7823c9 | 80 | return afu_control(afu, CXL_AFU_Cntl_An_E, 0, |
f204e0b8 IM |
81 | CXL_AFU_Cntl_An_ES_Enabled, |
82 | CXL_AFU_Cntl_An_ES_MASK, true); | |
83 | } | |
84 | ||
85 | int cxl_afu_disable(struct cxl_afu *afu) | |
86 | { | |
87 | pr_devel("AFU disable request\n"); | |
88 | ||
5e7823c9 IM |
89 | return afu_control(afu, 0, CXL_AFU_Cntl_An_E, |
90 | CXL_AFU_Cntl_An_ES_Disabled, | |
f204e0b8 IM |
91 | CXL_AFU_Cntl_An_ES_MASK, false); |
92 | } | |
93 | ||
94 | /* This will disable as well as reset */ | |
2b04cf31 | 95 | static int native_afu_reset(struct cxl_afu *afu) |
f204e0b8 IM |
96 | { |
97 | pr_devel("AFU reset request\n"); | |
98 | ||
5e7823c9 | 99 | return afu_control(afu, CXL_AFU_Cntl_An_RA, 0, |
f204e0b8 IM |
100 | CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled, |
101 | CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK, | |
102 | false); | |
103 | } | |
104 | ||
2b04cf31 | 105 | static int native_afu_check_and_enable(struct cxl_afu *afu) |
f204e0b8 | 106 | { |
0d400f77 | 107 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
108 | WARN(1, "Refusing to enable afu while link down!\n"); |
109 | return -EIO; | |
110 | } | |
f204e0b8 IM |
111 | if (afu->enabled) |
112 | return 0; | |
113 | return afu_enable(afu); | |
114 | } | |
115 | ||
116 | int cxl_psl_purge(struct cxl_afu *afu) | |
117 | { | |
118 | u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
119 | u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
120 | u64 dsisr, dar; | |
121 | u64 start, end; | |
5f761c26 | 122 | u64 trans_fault = 0x0ULL; |
f204e0b8 | 123 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
9bcf28cd IM |
124 | int rc = 0; |
125 | ||
126 | trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc); | |
f204e0b8 IM |
127 | |
128 | pr_devel("PSL purge request\n"); | |
129 | ||
5f761c26 CL |
130 | if (cxl_is_psl8(afu)) |
131 | trans_fault = CXL_PSL_DSISR_TRANS; | |
132 | if (cxl_is_psl9(afu)) | |
133 | trans_fault = CXL_PSL9_DSISR_An_TF; | |
134 | ||
0d400f77 | 135 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
136 | dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n"); |
137 | rc = -EIO; | |
138 | goto out; | |
139 | } | |
140 | ||
f204e0b8 IM |
141 | if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { |
142 | WARN(1, "psl_purge request while AFU not disabled!\n"); | |
143 | cxl_afu_disable(afu); | |
144 | } | |
145 | ||
146 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, | |
147 | PSL_CNTL | CXL_PSL_SCNTL_An_Pc); | |
148 | start = local_clock(); | |
149 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
150 | while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK) | |
151 | == CXL_PSL_SCNTL_An_Ps_Pending) { | |
152 | if (time_after_eq(jiffies, timeout)) { | |
153 | dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n"); | |
9bcf28cd IM |
154 | rc = -EBUSY; |
155 | goto out; | |
f204e0b8 | 156 | } |
0d400f77 | 157 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
158 | rc = -EIO; |
159 | goto out; | |
160 | } | |
161 | ||
f204e0b8 | 162 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
d371edf5 CL |
163 | pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", |
164 | PSL_CNTL, dsisr); | |
165 | ||
5f761c26 | 166 | if (dsisr & trans_fault) { |
f204e0b8 | 167 | dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); |
d371edf5 CL |
168 | dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", |
169 | dsisr, dar); | |
f204e0b8 IM |
170 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); |
171 | } else if (dsisr) { | |
d371edf5 CL |
172 | dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", |
173 | dsisr); | |
f204e0b8 IM |
174 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); |
175 | } else { | |
176 | cpu_relax(); | |
177 | } | |
178 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
3382a622 | 179 | } |
f204e0b8 IM |
180 | end = local_clock(); |
181 | pr_devel("PSL purged in %lld ns\n", end - start); | |
182 | ||
183 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, | |
184 | PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc); | |
9bcf28cd IM |
185 | out: |
186 | trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc); | |
187 | return rc; | |
f204e0b8 IM |
188 | } |
189 | ||
190 | static int spa_max_procs(int spa_size) | |
191 | { | |
192 | /* | |
193 | * From the CAIA: | |
194 | * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255 | |
195 | * Most of that junk is really just an overly-complicated way of saying | |
196 | * the last 256 bytes are __aligned(128), so it's really: | |
197 | * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255 | |
198 | * and | |
199 | * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1 | |
200 | * so | |
201 | * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256 | |
202 | * Ignore the alignment (which is safe in this case as long as we are | |
203 | * careful with our rounding) and solve for n: | |
204 | */ | |
205 | return ((spa_size / 8) - 96) / 17; | |
206 | } | |
207 | ||
5f761c26 | 208 | static int cxl_alloc_spa(struct cxl_afu *afu, int mode) |
f204e0b8 | 209 | { |
895a7980 IM |
210 | unsigned spa_size; |
211 | ||
f204e0b8 | 212 | /* Work out how many pages to allocate */ |
2224b671 | 213 | afu->native->spa_order = -1; |
f204e0b8 | 214 | do { |
cbffa3a5 | 215 | afu->native->spa_order++; |
895a7980 IM |
216 | spa_size = (1 << afu->native->spa_order) * PAGE_SIZE; |
217 | ||
218 | if (spa_size > 0x100000) { | |
219 | dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n", | |
220 | afu->native->spa_max_procs, afu->native->spa_size); | |
5f761c26 CL |
221 | if (mode != CXL_MODE_DEDICATED) |
222 | afu->num_procs = afu->native->spa_max_procs; | |
895a7980 IM |
223 | break; |
224 | } | |
225 | ||
226 | afu->native->spa_size = spa_size; | |
cbffa3a5 CL |
227 | afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size); |
228 | } while (afu->native->spa_max_procs < afu->num_procs); | |
f204e0b8 | 229 | |
cbffa3a5 CL |
230 | if (!(afu->native->spa = (struct cxl_process_element *) |
231 | __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) { | |
f204e0b8 IM |
232 | pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n"); |
233 | return -ENOMEM; | |
234 | } | |
235 | pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n", | |
cbffa3a5 | 236 | 1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs); |
f204e0b8 | 237 | |
05155772 DA |
238 | return 0; |
239 | } | |
240 | ||
241 | static void attach_spa(struct cxl_afu *afu) | |
242 | { | |
243 | u64 spap; | |
244 | ||
cbffa3a5 CL |
245 | afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa + |
246 | ((afu->native->spa_max_procs + 3) * 128)); | |
f204e0b8 | 247 | |
cbffa3a5 CL |
248 | spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr; |
249 | spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size; | |
f204e0b8 | 250 | spap |= CXL_PSL_SPAP_V; |
cbffa3a5 CL |
251 | pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", |
252 | afu->native->spa, afu->native->spa_max_procs, | |
253 | afu->native->sw_command_status, spap); | |
f204e0b8 | 254 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap); |
f204e0b8 IM |
255 | } |
256 | ||
05155772 | 257 | static inline void detach_spa(struct cxl_afu *afu) |
f204e0b8 | 258 | { |
db7933f3 | 259 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); |
05155772 DA |
260 | } |
261 | ||
262 | void cxl_release_spa(struct cxl_afu *afu) | |
263 | { | |
cbffa3a5 CL |
264 | if (afu->native->spa) { |
265 | free_pages((unsigned long) afu->native->spa, | |
266 | afu->native->spa_order); | |
267 | afu->native->spa = NULL; | |
05155772 | 268 | } |
f204e0b8 IM |
269 | } |
270 | ||
5f761c26 CL |
271 | /* |
272 | * Invalidation of all ERAT entries is no longer required by CAIA2. Use | |
273 | * only for debug. | |
274 | */ | |
275 | int cxl_invalidate_all_psl9(struct cxl *adapter) | |
276 | { | |
277 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
278 | u64 ierat; | |
279 | ||
280 | pr_devel("CXL adapter - invalidation of all ERAT entries\n"); | |
281 | ||
282 | /* Invalidates all ERAT entries for Radix or HPT */ | |
283 | ierat = CXL_XSL9_IERAT_IALL; | |
284 | if (radix_enabled()) | |
285 | ierat |= CXL_XSL9_IERAT_INVR; | |
286 | cxl_p1_write(adapter, CXL_XSL9_IERAT, ierat); | |
287 | ||
288 | while (cxl_p1_read(adapter, CXL_XSL9_IERAT) & CXL_XSL9_IERAT_IINPROG) { | |
289 | if (time_after_eq(jiffies, timeout)) { | |
290 | dev_warn(&adapter->dev, | |
291 | "WARNING: CXL adapter invalidation of all ERAT entries timed out!\n"); | |
292 | return -EBUSY; | |
293 | } | |
294 | if (!cxl_ops->link_ok(adapter, NULL)) | |
295 | return -EIO; | |
296 | cpu_relax(); | |
297 | } | |
298 | return 0; | |
299 | } | |
300 | ||
f6ac63a5 | 301 | int cxl_invalidate_all_psl8(struct cxl *adapter) |
f204e0b8 IM |
302 | { |
303 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
304 | ||
305 | pr_devel("CXL adapter wide TLBIA & SLBIA\n"); | |
306 | ||
307 | cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A); | |
308 | ||
309 | cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL); | |
310 | while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) { | |
311 | if (time_after_eq(jiffies, timeout)) { | |
312 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n"); | |
313 | return -EBUSY; | |
314 | } | |
0d400f77 | 315 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 316 | return -EIO; |
f204e0b8 IM |
317 | cpu_relax(); |
318 | } | |
319 | ||
320 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL); | |
321 | while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) { | |
322 | if (time_after_eq(jiffies, timeout)) { | |
323 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n"); | |
324 | return -EBUSY; | |
325 | } | |
0d400f77 | 326 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 327 | return -EIO; |
f204e0b8 IM |
328 | cpu_relax(); |
329 | } | |
330 | return 0; | |
331 | } | |
332 | ||
aaa2245e FB |
333 | int cxl_data_cache_flush(struct cxl *adapter) |
334 | { | |
335 | u64 reg; | |
336 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
337 | ||
338 | pr_devel("Flushing data cache\n"); | |
339 | ||
340 | reg = cxl_p1_read(adapter, CXL_PSL_Control); | |
341 | reg |= CXL_PSL_Control_Fr; | |
342 | cxl_p1_write(adapter, CXL_PSL_Control, reg); | |
343 | ||
344 | reg = cxl_p1_read(adapter, CXL_PSL_Control); | |
345 | while ((reg & CXL_PSL_Control_Fs_MASK) != CXL_PSL_Control_Fs_Complete) { | |
346 | if (time_after_eq(jiffies, timeout)) { | |
347 | dev_warn(&adapter->dev, "WARNING: cache flush timed out!\n"); | |
348 | return -EBUSY; | |
349 | } | |
350 | ||
351 | if (!cxl_ops->link_ok(adapter, NULL)) { | |
352 | dev_warn(&adapter->dev, "WARNING: link down when flushing cache\n"); | |
353 | return -EIO; | |
354 | } | |
355 | cpu_relax(); | |
356 | reg = cxl_p1_read(adapter, CXL_PSL_Control); | |
357 | } | |
358 | ||
359 | reg &= ~CXL_PSL_Control_Fr; | |
360 | cxl_p1_write(adapter, CXL_PSL_Control, reg); | |
361 | return 0; | |
362 | } | |
363 | ||
f204e0b8 IM |
364 | static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1) |
365 | { | |
366 | int rc; | |
367 | ||
368 | /* 1. Disable SSTP by writing 0 to SSTP1[V] */ | |
369 | cxl_p2n_write(afu, CXL_SSTP1_An, 0); | |
370 | ||
371 | /* 2. Invalidate all SLB entries */ | |
372 | if ((rc = cxl_afu_slbia(afu))) | |
373 | return rc; | |
374 | ||
375 | /* 3. Set SSTP0_An */ | |
376 | cxl_p2n_write(afu, CXL_SSTP0_An, sstp0); | |
377 | ||
378 | /* 4. Set SSTP1_An */ | |
379 | cxl_p2n_write(afu, CXL_SSTP1_An, sstp1); | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
384 | /* Using per slice version may improve performance here. (ie. SLBIA_An) */ | |
385 | static void slb_invalid(struct cxl_context *ctx) | |
386 | { | |
387 | struct cxl *adapter = ctx->afu->adapter; | |
388 | u64 slbia; | |
389 | ||
cbffa3a5 | 390 | WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex)); |
f204e0b8 IM |
391 | |
392 | cxl_p1_write(adapter, CXL_PSL_LBISEL, | |
393 | ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) | | |
394 | be32_to_cpu(ctx->elem->lpid)); | |
395 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID); | |
396 | ||
397 | while (1) { | |
0d400f77 | 398 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 399 | break; |
f204e0b8 IM |
400 | slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA); |
401 | if (!(slbia & CXL_TLB_SLB_P)) | |
402 | break; | |
403 | cpu_relax(); | |
404 | } | |
405 | } | |
406 | ||
407 | static int do_process_element_cmd(struct cxl_context *ctx, | |
408 | u64 cmd, u64 pe_state) | |
409 | { | |
410 | u64 state; | |
a98e6e9f | 411 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
9bcf28cd IM |
412 | int rc = 0; |
413 | ||
414 | trace_cxl_llcmd(ctx, cmd); | |
f204e0b8 IM |
415 | |
416 | WARN_ON(!ctx->afu->enabled); | |
417 | ||
418 | ctx->elem->software_state = cpu_to_be32(pe_state); | |
419 | smp_wmb(); | |
cbffa3a5 | 420 | *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe); |
f204e0b8 IM |
421 | smp_mb(); |
422 | cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe); | |
423 | while (1) { | |
a98e6e9f IM |
424 | if (time_after_eq(jiffies, timeout)) { |
425 | dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n"); | |
9bcf28cd IM |
426 | rc = -EBUSY; |
427 | goto out; | |
a98e6e9f | 428 | } |
0d400f77 | 429 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
0b3f9c75 DA |
430 | dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n"); |
431 | rc = -EIO; | |
432 | goto out; | |
433 | } | |
cbffa3a5 | 434 | state = be64_to_cpup(ctx->afu->native->sw_command_status); |
f204e0b8 IM |
435 | if (state == ~0ULL) { |
436 | pr_err("cxl: Error adding process element to AFU\n"); | |
9bcf28cd IM |
437 | rc = -1; |
438 | goto out; | |
f204e0b8 IM |
439 | } |
440 | if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) == | |
441 | (cmd | (cmd >> 16) | ctx->pe)) | |
442 | break; | |
443 | /* | |
444 | * The command won't finish in the PSL if there are | |
445 | * outstanding DSIs. Hence we need to yield here in | |
446 | * case there are outstanding DSIs that we need to | |
447 | * service. Tuning possiblity: we could wait for a | |
448 | * while before sched | |
449 | */ | |
450 | schedule(); | |
451 | ||
452 | } | |
9bcf28cd IM |
453 | out: |
454 | trace_cxl_llcmd_done(ctx, cmd, rc); | |
455 | return rc; | |
f204e0b8 IM |
456 | } |
457 | ||
458 | static int add_process_element(struct cxl_context *ctx) | |
459 | { | |
460 | int rc = 0; | |
461 | ||
cbffa3a5 | 462 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
463 | pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe); |
464 | if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V))) | |
465 | ctx->pe_inserted = true; | |
466 | pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 467 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
468 | return rc; |
469 | } | |
470 | ||
471 | static int terminate_process_element(struct cxl_context *ctx) | |
472 | { | |
473 | int rc = 0; | |
474 | ||
475 | /* fast path terminate if it's already invalid */ | |
476 | if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V))) | |
477 | return rc; | |
478 | ||
cbffa3a5 | 479 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 | 480 | pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe); |
0b3f9c75 DA |
481 | /* We could be asked to terminate when the hw is down. That |
482 | * should always succeed: it's not running if the hw has gone | |
483 | * away and is being reset. | |
484 | */ | |
0d400f77 | 485 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
0b3f9c75 DA |
486 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE, |
487 | CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T); | |
f204e0b8 IM |
488 | ctx->elem->software_state = 0; /* Remove Valid bit */ |
489 | pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 490 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
491 | return rc; |
492 | } | |
493 | ||
494 | static int remove_process_element(struct cxl_context *ctx) | |
495 | { | |
496 | int rc = 0; | |
497 | ||
cbffa3a5 | 498 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 | 499 | pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe); |
0b3f9c75 DA |
500 | |
501 | /* We could be asked to remove when the hw is down. Again, if | |
502 | * the hw is down, the PE is gone, so we succeed. | |
503 | */ | |
0d400f77 | 504 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
0b3f9c75 DA |
505 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0); |
506 | ||
507 | if (!rc) | |
f204e0b8 | 508 | ctx->pe_inserted = false; |
d371edf5 CL |
509 | if (cxl_is_power8()) |
510 | slb_invalid(ctx); | |
f204e0b8 | 511 | pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe); |
cbffa3a5 | 512 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
513 | |
514 | return rc; | |
515 | } | |
516 | ||
1a1a94b8 | 517 | void cxl_assign_psn_space(struct cxl_context *ctx) |
f204e0b8 IM |
518 | { |
519 | if (!ctx->afu->pp_size || ctx->master) { | |
520 | ctx->psn_phys = ctx->afu->psn_phys; | |
521 | ctx->psn_size = ctx->afu->adapter->ps_size; | |
522 | } else { | |
523 | ctx->psn_phys = ctx->afu->psn_phys + | |
cbffa3a5 | 524 | (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe); |
f204e0b8 IM |
525 | ctx->psn_size = ctx->afu->pp_size; |
526 | } | |
527 | } | |
528 | ||
529 | static int activate_afu_directed(struct cxl_afu *afu) | |
530 | { | |
531 | int rc; | |
532 | ||
533 | dev_info(&afu->dev, "Activating AFU directed mode\n"); | |
534 | ||
4108efb0 | 535 | afu->num_procs = afu->max_procs_virtualised; |
cbffa3a5 | 536 | if (afu->native->spa == NULL) { |
5f761c26 | 537 | if (cxl_alloc_spa(afu, CXL_MODE_DIRECTED)) |
05155772 DA |
538 | return -ENOMEM; |
539 | } | |
540 | attach_spa(afu); | |
f204e0b8 IM |
541 | |
542 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU); | |
d371edf5 CL |
543 | if (cxl_is_power8()) |
544 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); | |
f204e0b8 IM |
545 | cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L); |
546 | ||
547 | afu->current_mode = CXL_MODE_DIRECTED; | |
f204e0b8 IM |
548 | |
549 | if ((rc = cxl_chardev_m_afu_add(afu))) | |
550 | return rc; | |
551 | ||
552 | if ((rc = cxl_sysfs_afu_m_add(afu))) | |
553 | goto err; | |
554 | ||
555 | if ((rc = cxl_chardev_s_afu_add(afu))) | |
556 | goto err1; | |
557 | ||
558 | return 0; | |
559 | err1: | |
560 | cxl_sysfs_afu_m_remove(afu); | |
561 | err: | |
562 | cxl_chardev_afu_remove(afu); | |
563 | return rc; | |
564 | } | |
565 | ||
566 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
567 | #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE) | |
568 | #else | |
569 | #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE)) | |
570 | #endif | |
571 | ||
2f663527 MN |
572 | static u64 calculate_sr(struct cxl_context *ctx) |
573 | { | |
574 | u64 sr = 0; | |
575 | ||
e606e035 | 576 | set_endian(sr); |
2f663527 MN |
577 | if (ctx->master) |
578 | sr |= CXL_PSL_SR_An_MP; | |
579 | if (mfspr(SPRN_LPCR) & LPCR_TC) | |
580 | sr |= CXL_PSL_SR_An_TC; | |
581 | if (ctx->kernel) { | |
7a0d85d3 IM |
582 | if (!ctx->real_mode) |
583 | sr |= CXL_PSL_SR_An_R; | |
584 | sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV; | |
2f663527 MN |
585 | } else { |
586 | sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; | |
5f761c26 CL |
587 | if (radix_enabled()) |
588 | sr |= CXL_PSL_SR_An_HV; | |
589 | else | |
590 | sr &= ~(CXL_PSL_SR_An_HV); | |
2f663527 MN |
591 | if (!test_tsk_thread_flag(current, TIF_32BIT)) |
592 | sr |= CXL_PSL_SR_An_SF; | |
593 | } | |
5f761c26 CL |
594 | if (cxl_is_psl9(ctx->afu)) { |
595 | if (radix_enabled()) | |
596 | sr |= CXL_PSL_SR_An_XLAT_ror; | |
597 | else | |
598 | sr |= CXL_PSL_SR_An_XLAT_hpt; | |
599 | } | |
2f663527 MN |
600 | return sr; |
601 | } | |
602 | ||
292841b0 IM |
603 | static void update_ivtes_directed(struct cxl_context *ctx) |
604 | { | |
605 | bool need_update = (ctx->status == STARTED); | |
606 | int r; | |
607 | ||
608 | if (need_update) { | |
609 | WARN_ON(terminate_process_element(ctx)); | |
610 | WARN_ON(remove_process_element(ctx)); | |
611 | } | |
612 | ||
613 | for (r = 0; r < CXL_IRQ_RANGES; r++) { | |
614 | ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]); | |
615 | ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]); | |
616 | } | |
617 | ||
618 | /* | |
619 | * Theoretically we could use the update llcmd, instead of a | |
620 | * terminate/remove/add (or if an atomic update was required we could | |
621 | * do a suspend/update/resume), however it seems there might be issues | |
622 | * with the update llcmd on some cards (including those using an XSL on | |
623 | * an ASIC) so for now it's safest to go with the commands that are | |
624 | * known to work. In the future if we come across a situation where the | |
625 | * card may be performing transactions using the same PE while we are | |
626 | * doing this update we might need to revisit this. | |
627 | */ | |
628 | if (need_update) | |
629 | WARN_ON(add_process_element(ctx)); | |
630 | } | |
631 | ||
5f761c26 CL |
632 | static int process_element_entry_psl9(struct cxl_context *ctx, u64 wed, u64 amr) |
633 | { | |
634 | u32 pid; | |
635 | ||
636 | cxl_assign_psn_space(ctx); | |
637 | ||
638 | ctx->elem->ctxtime = 0; /* disable */ | |
639 | ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID)); | |
640 | ctx->elem->haurp = 0; /* disable */ | |
641 | ||
642 | if (ctx->kernel) | |
643 | pid = 0; | |
644 | else { | |
645 | if (ctx->mm == NULL) { | |
646 | pr_devel("%s: unable to get mm for pe=%d pid=%i\n", | |
647 | __func__, ctx->pe, pid_nr(ctx->pid)); | |
648 | return -EINVAL; | |
649 | } | |
650 | pid = ctx->mm->context.id; | |
651 | } | |
652 | ||
653 | ctx->elem->common.tid = 0; | |
654 | ctx->elem->common.pid = cpu_to_be32(pid); | |
655 | ||
656 | ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); | |
657 | ||
658 | ctx->elem->common.csrp = 0; /* disable */ | |
659 | ||
660 | cxl_prefault(ctx, wed); | |
661 | ||
662 | /* | |
663 | * Ensure we have the multiplexed PSL interrupt set up to take faults | |
664 | * for kernel contexts that may not have allocated any AFU IRQs at all: | |
665 | */ | |
666 | if (ctx->irqs.range[0] == 0) { | |
667 | ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq; | |
668 | ctx->irqs.range[0] = 1; | |
669 | } | |
670 | ||
671 | ctx->elem->common.amr = cpu_to_be64(amr); | |
672 | ctx->elem->common.wed = cpu_to_be64(wed); | |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
677 | int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr) | |
678 | { | |
679 | int result; | |
680 | ||
681 | /* fill the process element entry */ | |
682 | result = process_element_entry_psl9(ctx, wed, amr); | |
683 | if (result) | |
684 | return result; | |
685 | ||
686 | update_ivtes_directed(ctx); | |
687 | ||
688 | /* first guy needs to enable */ | |
689 | result = cxl_ops->afu_check_and_enable(ctx->afu); | |
690 | if (result) | |
691 | return result; | |
692 | ||
693 | return add_process_element(ctx); | |
694 | } | |
695 | ||
f6ac63a5 | 696 | int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr) |
f204e0b8 | 697 | { |
2f663527 | 698 | u32 pid; |
292841b0 | 699 | int result; |
f204e0b8 | 700 | |
1a1a94b8 | 701 | cxl_assign_psn_space(ctx); |
f204e0b8 IM |
702 | |
703 | ctx->elem->ctxtime = 0; /* disable */ | |
704 | ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID)); | |
705 | ctx->elem->haurp = 0; /* disable */ | |
5f761c26 | 706 | ctx->elem->u.sdr = cpu_to_be64(mfspr(SPRN_SDR1)); |
f204e0b8 | 707 | |
2f663527 MN |
708 | pid = current->pid; |
709 | if (ctx->kernel) | |
710 | pid = 0; | |
f204e0b8 | 711 | ctx->elem->common.tid = 0; |
2f663527 MN |
712 | ctx->elem->common.pid = cpu_to_be32(pid); |
713 | ||
714 | ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); | |
f204e0b8 IM |
715 | |
716 | ctx->elem->common.csrp = 0; /* disable */ | |
5f761c26 CL |
717 | ctx->elem->common.u.psl8.aurp0 = 0; /* disable */ |
718 | ctx->elem->common.u.psl8.aurp1 = 0; /* disable */ | |
f204e0b8 IM |
719 | |
720 | cxl_prefault(ctx, wed); | |
721 | ||
5f761c26 CL |
722 | ctx->elem->common.u.psl8.sstp0 = cpu_to_be64(ctx->sstp0); |
723 | ctx->elem->common.u.psl8.sstp1 = cpu_to_be64(ctx->sstp1); | |
f204e0b8 | 724 | |
3c206fa7 IM |
725 | /* |
726 | * Ensure we have the multiplexed PSL interrupt set up to take faults | |
727 | * for kernel contexts that may not have allocated any AFU IRQs at all: | |
728 | */ | |
729 | if (ctx->irqs.range[0] == 0) { | |
730 | ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq; | |
731 | ctx->irqs.range[0] = 1; | |
732 | } | |
733 | ||
292841b0 | 734 | update_ivtes_directed(ctx); |
f204e0b8 IM |
735 | |
736 | ctx->elem->common.amr = cpu_to_be64(amr); | |
737 | ctx->elem->common.wed = cpu_to_be64(wed); | |
738 | ||
739 | /* first guy needs to enable */ | |
5be587b1 | 740 | if ((result = cxl_ops->afu_check_and_enable(ctx->afu))) |
f204e0b8 IM |
741 | return result; |
742 | ||
368857c1 | 743 | return add_process_element(ctx); |
f204e0b8 IM |
744 | } |
745 | ||
746 | static int deactivate_afu_directed(struct cxl_afu *afu) | |
747 | { | |
748 | dev_info(&afu->dev, "Deactivating AFU directed mode\n"); | |
749 | ||
750 | afu->current_mode = 0; | |
751 | afu->num_procs = 0; | |
752 | ||
753 | cxl_sysfs_afu_m_remove(afu); | |
754 | cxl_chardev_afu_remove(afu); | |
755 | ||
5e7823c9 IM |
756 | /* |
757 | * The CAIA section 2.2.1 indicates that the procedure for starting and | |
758 | * stopping an AFU in AFU directed mode is AFU specific, which is not | |
759 | * ideal since this code is generic and with one exception has no | |
760 | * knowledge of the AFU. This is in contrast to the procedure for | |
761 | * disabling a dedicated process AFU, which is documented to just | |
762 | * require a reset. The architecture does indicate that both an AFU | |
763 | * reset and an AFU disable should result in the AFU being disabled and | |
764 | * we do both followed by a PSL purge for safety. | |
765 | * | |
766 | * Notably we used to have some issues with the disable sequence on PSL | |
767 | * cards, which is why we ended up using this heavy weight procedure in | |
768 | * the first place, however a bug was discovered that had rendered the | |
769 | * disable operation ineffective, so it is conceivable that was the | |
770 | * sole explanation for those difficulties. Careful regression testing | |
771 | * is recommended if anyone attempts to remove or reorder these | |
772 | * operations. | |
773 | * | |
774 | * The XSL on the Mellanox CX4 behaves a little differently from the | |
775 | * PSL based cards and will time out an AFU reset if the AFU is still | |
776 | * enabled. That card is special in that we do have a means to identify | |
777 | * it from this code, so in that case we skip the reset and just use a | |
778 | * disable/purge to avoid the timeout and corresponding noise in the | |
779 | * kernel log. | |
780 | */ | |
781 | if (afu->adapter->native->sl_ops->needs_reset_before_disable) | |
782 | cxl_ops->afu_reset(afu); | |
f204e0b8 IM |
783 | cxl_afu_disable(afu); |
784 | cxl_psl_purge(afu); | |
785 | ||
f204e0b8 IM |
786 | return 0; |
787 | } | |
788 | ||
5f761c26 CL |
789 | int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu) |
790 | { | |
791 | dev_info(&afu->dev, "Activating dedicated process mode\n"); | |
792 | ||
793 | /* | |
794 | * If XSL is set to dedicated mode (Set in PSL_SCNTL reg), the | |
795 | * XSL and AFU are programmed to work with a single context. | |
796 | * The context information should be configured in the SPA area | |
797 | * index 0 (so PSL_SPAP must be configured before enabling the | |
798 | * AFU). | |
799 | */ | |
800 | afu->num_procs = 1; | |
801 | if (afu->native->spa == NULL) { | |
802 | if (cxl_alloc_spa(afu, CXL_MODE_DEDICATED)) | |
803 | return -ENOMEM; | |
804 | } | |
805 | attach_spa(afu); | |
806 | ||
807 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process); | |
808 | cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L); | |
809 | ||
810 | afu->current_mode = CXL_MODE_DEDICATED; | |
811 | ||
812 | return cxl_chardev_d_afu_add(afu); | |
813 | } | |
814 | ||
f6ac63a5 | 815 | int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu) |
f204e0b8 IM |
816 | { |
817 | dev_info(&afu->dev, "Activating dedicated process mode\n"); | |
818 | ||
819 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process); | |
820 | ||
821 | cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */ | |
822 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */ | |
823 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); | |
824 | cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID)); | |
825 | cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */ | |
826 | cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1)); | |
827 | ||
828 | cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */ | |
829 | cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */ | |
830 | cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */ | |
831 | ||
832 | afu->current_mode = CXL_MODE_DEDICATED; | |
833 | afu->num_procs = 1; | |
834 | ||
835 | return cxl_chardev_d_afu_add(afu); | |
836 | } | |
837 | ||
5f761c26 CL |
838 | void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx) |
839 | { | |
840 | int r; | |
841 | ||
842 | for (r = 0; r < CXL_IRQ_RANGES; r++) { | |
843 | ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]); | |
844 | ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]); | |
845 | } | |
846 | } | |
847 | ||
f6ac63a5 | 848 | void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx) |
292841b0 IM |
849 | { |
850 | struct cxl_afu *afu = ctx->afu; | |
851 | ||
852 | cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, | |
853 | (((u64)ctx->irqs.offset[0] & 0xffff) << 48) | | |
854 | (((u64)ctx->irqs.offset[1] & 0xffff) << 32) | | |
855 | (((u64)ctx->irqs.offset[2] & 0xffff) << 16) | | |
856 | ((u64)ctx->irqs.offset[3] & 0xffff)); | |
857 | cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64) | |
858 | (((u64)ctx->irqs.range[0] & 0xffff) << 48) | | |
859 | (((u64)ctx->irqs.range[1] & 0xffff) << 32) | | |
860 | (((u64)ctx->irqs.range[2] & 0xffff) << 16) | | |
861 | ((u64)ctx->irqs.range[3] & 0xffff)); | |
862 | } | |
863 | ||
5f761c26 CL |
864 | int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr) |
865 | { | |
866 | struct cxl_afu *afu = ctx->afu; | |
867 | int result; | |
868 | ||
869 | /* fill the process element entry */ | |
870 | result = process_element_entry_psl9(ctx, wed, amr); | |
871 | if (result) | |
872 | return result; | |
873 | ||
874 | if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes) | |
875 | afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx); | |
876 | ||
877 | result = cxl_ops->afu_reset(afu); | |
878 | if (result) | |
879 | return result; | |
880 | ||
881 | return afu_enable(afu); | |
882 | } | |
883 | ||
f6ac63a5 | 884 | int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr) |
f204e0b8 IM |
885 | { |
886 | struct cxl_afu *afu = ctx->afu; | |
2f663527 | 887 | u64 pid; |
f204e0b8 IM |
888 | int rc; |
889 | ||
2f663527 MN |
890 | pid = (u64)current->pid << 32; |
891 | if (ctx->kernel) | |
892 | pid = 0; | |
893 | cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid); | |
894 | ||
895 | cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx)); | |
f204e0b8 IM |
896 | |
897 | if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1))) | |
898 | return rc; | |
899 | ||
900 | cxl_prefault(ctx, wed); | |
901 | ||
6f2ed3bf CL |
902 | if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes) |
903 | afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx); | |
f204e0b8 IM |
904 | |
905 | cxl_p2n_write(afu, CXL_PSL_AMR_An, amr); | |
906 | ||
907 | /* master only context for dedicated */ | |
1a1a94b8 | 908 | cxl_assign_psn_space(ctx); |
f204e0b8 | 909 | |
5be587b1 | 910 | if ((rc = cxl_ops->afu_reset(afu))) |
f204e0b8 IM |
911 | return rc; |
912 | ||
913 | cxl_p2n_write(afu, CXL_PSL_WED_An, wed); | |
914 | ||
915 | return afu_enable(afu); | |
916 | } | |
917 | ||
918 | static int deactivate_dedicated_process(struct cxl_afu *afu) | |
919 | { | |
920 | dev_info(&afu->dev, "Deactivating dedicated process mode\n"); | |
921 | ||
922 | afu->current_mode = 0; | |
923 | afu->num_procs = 0; | |
924 | ||
925 | cxl_chardev_afu_remove(afu); | |
926 | ||
927 | return 0; | |
928 | } | |
929 | ||
2b04cf31 | 930 | static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode) |
f204e0b8 IM |
931 | { |
932 | if (mode == CXL_MODE_DIRECTED) | |
933 | return deactivate_afu_directed(afu); | |
934 | if (mode == CXL_MODE_DEDICATED) | |
935 | return deactivate_dedicated_process(afu); | |
936 | return 0; | |
937 | } | |
938 | ||
2b04cf31 | 939 | static int native_afu_activate_mode(struct cxl_afu *afu, int mode) |
f204e0b8 IM |
940 | { |
941 | if (!mode) | |
942 | return 0; | |
943 | if (!(mode & afu->modes_supported)) | |
944 | return -EINVAL; | |
945 | ||
0d400f77 | 946 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
947 | WARN(1, "Device link is down, refusing to activate!\n"); |
948 | return -EIO; | |
949 | } | |
950 | ||
f204e0b8 IM |
951 | if (mode == CXL_MODE_DIRECTED) |
952 | return activate_afu_directed(afu); | |
6f2ed3bf CL |
953 | if ((mode == CXL_MODE_DEDICATED) && |
954 | (afu->adapter->native->sl_ops->activate_dedicated_process)) | |
955 | return afu->adapter->native->sl_ops->activate_dedicated_process(afu); | |
f204e0b8 IM |
956 | |
957 | return -EINVAL; | |
958 | } | |
959 | ||
2b04cf31 FB |
960 | static int native_attach_process(struct cxl_context *ctx, bool kernel, |
961 | u64 wed, u64 amr) | |
f204e0b8 | 962 | { |
0d400f77 | 963 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
0b3f9c75 DA |
964 | WARN(1, "Device link is down, refusing to attach process!\n"); |
965 | return -EIO; | |
966 | } | |
967 | ||
f204e0b8 | 968 | ctx->kernel = kernel; |
6f2ed3bf CL |
969 | if ((ctx->afu->current_mode == CXL_MODE_DIRECTED) && |
970 | (ctx->afu->adapter->native->sl_ops->attach_afu_directed)) | |
971 | return ctx->afu->adapter->native->sl_ops->attach_afu_directed(ctx, wed, amr); | |
f204e0b8 | 972 | |
6f2ed3bf CL |
973 | if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) && |
974 | (ctx->afu->adapter->native->sl_ops->attach_dedicated_process)) | |
975 | return ctx->afu->adapter->native->sl_ops->attach_dedicated_process(ctx, wed, amr); | |
f204e0b8 IM |
976 | |
977 | return -EINVAL; | |
978 | } | |
979 | ||
980 | static inline int detach_process_native_dedicated(struct cxl_context *ctx) | |
981 | { | |
5e7823c9 IM |
982 | /* |
983 | * The CAIA section 2.1.1 indicates that we need to do an AFU reset to | |
984 | * stop the AFU in dedicated mode (we therefore do not make that | |
985 | * optional like we do in the afu directed path). It does not indicate | |
986 | * that we need to do an explicit disable (which should occur | |
987 | * implicitly as part of the reset) or purge, but we do these as well | |
988 | * to be on the safe side. | |
989 | * | |
990 | * Notably we used to have some issues with the disable sequence | |
991 | * (before the sequence was spelled out in the architecture) which is | |
992 | * why we were so heavy weight in the first place, however a bug was | |
993 | * discovered that had rendered the disable operation ineffective, so | |
994 | * it is conceivable that was the sole explanation for those | |
995 | * difficulties. Point is, we should be careful and do some regression | |
996 | * testing if we ever attempt to remove any part of this procedure. | |
997 | */ | |
5be587b1 | 998 | cxl_ops->afu_reset(ctx->afu); |
f204e0b8 IM |
999 | cxl_afu_disable(ctx->afu); |
1000 | cxl_psl_purge(ctx->afu); | |
1001 | return 0; | |
1002 | } | |
1003 | ||
292841b0 IM |
1004 | static void native_update_ivtes(struct cxl_context *ctx) |
1005 | { | |
1006 | if (ctx->afu->current_mode == CXL_MODE_DIRECTED) | |
1007 | return update_ivtes_directed(ctx); | |
6f2ed3bf CL |
1008 | if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) && |
1009 | (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)) | |
1010 | return ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx); | |
292841b0 IM |
1011 | WARN(1, "native_update_ivtes: Bad mode\n"); |
1012 | } | |
1013 | ||
f204e0b8 IM |
1014 | static inline int detach_process_native_afu_directed(struct cxl_context *ctx) |
1015 | { | |
1016 | if (!ctx->pe_inserted) | |
1017 | return 0; | |
1018 | if (terminate_process_element(ctx)) | |
1019 | return -1; | |
1020 | if (remove_process_element(ctx)) | |
1021 | return -1; | |
1022 | ||
1023 | return 0; | |
1024 | } | |
1025 | ||
2b04cf31 | 1026 | static int native_detach_process(struct cxl_context *ctx) |
f204e0b8 | 1027 | { |
9bcf28cd IM |
1028 | trace_cxl_detach(ctx); |
1029 | ||
f204e0b8 IM |
1030 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) |
1031 | return detach_process_native_dedicated(ctx); | |
1032 | ||
1033 | return detach_process_native_afu_directed(ctx); | |
1034 | } | |
1035 | ||
2b04cf31 | 1036 | static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info) |
f204e0b8 | 1037 | { |
0b3f9c75 DA |
1038 | /* If the adapter has gone away, we can't get any meaningful |
1039 | * information. | |
1040 | */ | |
0d400f77 | 1041 | if (!cxl_ops->link_ok(afu->adapter, afu)) |
0b3f9c75 DA |
1042 | return -EIO; |
1043 | ||
bc78b05b IM |
1044 | info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
1045 | info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); | |
d371edf5 CL |
1046 | if (cxl_is_power8()) |
1047 | info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An); | |
bc78b05b IM |
1048 | info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An); |
1049 | info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
444c4ba4 | 1050 | info->proc_handle = 0; |
f204e0b8 IM |
1051 | |
1052 | return 0; | |
1053 | } | |
1054 | ||
5f761c26 CL |
1055 | void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx) |
1056 | { | |
1057 | u64 fir1, fir2, serr; | |
1058 | ||
1059 | fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR1); | |
1060 | fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR2); | |
1061 | ||
1062 | dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1); | |
1063 | dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2); | |
1064 | if (ctx->afu->adapter->native->sl_ops->register_serr_irq) { | |
1065 | serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An); | |
1066 | cxl_afu_decode_psl_serr(ctx->afu, serr); | |
1067 | } | |
1068 | } | |
1069 | ||
f6ac63a5 | 1070 | void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx) |
d56d301b FB |
1071 | { |
1072 | u64 fir1, fir2, fir_slice, serr, afu_debug; | |
1073 | ||
1074 | fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1); | |
1075 | fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2); | |
1076 | fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An); | |
d56d301b FB |
1077 | afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An); |
1078 | ||
d56d301b FB |
1079 | dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1); |
1080 | dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2); | |
6d382616 FB |
1081 | if (ctx->afu->adapter->native->sl_ops->register_serr_irq) { |
1082 | serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An); | |
6e0c50f9 | 1083 | cxl_afu_decode_psl_serr(ctx->afu, serr); |
6d382616 | 1084 | } |
d56d301b FB |
1085 | dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); |
1086 | dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); | |
6d382616 FB |
1087 | } |
1088 | ||
1089 | static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx, | |
1090 | u64 dsisr, u64 errstat) | |
1091 | { | |
1092 | ||
1093 | dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat); | |
d56d301b | 1094 | |
6d382616 FB |
1095 | if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers) |
1096 | ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx); | |
1097 | ||
1098 | if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) { | |
1099 | dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n"); | |
1100 | ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter); | |
1101 | } | |
d56d301b | 1102 | |
5be587b1 | 1103 | return cxl_ops->ack_irq(ctx, 0, errstat); |
d56d301b FB |
1104 | } |
1105 | ||
5f761c26 CL |
1106 | static bool cxl_is_translation_fault(struct cxl_afu *afu, u64 dsisr) |
1107 | { | |
1108 | if ((cxl_is_psl8(afu)) && (dsisr & CXL_PSL_DSISR_TRANS)) | |
1109 | return true; | |
1110 | ||
1111 | if ((cxl_is_psl9(afu)) && (dsisr & CXL_PSL9_DSISR_An_TF)) | |
1112 | return true; | |
1113 | ||
1114 | return false; | |
1115 | } | |
1116 | ||
6f2ed3bf | 1117 | irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info) |
d56d301b | 1118 | { |
5f761c26 | 1119 | if (cxl_is_translation_fault(afu, irq_info->dsisr)) |
d56d301b FB |
1120 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); |
1121 | else | |
1122 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); | |
1123 | ||
1124 | return IRQ_HANDLED; | |
1125 | } | |
1126 | ||
2b04cf31 | 1127 | static irqreturn_t native_irq_multiplexed(int irq, void *data) |
d56d301b FB |
1128 | { |
1129 | struct cxl_afu *afu = data; | |
1130 | struct cxl_context *ctx; | |
1131 | struct cxl_irq_info irq_info; | |
abf051be | 1132 | u64 phreg = cxl_p2n_read(afu, CXL_PSL_PEHandle_An); |
6f2ed3bf | 1133 | int ph, ret = IRQ_HANDLED, res; |
abf051be VJ |
1134 | |
1135 | /* check if eeh kicked in while the interrupt was in flight */ | |
1136 | if (unlikely(phreg == ~0ULL)) { | |
1137 | dev_warn(&afu->dev, | |
1138 | "Ignoring slice interrupt(%d) due to fenced card", | |
1139 | irq); | |
1140 | return IRQ_HANDLED; | |
1141 | } | |
1142 | /* Mask the pe-handle from register value */ | |
1143 | ph = phreg & 0xffff; | |
6f2ed3bf CL |
1144 | if ((res = native_get_irq_info(afu, &irq_info))) { |
1145 | WARN(1, "Unable to get CXL IRQ Info: %i\n", res); | |
1146 | if (afu->adapter->native->sl_ops->fail_irq) | |
1147 | return afu->adapter->native->sl_ops->fail_irq(afu, &irq_info); | |
1148 | return ret; | |
d56d301b FB |
1149 | } |
1150 | ||
1151 | rcu_read_lock(); | |
1152 | ctx = idr_find(&afu->contexts_idr, ph); | |
1153 | if (ctx) { | |
6f2ed3bf CL |
1154 | if (afu->adapter->native->sl_ops->handle_interrupt) |
1155 | ret = afu->adapter->native->sl_ops->handle_interrupt(irq, ctx, &irq_info); | |
d56d301b FB |
1156 | rcu_read_unlock(); |
1157 | return ret; | |
1158 | } | |
1159 | rcu_read_unlock(); | |
1160 | ||
1161 | WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR" | |
1162 | " %016llx\n(Possible AFU HW issue - was a term/remove acked" | |
1163 | " with outstanding transactions?)\n", ph, irq_info.dsisr, | |
1164 | irq_info.dar); | |
6f2ed3bf CL |
1165 | if (afu->adapter->native->sl_ops->fail_irq) |
1166 | ret = afu->adapter->native->sl_ops->fail_irq(afu, &irq_info); | |
1167 | return ret; | |
d56d301b FB |
1168 | } |
1169 | ||
6fd40f19 | 1170 | static void native_irq_wait(struct cxl_context *ctx) |
2bc79ffc MN |
1171 | { |
1172 | u64 dsisr; | |
1173 | int timeout = 1000; | |
1174 | int ph; | |
1175 | ||
1176 | /* | |
1177 | * Wait until no further interrupts are presented by the PSL | |
1178 | * for this context. | |
1179 | */ | |
1180 | while (timeout--) { | |
1181 | ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff; | |
1182 | if (ph != ctx->pe) | |
1183 | return; | |
1184 | dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An); | |
d371edf5 CL |
1185 | if (cxl_is_psl8(ctx->afu) && |
1186 | ((dsisr & CXL_PSL_DSISR_PENDING) == 0)) | |
2bc79ffc | 1187 | return; |
5f761c26 CL |
1188 | if (cxl_is_psl9(ctx->afu) && |
1189 | ((dsisr & CXL_PSL9_DSISR_PENDING) == 0)) | |
1190 | return; | |
2bc79ffc MN |
1191 | /* |
1192 | * We are waiting for the workqueue to process our | |
1193 | * irq, so need to let that run here. | |
1194 | */ | |
1195 | msleep(1); | |
1196 | } | |
1197 | ||
1198 | dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i" | |
1199 | " DSISR %016llx!\n", ph, dsisr); | |
1200 | return; | |
1201 | } | |
1202 | ||
2b04cf31 | 1203 | static irqreturn_t native_slice_irq_err(int irq, void *data) |
d56d301b FB |
1204 | { |
1205 | struct cxl_afu *afu = data; | |
d371edf5 CL |
1206 | u64 errstat, serr, afu_error, dsisr; |
1207 | u64 fir_slice, afu_debug; | |
d56d301b | 1208 | |
6d382616 FB |
1209 | /* |
1210 | * slice err interrupt is only used with full PSL (no XSL) | |
1211 | */ | |
d56d301b | 1212 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); |
d56d301b | 1213 | errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); |
6e0c50f9 PB |
1214 | afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An); |
1215 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
1216 | cxl_afu_decode_psl_serr(afu, serr); | |
d371edf5 CL |
1217 | |
1218 | if (cxl_is_power8()) { | |
1219 | fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An); | |
1220 | afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An); | |
1221 | dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); | |
1222 | dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); | |
1223 | } | |
d56d301b | 1224 | dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat); |
6e0c50f9 PB |
1225 | dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error); |
1226 | dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr); | |
d56d301b FB |
1227 | |
1228 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); | |
1229 | ||
1230 | return IRQ_HANDLED; | |
1231 | } | |
1232 | ||
6d382616 FB |
1233 | void cxl_native_err_irq_dump_regs(struct cxl *adapter) |
1234 | { | |
1235 | u64 fir1, fir2; | |
1236 | ||
1237 | fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1); | |
1238 | fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2); | |
1239 | ||
1240 | dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2); | |
1241 | } | |
1242 | ||
2b04cf31 | 1243 | static irqreturn_t native_irq_err(int irq, void *data) |
d56d301b FB |
1244 | { |
1245 | struct cxl *adapter = data; | |
6d382616 | 1246 | u64 err_ivte; |
d56d301b FB |
1247 | |
1248 | WARN(1, "CXL ERROR interrupt %i\n", irq); | |
1249 | ||
1250 | err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE); | |
1251 | dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte); | |
1252 | ||
6d382616 FB |
1253 | if (adapter->native->sl_ops->debugfs_stop_trace) { |
1254 | dev_crit(&adapter->dev, "STOPPING CXL TRACE\n"); | |
1255 | adapter->native->sl_ops->debugfs_stop_trace(adapter); | |
1256 | } | |
d56d301b | 1257 | |
6d382616 FB |
1258 | if (adapter->native->sl_ops->err_irq_dump_registers) |
1259 | adapter->native->sl_ops->err_irq_dump_registers(adapter); | |
d56d301b FB |
1260 | |
1261 | return IRQ_HANDLED; | |
1262 | } | |
1263 | ||
2b04cf31 | 1264 | int cxl_native_register_psl_err_irq(struct cxl *adapter) |
d56d301b FB |
1265 | { |
1266 | int rc; | |
1267 | ||
1268 | adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", | |
1269 | dev_name(&adapter->dev)); | |
1270 | if (!adapter->irq_name) | |
1271 | return -ENOMEM; | |
1272 | ||
2b04cf31 | 1273 | if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter, |
cbffa3a5 CL |
1274 | &adapter->native->err_hwirq, |
1275 | &adapter->native->err_virq, | |
d56d301b FB |
1276 | adapter->irq_name))) { |
1277 | kfree(adapter->irq_name); | |
1278 | adapter->irq_name = NULL; | |
1279 | return rc; | |
1280 | } | |
1281 | ||
cbffa3a5 | 1282 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff); |
d56d301b FB |
1283 | |
1284 | return 0; | |
1285 | } | |
1286 | ||
2b04cf31 | 1287 | void cxl_native_release_psl_err_irq(struct cxl *adapter) |
d56d301b | 1288 | { |
cbffa3a5 | 1289 | if (adapter->native->err_virq != irq_find_mapping(NULL, adapter->native->err_hwirq)) |
d56d301b FB |
1290 | return; |
1291 | ||
1292 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000); | |
cbffa3a5 CL |
1293 | cxl_unmap_irq(adapter->native->err_virq, adapter); |
1294 | cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq); | |
d56d301b FB |
1295 | kfree(adapter->irq_name); |
1296 | } | |
1297 | ||
2b04cf31 | 1298 | int cxl_native_register_serr_irq(struct cxl_afu *afu) |
d56d301b FB |
1299 | { |
1300 | u64 serr; | |
1301 | int rc; | |
1302 | ||
1303 | afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", | |
1304 | dev_name(&afu->dev)); | |
1305 | if (!afu->err_irq_name) | |
1306 | return -ENOMEM; | |
1307 | ||
2b04cf31 | 1308 | if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu, |
d56d301b FB |
1309 | &afu->serr_hwirq, |
1310 | &afu->serr_virq, afu->err_irq_name))) { | |
1311 | kfree(afu->err_irq_name); | |
1312 | afu->err_irq_name = NULL; | |
1313 | return rc; | |
1314 | } | |
1315 | ||
1316 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
d371edf5 CL |
1317 | if (cxl_is_power8()) |
1318 | serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff); | |
5f761c26 CL |
1319 | if (cxl_is_power9()) { |
1320 | /* | |
1321 | * By default, all errors are masked. So don't set all masks. | |
1322 | * Slice errors will be transfered. | |
1323 | */ | |
1324 | serr = (serr & ~0xff0000007fffffffULL) | (afu->serr_hwirq & 0xffff); | |
1325 | } | |
d56d301b FB |
1326 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); |
1327 | ||
1328 | return 0; | |
1329 | } | |
1330 | ||
2b04cf31 | 1331 | void cxl_native_release_serr_irq(struct cxl_afu *afu) |
d56d301b FB |
1332 | { |
1333 | if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq)) | |
1334 | return; | |
1335 | ||
1336 | cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000); | |
1337 | cxl_unmap_irq(afu->serr_virq, afu); | |
5be587b1 | 1338 | cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq); |
d56d301b FB |
1339 | kfree(afu->err_irq_name); |
1340 | } | |
1341 | ||
2b04cf31 | 1342 | int cxl_native_register_psl_irq(struct cxl_afu *afu) |
d56d301b FB |
1343 | { |
1344 | int rc; | |
1345 | ||
1346 | afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s", | |
1347 | dev_name(&afu->dev)); | |
1348 | if (!afu->psl_irq_name) | |
1349 | return -ENOMEM; | |
1350 | ||
cbffa3a5 CL |
1351 | if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed, |
1352 | afu, &afu->native->psl_hwirq, &afu->native->psl_virq, | |
d56d301b FB |
1353 | afu->psl_irq_name))) { |
1354 | kfree(afu->psl_irq_name); | |
1355 | afu->psl_irq_name = NULL; | |
1356 | } | |
1357 | return rc; | |
1358 | } | |
1359 | ||
2b04cf31 | 1360 | void cxl_native_release_psl_irq(struct cxl_afu *afu) |
d56d301b | 1361 | { |
cbffa3a5 | 1362 | if (afu->native->psl_virq != irq_find_mapping(NULL, afu->native->psl_hwirq)) |
d56d301b FB |
1363 | return; |
1364 | ||
cbffa3a5 CL |
1365 | cxl_unmap_irq(afu->native->psl_virq, afu); |
1366 | cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq); | |
d56d301b FB |
1367 | kfree(afu->psl_irq_name); |
1368 | } | |
1369 | ||
f204e0b8 IM |
1370 | static void recover_psl_err(struct cxl_afu *afu, u64 errstat) |
1371 | { | |
1372 | u64 dsisr; | |
1373 | ||
de369538 | 1374 | pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat); |
f204e0b8 IM |
1375 | |
1376 | /* Clear PSL_DSISR[PE] */ | |
1377 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
1378 | cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE); | |
1379 | ||
1380 | /* Write 1s to clear error status bits */ | |
1381 | cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat); | |
1382 | } | |
1383 | ||
2b04cf31 | 1384 | static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask) |
f204e0b8 | 1385 | { |
9bcf28cd | 1386 | trace_cxl_psl_irq_ack(ctx, tfc); |
f204e0b8 IM |
1387 | if (tfc) |
1388 | cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc); | |
1389 | if (psl_reset_mask) | |
1390 | recover_psl_err(ctx->afu, psl_reset_mask); | |
1391 | ||
1392 | return 0; | |
1393 | } | |
1394 | ||
1395 | int cxl_check_error(struct cxl_afu *afu) | |
1396 | { | |
1397 | return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL); | |
1398 | } | |
d56d301b | 1399 | |
4752876c CL |
1400 | static bool native_support_attributes(const char *attr_name, |
1401 | enum cxl_attrs type) | |
1402 | { | |
1403 | return true; | |
1404 | } | |
1405 | ||
2b04cf31 | 1406 | static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out) |
d56d301b | 1407 | { |
0d400f77 | 1408 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
5be587b1 FB |
1409 | return -EIO; |
1410 | if (unlikely(off >= afu->crs_len)) | |
1411 | return -ERANGE; | |
cbffa3a5 | 1412 | *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset + |
5be587b1 FB |
1413 | (cr * afu->crs_len) + off); |
1414 | return 0; | |
d56d301b FB |
1415 | } |
1416 | ||
2b04cf31 | 1417 | static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out) |
d56d301b | 1418 | { |
0d400f77 | 1419 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
5be587b1 FB |
1420 | return -EIO; |
1421 | if (unlikely(off >= afu->crs_len)) | |
1422 | return -ERANGE; | |
cbffa3a5 | 1423 | *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset + |
5be587b1 FB |
1424 | (cr * afu->crs_len) + off); |
1425 | return 0; | |
d56d301b FB |
1426 | } |
1427 | ||
2b04cf31 | 1428 | static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out) |
d56d301b FB |
1429 | { |
1430 | u64 aligned_off = off & ~0x3L; | |
1431 | u32 val; | |
5be587b1 | 1432 | int rc; |
d56d301b | 1433 | |
2b04cf31 | 1434 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
5be587b1 FB |
1435 | if (!rc) |
1436 | *out = (val >> ((off & 0x3) * 8)) & 0xffff; | |
1437 | return rc; | |
d56d301b FB |
1438 | } |
1439 | ||
2b04cf31 | 1440 | static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out) |
d56d301b FB |
1441 | { |
1442 | u64 aligned_off = off & ~0x3L; | |
1443 | u32 val; | |
5be587b1 | 1444 | int rc; |
d56d301b | 1445 | |
2b04cf31 | 1446 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
5be587b1 FB |
1447 | if (!rc) |
1448 | *out = (val >> ((off & 0x3) * 8)) & 0xff; | |
1449 | return rc; | |
d56d301b | 1450 | } |
5be587b1 | 1451 | |
d601ea91 FB |
1452 | static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in) |
1453 | { | |
0d400f77 | 1454 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
d601ea91 FB |
1455 | return -EIO; |
1456 | if (unlikely(off >= afu->crs_len)) | |
1457 | return -ERANGE; | |
1458 | out_le32(afu->native->afu_desc_mmio + afu->crs_offset + | |
1459 | (cr * afu->crs_len) + off, in); | |
1460 | return 0; | |
1461 | } | |
1462 | ||
1463 | static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in) | |
1464 | { | |
1465 | u64 aligned_off = off & ~0x3L; | |
1466 | u32 val32, mask, shift; | |
1467 | int rc; | |
1468 | ||
1469 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); | |
1470 | if (rc) | |
1471 | return rc; | |
1472 | shift = (off & 0x3) * 8; | |
1473 | WARN_ON(shift == 24); | |
1474 | mask = 0xffff << shift; | |
1475 | val32 = (val32 & ~mask) | (in << shift); | |
1476 | ||
1477 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); | |
1478 | return rc; | |
1479 | } | |
1480 | ||
1481 | static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in) | |
1482 | { | |
1483 | u64 aligned_off = off & ~0x3L; | |
1484 | u32 val32, mask, shift; | |
1485 | int rc; | |
1486 | ||
1487 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); | |
1488 | if (rc) | |
1489 | return rc; | |
1490 | shift = (off & 0x3) * 8; | |
1491 | mask = 0xff << shift; | |
1492 | val32 = (val32 & ~mask) | (in << shift); | |
1493 | ||
1494 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); | |
1495 | return rc; | |
1496 | } | |
1497 | ||
5be587b1 FB |
1498 | const struct cxl_backend_ops cxl_native_ops = { |
1499 | .module = THIS_MODULE, | |
2b04cf31 FB |
1500 | .adapter_reset = cxl_pci_reset, |
1501 | .alloc_one_irq = cxl_pci_alloc_one_irq, | |
1502 | .release_one_irq = cxl_pci_release_one_irq, | |
1503 | .alloc_irq_ranges = cxl_pci_alloc_irq_ranges, | |
1504 | .release_irq_ranges = cxl_pci_release_irq_ranges, | |
1505 | .setup_irq = cxl_pci_setup_irq, | |
1506 | .handle_psl_slice_error = native_handle_psl_slice_error, | |
5be587b1 | 1507 | .psl_interrupt = NULL, |
2b04cf31 | 1508 | .ack_irq = native_ack_irq, |
2bc79ffc | 1509 | .irq_wait = native_irq_wait, |
2b04cf31 FB |
1510 | .attach_process = native_attach_process, |
1511 | .detach_process = native_detach_process, | |
292841b0 | 1512 | .update_ivtes = native_update_ivtes, |
4752876c | 1513 | .support_attributes = native_support_attributes, |
5be587b1 | 1514 | .link_ok = cxl_adapter_link_ok, |
2b04cf31 FB |
1515 | .release_afu = cxl_pci_release_afu, |
1516 | .afu_read_err_buffer = cxl_pci_afu_read_err_buffer, | |
1517 | .afu_check_and_enable = native_afu_check_and_enable, | |
1518 | .afu_activate_mode = native_afu_activate_mode, | |
1519 | .afu_deactivate_mode = native_afu_deactivate_mode, | |
1520 | .afu_reset = native_afu_reset, | |
1521 | .afu_cr_read8 = native_afu_cr_read8, | |
1522 | .afu_cr_read16 = native_afu_cr_read16, | |
1523 | .afu_cr_read32 = native_afu_cr_read32, | |
1524 | .afu_cr_read64 = native_afu_cr_read64, | |
d601ea91 FB |
1525 | .afu_cr_write8 = native_afu_cr_write8, |
1526 | .afu_cr_write16 = native_afu_cr_write16, | |
1527 | .afu_cr_write32 = native_afu_cr_write32, | |
1528 | .read_adapter_vpd = cxl_pci_read_adapter_vpd, | |
5be587b1 | 1529 | }; |