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Commit | Line | Data |
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f204e0b8 IM |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/spinlock.h> | |
11 | #include <linux/sched.h> | |
e6017571 | 12 | #include <linux/sched/clock.h> |
f204e0b8 | 13 | #include <linux/slab.h> |
f204e0b8 IM |
14 | #include <linux/mutex.h> |
15 | #include <linux/mm.h> | |
16 | #include <linux/uaccess.h> | |
2bc79ffc | 17 | #include <linux/delay.h> |
f204e0b8 | 18 | #include <asm/synch.h> |
ec249dd8 | 19 | #include <misc/cxl-base.h> |
f204e0b8 IM |
20 | |
21 | #include "cxl.h" | |
9bcf28cd | 22 | #include "trace.h" |
f204e0b8 | 23 | |
5e7823c9 | 24 | static int afu_control(struct cxl_afu *afu, u64 command, u64 clear, |
f204e0b8 IM |
25 | u64 result, u64 mask, bool enabled) |
26 | { | |
5e7823c9 | 27 | u64 AFU_Cntl; |
f204e0b8 | 28 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
9bcf28cd | 29 | int rc = 0; |
f204e0b8 IM |
30 | |
31 | spin_lock(&afu->afu_cntl_lock); | |
32 | pr_devel("AFU command starting: %llx\n", command); | |
33 | ||
9bcf28cd IM |
34 | trace_cxl_afu_ctrl(afu, command); |
35 | ||
5e7823c9 IM |
36 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); |
37 | cxl_p2n_write(afu, CXL_AFU_Cntl_An, (AFU_Cntl & ~clear) | command); | |
f204e0b8 IM |
38 | |
39 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
40 | while ((AFU_Cntl & mask) != result) { | |
41 | if (time_after_eq(jiffies, timeout)) { | |
42 | dev_warn(&afu->dev, "WARNING: AFU control timed out!\n"); | |
9bcf28cd IM |
43 | rc = -EBUSY; |
44 | goto out; | |
f204e0b8 | 45 | } |
0b3f9c75 | 46 | |
0d400f77 | 47 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
48 | afu->enabled = enabled; |
49 | rc = -EIO; | |
50 | goto out; | |
51 | } | |
52 | ||
de369538 | 53 | pr_devel_ratelimited("AFU control... (0x%016llx)\n", |
f204e0b8 IM |
54 | AFU_Cntl | command); |
55 | cpu_relax(); | |
56 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
3382a622 | 57 | } |
2a4f667a IM |
58 | |
59 | if (AFU_Cntl & CXL_AFU_Cntl_An_RA) { | |
60 | /* | |
61 | * Workaround for a bug in the XSL used in the Mellanox CX4 | |
62 | * that fails to clear the RA bit after an AFU reset, | |
63 | * preventing subsequent AFU resets from working. | |
64 | */ | |
65 | cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl & ~CXL_AFU_Cntl_An_RA); | |
66 | } | |
67 | ||
f204e0b8 IM |
68 | pr_devel("AFU command complete: %llx\n", command); |
69 | afu->enabled = enabled; | |
9bcf28cd IM |
70 | out: |
71 | trace_cxl_afu_ctrl_done(afu, command, rc); | |
f204e0b8 IM |
72 | spin_unlock(&afu->afu_cntl_lock); |
73 | ||
9bcf28cd | 74 | return rc; |
f204e0b8 IM |
75 | } |
76 | ||
77 | static int afu_enable(struct cxl_afu *afu) | |
78 | { | |
79 | pr_devel("AFU enable request\n"); | |
80 | ||
5e7823c9 | 81 | return afu_control(afu, CXL_AFU_Cntl_An_E, 0, |
f204e0b8 IM |
82 | CXL_AFU_Cntl_An_ES_Enabled, |
83 | CXL_AFU_Cntl_An_ES_MASK, true); | |
84 | } | |
85 | ||
86 | int cxl_afu_disable(struct cxl_afu *afu) | |
87 | { | |
88 | pr_devel("AFU disable request\n"); | |
89 | ||
5e7823c9 IM |
90 | return afu_control(afu, 0, CXL_AFU_Cntl_An_E, |
91 | CXL_AFU_Cntl_An_ES_Disabled, | |
f204e0b8 IM |
92 | CXL_AFU_Cntl_An_ES_MASK, false); |
93 | } | |
94 | ||
95 | /* This will disable as well as reset */ | |
2b04cf31 | 96 | static int native_afu_reset(struct cxl_afu *afu) |
f204e0b8 IM |
97 | { |
98 | pr_devel("AFU reset request\n"); | |
99 | ||
5e7823c9 | 100 | return afu_control(afu, CXL_AFU_Cntl_An_RA, 0, |
f204e0b8 IM |
101 | CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled, |
102 | CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK, | |
103 | false); | |
104 | } | |
105 | ||
2b04cf31 | 106 | static int native_afu_check_and_enable(struct cxl_afu *afu) |
f204e0b8 | 107 | { |
0d400f77 | 108 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
109 | WARN(1, "Refusing to enable afu while link down!\n"); |
110 | return -EIO; | |
111 | } | |
f204e0b8 IM |
112 | if (afu->enabled) |
113 | return 0; | |
114 | return afu_enable(afu); | |
115 | } | |
116 | ||
117 | int cxl_psl_purge(struct cxl_afu *afu) | |
118 | { | |
119 | u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
120 | u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
121 | u64 dsisr, dar; | |
122 | u64 start, end; | |
123 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
9bcf28cd IM |
124 | int rc = 0; |
125 | ||
126 | trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc); | |
f204e0b8 IM |
127 | |
128 | pr_devel("PSL purge request\n"); | |
129 | ||
0d400f77 | 130 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
131 | dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n"); |
132 | rc = -EIO; | |
133 | goto out; | |
134 | } | |
135 | ||
f204e0b8 IM |
136 | if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { |
137 | WARN(1, "psl_purge request while AFU not disabled!\n"); | |
138 | cxl_afu_disable(afu); | |
139 | } | |
140 | ||
141 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, | |
142 | PSL_CNTL | CXL_PSL_SCNTL_An_Pc); | |
143 | start = local_clock(); | |
144 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
145 | while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK) | |
146 | == CXL_PSL_SCNTL_An_Ps_Pending) { | |
147 | if (time_after_eq(jiffies, timeout)) { | |
148 | dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n"); | |
9bcf28cd IM |
149 | rc = -EBUSY; |
150 | goto out; | |
f204e0b8 | 151 | } |
0d400f77 | 152 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
153 | rc = -EIO; |
154 | goto out; | |
155 | } | |
156 | ||
f204e0b8 | 157 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
de369538 | 158 | pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr); |
f204e0b8 IM |
159 | if (dsisr & CXL_PSL_DSISR_TRANS) { |
160 | dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); | |
de369538 | 161 | dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar); |
f204e0b8 IM |
162 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); |
163 | } else if (dsisr) { | |
de369538 | 164 | dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr); |
f204e0b8 IM |
165 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); |
166 | } else { | |
167 | cpu_relax(); | |
168 | } | |
169 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
3382a622 | 170 | } |
f204e0b8 IM |
171 | end = local_clock(); |
172 | pr_devel("PSL purged in %lld ns\n", end - start); | |
173 | ||
174 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, | |
175 | PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc); | |
9bcf28cd IM |
176 | out: |
177 | trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc); | |
178 | return rc; | |
f204e0b8 IM |
179 | } |
180 | ||
181 | static int spa_max_procs(int spa_size) | |
182 | { | |
183 | /* | |
184 | * From the CAIA: | |
185 | * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255 | |
186 | * Most of that junk is really just an overly-complicated way of saying | |
187 | * the last 256 bytes are __aligned(128), so it's really: | |
188 | * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255 | |
189 | * and | |
190 | * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1 | |
191 | * so | |
192 | * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256 | |
193 | * Ignore the alignment (which is safe in this case as long as we are | |
194 | * careful with our rounding) and solve for n: | |
195 | */ | |
196 | return ((spa_size / 8) - 96) / 17; | |
197 | } | |
198 | ||
05155772 | 199 | int cxl_alloc_spa(struct cxl_afu *afu) |
f204e0b8 | 200 | { |
895a7980 IM |
201 | unsigned spa_size; |
202 | ||
f204e0b8 | 203 | /* Work out how many pages to allocate */ |
2224b671 | 204 | afu->native->spa_order = -1; |
f204e0b8 | 205 | do { |
cbffa3a5 | 206 | afu->native->spa_order++; |
895a7980 IM |
207 | spa_size = (1 << afu->native->spa_order) * PAGE_SIZE; |
208 | ||
209 | if (spa_size > 0x100000) { | |
210 | dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n", | |
211 | afu->native->spa_max_procs, afu->native->spa_size); | |
212 | afu->num_procs = afu->native->spa_max_procs; | |
213 | break; | |
214 | } | |
215 | ||
216 | afu->native->spa_size = spa_size; | |
cbffa3a5 CL |
217 | afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size); |
218 | } while (afu->native->spa_max_procs < afu->num_procs); | |
f204e0b8 | 219 | |
cbffa3a5 CL |
220 | if (!(afu->native->spa = (struct cxl_process_element *) |
221 | __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) { | |
f204e0b8 IM |
222 | pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n"); |
223 | return -ENOMEM; | |
224 | } | |
225 | pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n", | |
cbffa3a5 | 226 | 1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs); |
f204e0b8 | 227 | |
05155772 DA |
228 | return 0; |
229 | } | |
230 | ||
231 | static void attach_spa(struct cxl_afu *afu) | |
232 | { | |
233 | u64 spap; | |
234 | ||
cbffa3a5 CL |
235 | afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa + |
236 | ((afu->native->spa_max_procs + 3) * 128)); | |
f204e0b8 | 237 | |
cbffa3a5 CL |
238 | spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr; |
239 | spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size; | |
f204e0b8 | 240 | spap |= CXL_PSL_SPAP_V; |
cbffa3a5 CL |
241 | pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", |
242 | afu->native->spa, afu->native->spa_max_procs, | |
243 | afu->native->sw_command_status, spap); | |
f204e0b8 | 244 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap); |
f204e0b8 IM |
245 | } |
246 | ||
05155772 | 247 | static inline void detach_spa(struct cxl_afu *afu) |
f204e0b8 | 248 | { |
db7933f3 | 249 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); |
05155772 DA |
250 | } |
251 | ||
252 | void cxl_release_spa(struct cxl_afu *afu) | |
253 | { | |
cbffa3a5 CL |
254 | if (afu->native->spa) { |
255 | free_pages((unsigned long) afu->native->spa, | |
256 | afu->native->spa_order); | |
257 | afu->native->spa = NULL; | |
05155772 | 258 | } |
f204e0b8 IM |
259 | } |
260 | ||
261 | int cxl_tlb_slb_invalidate(struct cxl *adapter) | |
262 | { | |
263 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
264 | ||
265 | pr_devel("CXL adapter wide TLBIA & SLBIA\n"); | |
266 | ||
267 | cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A); | |
268 | ||
269 | cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL); | |
270 | while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) { | |
271 | if (time_after_eq(jiffies, timeout)) { | |
272 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n"); | |
273 | return -EBUSY; | |
274 | } | |
0d400f77 | 275 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 276 | return -EIO; |
f204e0b8 IM |
277 | cpu_relax(); |
278 | } | |
279 | ||
280 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL); | |
281 | while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) { | |
282 | if (time_after_eq(jiffies, timeout)) { | |
283 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n"); | |
284 | return -EBUSY; | |
285 | } | |
0d400f77 | 286 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 287 | return -EIO; |
f204e0b8 IM |
288 | cpu_relax(); |
289 | } | |
290 | return 0; | |
291 | } | |
292 | ||
aaa2245e FB |
293 | int cxl_data_cache_flush(struct cxl *adapter) |
294 | { | |
295 | u64 reg; | |
296 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
297 | ||
298 | pr_devel("Flushing data cache\n"); | |
299 | ||
300 | reg = cxl_p1_read(adapter, CXL_PSL_Control); | |
301 | reg |= CXL_PSL_Control_Fr; | |
302 | cxl_p1_write(adapter, CXL_PSL_Control, reg); | |
303 | ||
304 | reg = cxl_p1_read(adapter, CXL_PSL_Control); | |
305 | while ((reg & CXL_PSL_Control_Fs_MASK) != CXL_PSL_Control_Fs_Complete) { | |
306 | if (time_after_eq(jiffies, timeout)) { | |
307 | dev_warn(&adapter->dev, "WARNING: cache flush timed out!\n"); | |
308 | return -EBUSY; | |
309 | } | |
310 | ||
311 | if (!cxl_ops->link_ok(adapter, NULL)) { | |
312 | dev_warn(&adapter->dev, "WARNING: link down when flushing cache\n"); | |
313 | return -EIO; | |
314 | } | |
315 | cpu_relax(); | |
316 | reg = cxl_p1_read(adapter, CXL_PSL_Control); | |
317 | } | |
318 | ||
319 | reg &= ~CXL_PSL_Control_Fr; | |
320 | cxl_p1_write(adapter, CXL_PSL_Control, reg); | |
321 | return 0; | |
322 | } | |
323 | ||
f204e0b8 IM |
324 | static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1) |
325 | { | |
326 | int rc; | |
327 | ||
328 | /* 1. Disable SSTP by writing 0 to SSTP1[V] */ | |
329 | cxl_p2n_write(afu, CXL_SSTP1_An, 0); | |
330 | ||
331 | /* 2. Invalidate all SLB entries */ | |
332 | if ((rc = cxl_afu_slbia(afu))) | |
333 | return rc; | |
334 | ||
335 | /* 3. Set SSTP0_An */ | |
336 | cxl_p2n_write(afu, CXL_SSTP0_An, sstp0); | |
337 | ||
338 | /* 4. Set SSTP1_An */ | |
339 | cxl_p2n_write(afu, CXL_SSTP1_An, sstp1); | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
344 | /* Using per slice version may improve performance here. (ie. SLBIA_An) */ | |
345 | static void slb_invalid(struct cxl_context *ctx) | |
346 | { | |
347 | struct cxl *adapter = ctx->afu->adapter; | |
348 | u64 slbia; | |
349 | ||
cbffa3a5 | 350 | WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex)); |
f204e0b8 IM |
351 | |
352 | cxl_p1_write(adapter, CXL_PSL_LBISEL, | |
353 | ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) | | |
354 | be32_to_cpu(ctx->elem->lpid)); | |
355 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID); | |
356 | ||
357 | while (1) { | |
0d400f77 | 358 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 359 | break; |
f204e0b8 IM |
360 | slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA); |
361 | if (!(slbia & CXL_TLB_SLB_P)) | |
362 | break; | |
363 | cpu_relax(); | |
364 | } | |
365 | } | |
366 | ||
367 | static int do_process_element_cmd(struct cxl_context *ctx, | |
368 | u64 cmd, u64 pe_state) | |
369 | { | |
370 | u64 state; | |
a98e6e9f | 371 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
9bcf28cd IM |
372 | int rc = 0; |
373 | ||
374 | trace_cxl_llcmd(ctx, cmd); | |
f204e0b8 IM |
375 | |
376 | WARN_ON(!ctx->afu->enabled); | |
377 | ||
378 | ctx->elem->software_state = cpu_to_be32(pe_state); | |
379 | smp_wmb(); | |
cbffa3a5 | 380 | *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe); |
f204e0b8 IM |
381 | smp_mb(); |
382 | cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe); | |
383 | while (1) { | |
a98e6e9f IM |
384 | if (time_after_eq(jiffies, timeout)) { |
385 | dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n"); | |
9bcf28cd IM |
386 | rc = -EBUSY; |
387 | goto out; | |
a98e6e9f | 388 | } |
0d400f77 | 389 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
0b3f9c75 DA |
390 | dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n"); |
391 | rc = -EIO; | |
392 | goto out; | |
393 | } | |
cbffa3a5 | 394 | state = be64_to_cpup(ctx->afu->native->sw_command_status); |
f204e0b8 IM |
395 | if (state == ~0ULL) { |
396 | pr_err("cxl: Error adding process element to AFU\n"); | |
9bcf28cd IM |
397 | rc = -1; |
398 | goto out; | |
f204e0b8 IM |
399 | } |
400 | if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) == | |
401 | (cmd | (cmd >> 16) | ctx->pe)) | |
402 | break; | |
403 | /* | |
404 | * The command won't finish in the PSL if there are | |
405 | * outstanding DSIs. Hence we need to yield here in | |
406 | * case there are outstanding DSIs that we need to | |
407 | * service. Tuning possiblity: we could wait for a | |
408 | * while before sched | |
409 | */ | |
410 | schedule(); | |
411 | ||
412 | } | |
9bcf28cd IM |
413 | out: |
414 | trace_cxl_llcmd_done(ctx, cmd, rc); | |
415 | return rc; | |
f204e0b8 IM |
416 | } |
417 | ||
418 | static int add_process_element(struct cxl_context *ctx) | |
419 | { | |
420 | int rc = 0; | |
421 | ||
cbffa3a5 | 422 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
423 | pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe); |
424 | if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V))) | |
425 | ctx->pe_inserted = true; | |
426 | pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 427 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
428 | return rc; |
429 | } | |
430 | ||
431 | static int terminate_process_element(struct cxl_context *ctx) | |
432 | { | |
433 | int rc = 0; | |
434 | ||
435 | /* fast path terminate if it's already invalid */ | |
436 | if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V))) | |
437 | return rc; | |
438 | ||
cbffa3a5 | 439 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 | 440 | pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe); |
0b3f9c75 DA |
441 | /* We could be asked to terminate when the hw is down. That |
442 | * should always succeed: it's not running if the hw has gone | |
443 | * away and is being reset. | |
444 | */ | |
0d400f77 | 445 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
0b3f9c75 DA |
446 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE, |
447 | CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T); | |
f204e0b8 IM |
448 | ctx->elem->software_state = 0; /* Remove Valid bit */ |
449 | pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 450 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
451 | return rc; |
452 | } | |
453 | ||
454 | static int remove_process_element(struct cxl_context *ctx) | |
455 | { | |
456 | int rc = 0; | |
457 | ||
cbffa3a5 | 458 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 | 459 | pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe); |
0b3f9c75 DA |
460 | |
461 | /* We could be asked to remove when the hw is down. Again, if | |
462 | * the hw is down, the PE is gone, so we succeed. | |
463 | */ | |
0d400f77 | 464 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
0b3f9c75 DA |
465 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0); |
466 | ||
467 | if (!rc) | |
f204e0b8 IM |
468 | ctx->pe_inserted = false; |
469 | slb_invalid(ctx); | |
470 | pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 471 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
472 | |
473 | return rc; | |
474 | } | |
475 | ||
1a1a94b8 | 476 | void cxl_assign_psn_space(struct cxl_context *ctx) |
f204e0b8 IM |
477 | { |
478 | if (!ctx->afu->pp_size || ctx->master) { | |
479 | ctx->psn_phys = ctx->afu->psn_phys; | |
480 | ctx->psn_size = ctx->afu->adapter->ps_size; | |
481 | } else { | |
482 | ctx->psn_phys = ctx->afu->psn_phys + | |
cbffa3a5 | 483 | (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe); |
f204e0b8 IM |
484 | ctx->psn_size = ctx->afu->pp_size; |
485 | } | |
486 | } | |
487 | ||
488 | static int activate_afu_directed(struct cxl_afu *afu) | |
489 | { | |
490 | int rc; | |
491 | ||
492 | dev_info(&afu->dev, "Activating AFU directed mode\n"); | |
493 | ||
4108efb0 | 494 | afu->num_procs = afu->max_procs_virtualised; |
cbffa3a5 | 495 | if (afu->native->spa == NULL) { |
05155772 DA |
496 | if (cxl_alloc_spa(afu)) |
497 | return -ENOMEM; | |
498 | } | |
499 | attach_spa(afu); | |
f204e0b8 IM |
500 | |
501 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU); | |
502 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); | |
503 | cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L); | |
504 | ||
505 | afu->current_mode = CXL_MODE_DIRECTED; | |
f204e0b8 IM |
506 | |
507 | if ((rc = cxl_chardev_m_afu_add(afu))) | |
508 | return rc; | |
509 | ||
510 | if ((rc = cxl_sysfs_afu_m_add(afu))) | |
511 | goto err; | |
512 | ||
513 | if ((rc = cxl_chardev_s_afu_add(afu))) | |
514 | goto err1; | |
515 | ||
516 | return 0; | |
517 | err1: | |
518 | cxl_sysfs_afu_m_remove(afu); | |
519 | err: | |
520 | cxl_chardev_afu_remove(afu); | |
521 | return rc; | |
522 | } | |
523 | ||
524 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
525 | #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE) | |
526 | #else | |
527 | #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE)) | |
528 | #endif | |
529 | ||
2f663527 MN |
530 | static u64 calculate_sr(struct cxl_context *ctx) |
531 | { | |
532 | u64 sr = 0; | |
533 | ||
e606e035 | 534 | set_endian(sr); |
2f663527 MN |
535 | if (ctx->master) |
536 | sr |= CXL_PSL_SR_An_MP; | |
537 | if (mfspr(SPRN_LPCR) & LPCR_TC) | |
538 | sr |= CXL_PSL_SR_An_TC; | |
539 | if (ctx->kernel) { | |
7a0d85d3 IM |
540 | if (!ctx->real_mode) |
541 | sr |= CXL_PSL_SR_An_R; | |
542 | sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV; | |
2f663527 MN |
543 | } else { |
544 | sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; | |
2f663527 MN |
545 | sr &= ~(CXL_PSL_SR_An_HV); |
546 | if (!test_tsk_thread_flag(current, TIF_32BIT)) | |
547 | sr |= CXL_PSL_SR_An_SF; | |
548 | } | |
549 | return sr; | |
550 | } | |
551 | ||
292841b0 IM |
552 | static void update_ivtes_directed(struct cxl_context *ctx) |
553 | { | |
554 | bool need_update = (ctx->status == STARTED); | |
555 | int r; | |
556 | ||
557 | if (need_update) { | |
558 | WARN_ON(terminate_process_element(ctx)); | |
559 | WARN_ON(remove_process_element(ctx)); | |
560 | } | |
561 | ||
562 | for (r = 0; r < CXL_IRQ_RANGES; r++) { | |
563 | ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]); | |
564 | ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]); | |
565 | } | |
566 | ||
567 | /* | |
568 | * Theoretically we could use the update llcmd, instead of a | |
569 | * terminate/remove/add (or if an atomic update was required we could | |
570 | * do a suspend/update/resume), however it seems there might be issues | |
571 | * with the update llcmd on some cards (including those using an XSL on | |
572 | * an ASIC) so for now it's safest to go with the commands that are | |
573 | * known to work. In the future if we come across a situation where the | |
574 | * card may be performing transactions using the same PE while we are | |
575 | * doing this update we might need to revisit this. | |
576 | */ | |
577 | if (need_update) | |
578 | WARN_ON(add_process_element(ctx)); | |
579 | } | |
580 | ||
f204e0b8 IM |
581 | static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr) |
582 | { | |
2f663527 | 583 | u32 pid; |
292841b0 | 584 | int result; |
f204e0b8 | 585 | |
1a1a94b8 | 586 | cxl_assign_psn_space(ctx); |
f204e0b8 IM |
587 | |
588 | ctx->elem->ctxtime = 0; /* disable */ | |
589 | ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID)); | |
590 | ctx->elem->haurp = 0; /* disable */ | |
591 | ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1)); | |
592 | ||
2f663527 MN |
593 | pid = current->pid; |
594 | if (ctx->kernel) | |
595 | pid = 0; | |
f204e0b8 | 596 | ctx->elem->common.tid = 0; |
2f663527 MN |
597 | ctx->elem->common.pid = cpu_to_be32(pid); |
598 | ||
599 | ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); | |
f204e0b8 IM |
600 | |
601 | ctx->elem->common.csrp = 0; /* disable */ | |
602 | ctx->elem->common.aurp0 = 0; /* disable */ | |
603 | ctx->elem->common.aurp1 = 0; /* disable */ | |
604 | ||
605 | cxl_prefault(ctx, wed); | |
606 | ||
607 | ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0); | |
608 | ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1); | |
609 | ||
3c206fa7 IM |
610 | /* |
611 | * Ensure we have the multiplexed PSL interrupt set up to take faults | |
612 | * for kernel contexts that may not have allocated any AFU IRQs at all: | |
613 | */ | |
614 | if (ctx->irqs.range[0] == 0) { | |
615 | ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq; | |
616 | ctx->irqs.range[0] = 1; | |
617 | } | |
618 | ||
292841b0 | 619 | update_ivtes_directed(ctx); |
f204e0b8 IM |
620 | |
621 | ctx->elem->common.amr = cpu_to_be64(amr); | |
622 | ctx->elem->common.wed = cpu_to_be64(wed); | |
623 | ||
624 | /* first guy needs to enable */ | |
5be587b1 | 625 | if ((result = cxl_ops->afu_check_and_enable(ctx->afu))) |
f204e0b8 IM |
626 | return result; |
627 | ||
368857c1 | 628 | return add_process_element(ctx); |
f204e0b8 IM |
629 | } |
630 | ||
631 | static int deactivate_afu_directed(struct cxl_afu *afu) | |
632 | { | |
633 | dev_info(&afu->dev, "Deactivating AFU directed mode\n"); | |
634 | ||
635 | afu->current_mode = 0; | |
636 | afu->num_procs = 0; | |
637 | ||
638 | cxl_sysfs_afu_m_remove(afu); | |
639 | cxl_chardev_afu_remove(afu); | |
640 | ||
5e7823c9 IM |
641 | /* |
642 | * The CAIA section 2.2.1 indicates that the procedure for starting and | |
643 | * stopping an AFU in AFU directed mode is AFU specific, which is not | |
644 | * ideal since this code is generic and with one exception has no | |
645 | * knowledge of the AFU. This is in contrast to the procedure for | |
646 | * disabling a dedicated process AFU, which is documented to just | |
647 | * require a reset. The architecture does indicate that both an AFU | |
648 | * reset and an AFU disable should result in the AFU being disabled and | |
649 | * we do both followed by a PSL purge for safety. | |
650 | * | |
651 | * Notably we used to have some issues with the disable sequence on PSL | |
652 | * cards, which is why we ended up using this heavy weight procedure in | |
653 | * the first place, however a bug was discovered that had rendered the | |
654 | * disable operation ineffective, so it is conceivable that was the | |
655 | * sole explanation for those difficulties. Careful regression testing | |
656 | * is recommended if anyone attempts to remove or reorder these | |
657 | * operations. | |
658 | * | |
659 | * The XSL on the Mellanox CX4 behaves a little differently from the | |
660 | * PSL based cards and will time out an AFU reset if the AFU is still | |
661 | * enabled. That card is special in that we do have a means to identify | |
662 | * it from this code, so in that case we skip the reset and just use a | |
663 | * disable/purge to avoid the timeout and corresponding noise in the | |
664 | * kernel log. | |
665 | */ | |
666 | if (afu->adapter->native->sl_ops->needs_reset_before_disable) | |
667 | cxl_ops->afu_reset(afu); | |
f204e0b8 IM |
668 | cxl_afu_disable(afu); |
669 | cxl_psl_purge(afu); | |
670 | ||
f204e0b8 IM |
671 | return 0; |
672 | } | |
673 | ||
674 | static int activate_dedicated_process(struct cxl_afu *afu) | |
675 | { | |
676 | dev_info(&afu->dev, "Activating dedicated process mode\n"); | |
677 | ||
678 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process); | |
679 | ||
680 | cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */ | |
681 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */ | |
682 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); | |
683 | cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID)); | |
684 | cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */ | |
685 | cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1)); | |
686 | ||
687 | cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */ | |
688 | cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */ | |
689 | cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */ | |
690 | ||
691 | afu->current_mode = CXL_MODE_DEDICATED; | |
692 | afu->num_procs = 1; | |
693 | ||
694 | return cxl_chardev_d_afu_add(afu); | |
695 | } | |
696 | ||
292841b0 IM |
697 | static void update_ivtes_dedicated(struct cxl_context *ctx) |
698 | { | |
699 | struct cxl_afu *afu = ctx->afu; | |
700 | ||
701 | cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, | |
702 | (((u64)ctx->irqs.offset[0] & 0xffff) << 48) | | |
703 | (((u64)ctx->irqs.offset[1] & 0xffff) << 32) | | |
704 | (((u64)ctx->irqs.offset[2] & 0xffff) << 16) | | |
705 | ((u64)ctx->irqs.offset[3] & 0xffff)); | |
706 | cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64) | |
707 | (((u64)ctx->irqs.range[0] & 0xffff) << 48) | | |
708 | (((u64)ctx->irqs.range[1] & 0xffff) << 32) | | |
709 | (((u64)ctx->irqs.range[2] & 0xffff) << 16) | | |
710 | ((u64)ctx->irqs.range[3] & 0xffff)); | |
711 | } | |
712 | ||
f204e0b8 IM |
713 | static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr) |
714 | { | |
715 | struct cxl_afu *afu = ctx->afu; | |
2f663527 | 716 | u64 pid; |
f204e0b8 IM |
717 | int rc; |
718 | ||
2f663527 MN |
719 | pid = (u64)current->pid << 32; |
720 | if (ctx->kernel) | |
721 | pid = 0; | |
722 | cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid); | |
723 | ||
724 | cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx)); | |
f204e0b8 IM |
725 | |
726 | if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1))) | |
727 | return rc; | |
728 | ||
729 | cxl_prefault(ctx, wed); | |
730 | ||
292841b0 | 731 | update_ivtes_dedicated(ctx); |
f204e0b8 IM |
732 | |
733 | cxl_p2n_write(afu, CXL_PSL_AMR_An, amr); | |
734 | ||
735 | /* master only context for dedicated */ | |
1a1a94b8 | 736 | cxl_assign_psn_space(ctx); |
f204e0b8 | 737 | |
5be587b1 | 738 | if ((rc = cxl_ops->afu_reset(afu))) |
f204e0b8 IM |
739 | return rc; |
740 | ||
741 | cxl_p2n_write(afu, CXL_PSL_WED_An, wed); | |
742 | ||
743 | return afu_enable(afu); | |
744 | } | |
745 | ||
746 | static int deactivate_dedicated_process(struct cxl_afu *afu) | |
747 | { | |
748 | dev_info(&afu->dev, "Deactivating dedicated process mode\n"); | |
749 | ||
750 | afu->current_mode = 0; | |
751 | afu->num_procs = 0; | |
752 | ||
753 | cxl_chardev_afu_remove(afu); | |
754 | ||
755 | return 0; | |
756 | } | |
757 | ||
2b04cf31 | 758 | static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode) |
f204e0b8 IM |
759 | { |
760 | if (mode == CXL_MODE_DIRECTED) | |
761 | return deactivate_afu_directed(afu); | |
762 | if (mode == CXL_MODE_DEDICATED) | |
763 | return deactivate_dedicated_process(afu); | |
764 | return 0; | |
765 | } | |
766 | ||
2b04cf31 | 767 | static int native_afu_activate_mode(struct cxl_afu *afu, int mode) |
f204e0b8 IM |
768 | { |
769 | if (!mode) | |
770 | return 0; | |
771 | if (!(mode & afu->modes_supported)) | |
772 | return -EINVAL; | |
773 | ||
0d400f77 | 774 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
775 | WARN(1, "Device link is down, refusing to activate!\n"); |
776 | return -EIO; | |
777 | } | |
778 | ||
f204e0b8 IM |
779 | if (mode == CXL_MODE_DIRECTED) |
780 | return activate_afu_directed(afu); | |
781 | if (mode == CXL_MODE_DEDICATED) | |
782 | return activate_dedicated_process(afu); | |
783 | ||
784 | return -EINVAL; | |
785 | } | |
786 | ||
2b04cf31 FB |
787 | static int native_attach_process(struct cxl_context *ctx, bool kernel, |
788 | u64 wed, u64 amr) | |
f204e0b8 | 789 | { |
0d400f77 | 790 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
0b3f9c75 DA |
791 | WARN(1, "Device link is down, refusing to attach process!\n"); |
792 | return -EIO; | |
793 | } | |
794 | ||
f204e0b8 IM |
795 | ctx->kernel = kernel; |
796 | if (ctx->afu->current_mode == CXL_MODE_DIRECTED) | |
797 | return attach_afu_directed(ctx, wed, amr); | |
798 | ||
799 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) | |
800 | return attach_dedicated(ctx, wed, amr); | |
801 | ||
802 | return -EINVAL; | |
803 | } | |
804 | ||
805 | static inline int detach_process_native_dedicated(struct cxl_context *ctx) | |
806 | { | |
5e7823c9 IM |
807 | /* |
808 | * The CAIA section 2.1.1 indicates that we need to do an AFU reset to | |
809 | * stop the AFU in dedicated mode (we therefore do not make that | |
810 | * optional like we do in the afu directed path). It does not indicate | |
811 | * that we need to do an explicit disable (which should occur | |
812 | * implicitly as part of the reset) or purge, but we do these as well | |
813 | * to be on the safe side. | |
814 | * | |
815 | * Notably we used to have some issues with the disable sequence | |
816 | * (before the sequence was spelled out in the architecture) which is | |
817 | * why we were so heavy weight in the first place, however a bug was | |
818 | * discovered that had rendered the disable operation ineffective, so | |
819 | * it is conceivable that was the sole explanation for those | |
820 | * difficulties. Point is, we should be careful and do some regression | |
821 | * testing if we ever attempt to remove any part of this procedure. | |
822 | */ | |
5be587b1 | 823 | cxl_ops->afu_reset(ctx->afu); |
f204e0b8 IM |
824 | cxl_afu_disable(ctx->afu); |
825 | cxl_psl_purge(ctx->afu); | |
826 | return 0; | |
827 | } | |
828 | ||
292841b0 IM |
829 | static void native_update_ivtes(struct cxl_context *ctx) |
830 | { | |
831 | if (ctx->afu->current_mode == CXL_MODE_DIRECTED) | |
832 | return update_ivtes_directed(ctx); | |
833 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) | |
834 | return update_ivtes_dedicated(ctx); | |
835 | WARN(1, "native_update_ivtes: Bad mode\n"); | |
836 | } | |
837 | ||
f204e0b8 IM |
838 | static inline int detach_process_native_afu_directed(struct cxl_context *ctx) |
839 | { | |
840 | if (!ctx->pe_inserted) | |
841 | return 0; | |
842 | if (terminate_process_element(ctx)) | |
843 | return -1; | |
844 | if (remove_process_element(ctx)) | |
845 | return -1; | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
2b04cf31 | 850 | static int native_detach_process(struct cxl_context *ctx) |
f204e0b8 | 851 | { |
9bcf28cd IM |
852 | trace_cxl_detach(ctx); |
853 | ||
f204e0b8 IM |
854 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) |
855 | return detach_process_native_dedicated(ctx); | |
856 | ||
857 | return detach_process_native_afu_directed(ctx); | |
858 | } | |
859 | ||
2b04cf31 | 860 | static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info) |
f204e0b8 | 861 | { |
0b3f9c75 DA |
862 | /* If the adapter has gone away, we can't get any meaningful |
863 | * information. | |
864 | */ | |
0d400f77 | 865 | if (!cxl_ops->link_ok(afu->adapter, afu)) |
0b3f9c75 DA |
866 | return -EIO; |
867 | ||
bc78b05b IM |
868 | info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
869 | info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); | |
870 | info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An); | |
bc78b05b IM |
871 | info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An); |
872 | info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
444c4ba4 | 873 | info->proc_handle = 0; |
f204e0b8 IM |
874 | |
875 | return 0; | |
876 | } | |
877 | ||
6d382616 | 878 | void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx) |
d56d301b FB |
879 | { |
880 | u64 fir1, fir2, fir_slice, serr, afu_debug; | |
881 | ||
882 | fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1); | |
883 | fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2); | |
884 | fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An); | |
d56d301b FB |
885 | afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An); |
886 | ||
d56d301b FB |
887 | dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1); |
888 | dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2); | |
6d382616 FB |
889 | if (ctx->afu->adapter->native->sl_ops->register_serr_irq) { |
890 | serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An); | |
6e0c50f9 | 891 | cxl_afu_decode_psl_serr(ctx->afu, serr); |
6d382616 | 892 | } |
d56d301b FB |
893 | dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); |
894 | dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); | |
6d382616 FB |
895 | } |
896 | ||
897 | static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx, | |
898 | u64 dsisr, u64 errstat) | |
899 | { | |
900 | ||
901 | dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat); | |
d56d301b | 902 | |
6d382616 FB |
903 | if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers) |
904 | ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx); | |
905 | ||
906 | if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) { | |
907 | dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n"); | |
908 | ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter); | |
909 | } | |
d56d301b | 910 | |
5be587b1 | 911 | return cxl_ops->ack_irq(ctx, 0, errstat); |
d56d301b FB |
912 | } |
913 | ||
914 | static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info) | |
915 | { | |
916 | if (irq_info->dsisr & CXL_PSL_DSISR_TRANS) | |
917 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); | |
918 | else | |
919 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); | |
920 | ||
921 | return IRQ_HANDLED; | |
922 | } | |
923 | ||
2b04cf31 | 924 | static irqreturn_t native_irq_multiplexed(int irq, void *data) |
d56d301b FB |
925 | { |
926 | struct cxl_afu *afu = data; | |
927 | struct cxl_context *ctx; | |
928 | struct cxl_irq_info irq_info; | |
abf051be VJ |
929 | u64 phreg = cxl_p2n_read(afu, CXL_PSL_PEHandle_An); |
930 | int ph, ret; | |
931 | ||
932 | /* check if eeh kicked in while the interrupt was in flight */ | |
933 | if (unlikely(phreg == ~0ULL)) { | |
934 | dev_warn(&afu->dev, | |
935 | "Ignoring slice interrupt(%d) due to fenced card", | |
936 | irq); | |
937 | return IRQ_HANDLED; | |
938 | } | |
939 | /* Mask the pe-handle from register value */ | |
940 | ph = phreg & 0xffff; | |
2b04cf31 | 941 | if ((ret = native_get_irq_info(afu, &irq_info))) { |
d56d301b FB |
942 | WARN(1, "Unable to get CXL IRQ Info: %i\n", ret); |
943 | return fail_psl_irq(afu, &irq_info); | |
944 | } | |
945 | ||
946 | rcu_read_lock(); | |
947 | ctx = idr_find(&afu->contexts_idr, ph); | |
948 | if (ctx) { | |
949 | ret = cxl_irq(irq, ctx, &irq_info); | |
950 | rcu_read_unlock(); | |
951 | return ret; | |
952 | } | |
953 | rcu_read_unlock(); | |
954 | ||
955 | WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR" | |
956 | " %016llx\n(Possible AFU HW issue - was a term/remove acked" | |
957 | " with outstanding transactions?)\n", ph, irq_info.dsisr, | |
958 | irq_info.dar); | |
959 | return fail_psl_irq(afu, &irq_info); | |
960 | } | |
961 | ||
6fd40f19 | 962 | static void native_irq_wait(struct cxl_context *ctx) |
2bc79ffc MN |
963 | { |
964 | u64 dsisr; | |
965 | int timeout = 1000; | |
966 | int ph; | |
967 | ||
968 | /* | |
969 | * Wait until no further interrupts are presented by the PSL | |
970 | * for this context. | |
971 | */ | |
972 | while (timeout--) { | |
973 | ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff; | |
974 | if (ph != ctx->pe) | |
975 | return; | |
976 | dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An); | |
977 | if ((dsisr & CXL_PSL_DSISR_PENDING) == 0) | |
978 | return; | |
979 | /* | |
980 | * We are waiting for the workqueue to process our | |
981 | * irq, so need to let that run here. | |
982 | */ | |
983 | msleep(1); | |
984 | } | |
985 | ||
986 | dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i" | |
987 | " DSISR %016llx!\n", ph, dsisr); | |
988 | return; | |
989 | } | |
990 | ||
2b04cf31 | 991 | static irqreturn_t native_slice_irq_err(int irq, void *data) |
d56d301b FB |
992 | { |
993 | struct cxl_afu *afu = data; | |
6e0c50f9 | 994 | u64 fir_slice, errstat, serr, afu_debug, afu_error, dsisr; |
d56d301b | 995 | |
6d382616 FB |
996 | /* |
997 | * slice err interrupt is only used with full PSL (no XSL) | |
998 | */ | |
d56d301b FB |
999 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); |
1000 | fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An); | |
1001 | errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
1002 | afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An); | |
6e0c50f9 PB |
1003 | afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An); |
1004 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
1005 | cxl_afu_decode_psl_serr(afu, serr); | |
d56d301b FB |
1006 | dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); |
1007 | dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat); | |
1008 | dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); | |
6e0c50f9 PB |
1009 | dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error); |
1010 | dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr); | |
d56d301b FB |
1011 | |
1012 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); | |
1013 | ||
1014 | return IRQ_HANDLED; | |
1015 | } | |
1016 | ||
6d382616 FB |
1017 | void cxl_native_err_irq_dump_regs(struct cxl *adapter) |
1018 | { | |
1019 | u64 fir1, fir2; | |
1020 | ||
1021 | fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1); | |
1022 | fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2); | |
1023 | ||
1024 | dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2); | |
1025 | } | |
1026 | ||
2b04cf31 | 1027 | static irqreturn_t native_irq_err(int irq, void *data) |
d56d301b FB |
1028 | { |
1029 | struct cxl *adapter = data; | |
6d382616 | 1030 | u64 err_ivte; |
d56d301b FB |
1031 | |
1032 | WARN(1, "CXL ERROR interrupt %i\n", irq); | |
1033 | ||
1034 | err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE); | |
1035 | dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte); | |
1036 | ||
6d382616 FB |
1037 | if (adapter->native->sl_ops->debugfs_stop_trace) { |
1038 | dev_crit(&adapter->dev, "STOPPING CXL TRACE\n"); | |
1039 | adapter->native->sl_ops->debugfs_stop_trace(adapter); | |
1040 | } | |
d56d301b | 1041 | |
6d382616 FB |
1042 | if (adapter->native->sl_ops->err_irq_dump_registers) |
1043 | adapter->native->sl_ops->err_irq_dump_registers(adapter); | |
d56d301b FB |
1044 | |
1045 | return IRQ_HANDLED; | |
1046 | } | |
1047 | ||
2b04cf31 | 1048 | int cxl_native_register_psl_err_irq(struct cxl *adapter) |
d56d301b FB |
1049 | { |
1050 | int rc; | |
1051 | ||
1052 | adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", | |
1053 | dev_name(&adapter->dev)); | |
1054 | if (!adapter->irq_name) | |
1055 | return -ENOMEM; | |
1056 | ||
2b04cf31 | 1057 | if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter, |
cbffa3a5 CL |
1058 | &adapter->native->err_hwirq, |
1059 | &adapter->native->err_virq, | |
d56d301b FB |
1060 | adapter->irq_name))) { |
1061 | kfree(adapter->irq_name); | |
1062 | adapter->irq_name = NULL; | |
1063 | return rc; | |
1064 | } | |
1065 | ||
cbffa3a5 | 1066 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff); |
d56d301b FB |
1067 | |
1068 | return 0; | |
1069 | } | |
1070 | ||
2b04cf31 | 1071 | void cxl_native_release_psl_err_irq(struct cxl *adapter) |
d56d301b | 1072 | { |
cbffa3a5 | 1073 | if (adapter->native->err_virq != irq_find_mapping(NULL, adapter->native->err_hwirq)) |
d56d301b FB |
1074 | return; |
1075 | ||
1076 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000); | |
cbffa3a5 CL |
1077 | cxl_unmap_irq(adapter->native->err_virq, adapter); |
1078 | cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq); | |
d56d301b FB |
1079 | kfree(adapter->irq_name); |
1080 | } | |
1081 | ||
2b04cf31 | 1082 | int cxl_native_register_serr_irq(struct cxl_afu *afu) |
d56d301b FB |
1083 | { |
1084 | u64 serr; | |
1085 | int rc; | |
1086 | ||
1087 | afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", | |
1088 | dev_name(&afu->dev)); | |
1089 | if (!afu->err_irq_name) | |
1090 | return -ENOMEM; | |
1091 | ||
2b04cf31 | 1092 | if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu, |
d56d301b FB |
1093 | &afu->serr_hwirq, |
1094 | &afu->serr_virq, afu->err_irq_name))) { | |
1095 | kfree(afu->err_irq_name); | |
1096 | afu->err_irq_name = NULL; | |
1097 | return rc; | |
1098 | } | |
1099 | ||
1100 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
1101 | serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff); | |
1102 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); | |
1103 | ||
1104 | return 0; | |
1105 | } | |
1106 | ||
2b04cf31 | 1107 | void cxl_native_release_serr_irq(struct cxl_afu *afu) |
d56d301b FB |
1108 | { |
1109 | if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq)) | |
1110 | return; | |
1111 | ||
1112 | cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000); | |
1113 | cxl_unmap_irq(afu->serr_virq, afu); | |
5be587b1 | 1114 | cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq); |
d56d301b FB |
1115 | kfree(afu->err_irq_name); |
1116 | } | |
1117 | ||
2b04cf31 | 1118 | int cxl_native_register_psl_irq(struct cxl_afu *afu) |
d56d301b FB |
1119 | { |
1120 | int rc; | |
1121 | ||
1122 | afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s", | |
1123 | dev_name(&afu->dev)); | |
1124 | if (!afu->psl_irq_name) | |
1125 | return -ENOMEM; | |
1126 | ||
cbffa3a5 CL |
1127 | if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed, |
1128 | afu, &afu->native->psl_hwirq, &afu->native->psl_virq, | |
d56d301b FB |
1129 | afu->psl_irq_name))) { |
1130 | kfree(afu->psl_irq_name); | |
1131 | afu->psl_irq_name = NULL; | |
1132 | } | |
1133 | return rc; | |
1134 | } | |
1135 | ||
2b04cf31 | 1136 | void cxl_native_release_psl_irq(struct cxl_afu *afu) |
d56d301b | 1137 | { |
cbffa3a5 | 1138 | if (afu->native->psl_virq != irq_find_mapping(NULL, afu->native->psl_hwirq)) |
d56d301b FB |
1139 | return; |
1140 | ||
cbffa3a5 CL |
1141 | cxl_unmap_irq(afu->native->psl_virq, afu); |
1142 | cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq); | |
d56d301b FB |
1143 | kfree(afu->psl_irq_name); |
1144 | } | |
1145 | ||
f204e0b8 IM |
1146 | static void recover_psl_err(struct cxl_afu *afu, u64 errstat) |
1147 | { | |
1148 | u64 dsisr; | |
1149 | ||
de369538 | 1150 | pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat); |
f204e0b8 IM |
1151 | |
1152 | /* Clear PSL_DSISR[PE] */ | |
1153 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
1154 | cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE); | |
1155 | ||
1156 | /* Write 1s to clear error status bits */ | |
1157 | cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat); | |
1158 | } | |
1159 | ||
2b04cf31 | 1160 | static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask) |
f204e0b8 | 1161 | { |
9bcf28cd | 1162 | trace_cxl_psl_irq_ack(ctx, tfc); |
f204e0b8 IM |
1163 | if (tfc) |
1164 | cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc); | |
1165 | if (psl_reset_mask) | |
1166 | recover_psl_err(ctx->afu, psl_reset_mask); | |
1167 | ||
1168 | return 0; | |
1169 | } | |
1170 | ||
1171 | int cxl_check_error(struct cxl_afu *afu) | |
1172 | { | |
1173 | return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL); | |
1174 | } | |
d56d301b | 1175 | |
4752876c CL |
1176 | static bool native_support_attributes(const char *attr_name, |
1177 | enum cxl_attrs type) | |
1178 | { | |
1179 | return true; | |
1180 | } | |
1181 | ||
2b04cf31 | 1182 | static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out) |
d56d301b | 1183 | { |
0d400f77 | 1184 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
5be587b1 FB |
1185 | return -EIO; |
1186 | if (unlikely(off >= afu->crs_len)) | |
1187 | return -ERANGE; | |
cbffa3a5 | 1188 | *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset + |
5be587b1 FB |
1189 | (cr * afu->crs_len) + off); |
1190 | return 0; | |
d56d301b FB |
1191 | } |
1192 | ||
2b04cf31 | 1193 | static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out) |
d56d301b | 1194 | { |
0d400f77 | 1195 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
5be587b1 FB |
1196 | return -EIO; |
1197 | if (unlikely(off >= afu->crs_len)) | |
1198 | return -ERANGE; | |
cbffa3a5 | 1199 | *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset + |
5be587b1 FB |
1200 | (cr * afu->crs_len) + off); |
1201 | return 0; | |
d56d301b FB |
1202 | } |
1203 | ||
2b04cf31 | 1204 | static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out) |
d56d301b FB |
1205 | { |
1206 | u64 aligned_off = off & ~0x3L; | |
1207 | u32 val; | |
5be587b1 | 1208 | int rc; |
d56d301b | 1209 | |
2b04cf31 | 1210 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
5be587b1 FB |
1211 | if (!rc) |
1212 | *out = (val >> ((off & 0x3) * 8)) & 0xffff; | |
1213 | return rc; | |
d56d301b FB |
1214 | } |
1215 | ||
2b04cf31 | 1216 | static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out) |
d56d301b FB |
1217 | { |
1218 | u64 aligned_off = off & ~0x3L; | |
1219 | u32 val; | |
5be587b1 | 1220 | int rc; |
d56d301b | 1221 | |
2b04cf31 | 1222 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
5be587b1 FB |
1223 | if (!rc) |
1224 | *out = (val >> ((off & 0x3) * 8)) & 0xff; | |
1225 | return rc; | |
d56d301b | 1226 | } |
5be587b1 | 1227 | |
d601ea91 FB |
1228 | static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in) |
1229 | { | |
0d400f77 | 1230 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
d601ea91 FB |
1231 | return -EIO; |
1232 | if (unlikely(off >= afu->crs_len)) | |
1233 | return -ERANGE; | |
1234 | out_le32(afu->native->afu_desc_mmio + afu->crs_offset + | |
1235 | (cr * afu->crs_len) + off, in); | |
1236 | return 0; | |
1237 | } | |
1238 | ||
1239 | static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in) | |
1240 | { | |
1241 | u64 aligned_off = off & ~0x3L; | |
1242 | u32 val32, mask, shift; | |
1243 | int rc; | |
1244 | ||
1245 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); | |
1246 | if (rc) | |
1247 | return rc; | |
1248 | shift = (off & 0x3) * 8; | |
1249 | WARN_ON(shift == 24); | |
1250 | mask = 0xffff << shift; | |
1251 | val32 = (val32 & ~mask) | (in << shift); | |
1252 | ||
1253 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); | |
1254 | return rc; | |
1255 | } | |
1256 | ||
1257 | static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in) | |
1258 | { | |
1259 | u64 aligned_off = off & ~0x3L; | |
1260 | u32 val32, mask, shift; | |
1261 | int rc; | |
1262 | ||
1263 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); | |
1264 | if (rc) | |
1265 | return rc; | |
1266 | shift = (off & 0x3) * 8; | |
1267 | mask = 0xff << shift; | |
1268 | val32 = (val32 & ~mask) | (in << shift); | |
1269 | ||
1270 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); | |
1271 | return rc; | |
1272 | } | |
1273 | ||
5be587b1 FB |
1274 | const struct cxl_backend_ops cxl_native_ops = { |
1275 | .module = THIS_MODULE, | |
2b04cf31 FB |
1276 | .adapter_reset = cxl_pci_reset, |
1277 | .alloc_one_irq = cxl_pci_alloc_one_irq, | |
1278 | .release_one_irq = cxl_pci_release_one_irq, | |
1279 | .alloc_irq_ranges = cxl_pci_alloc_irq_ranges, | |
1280 | .release_irq_ranges = cxl_pci_release_irq_ranges, | |
1281 | .setup_irq = cxl_pci_setup_irq, | |
1282 | .handle_psl_slice_error = native_handle_psl_slice_error, | |
5be587b1 | 1283 | .psl_interrupt = NULL, |
2b04cf31 | 1284 | .ack_irq = native_ack_irq, |
2bc79ffc | 1285 | .irq_wait = native_irq_wait, |
2b04cf31 FB |
1286 | .attach_process = native_attach_process, |
1287 | .detach_process = native_detach_process, | |
292841b0 | 1288 | .update_ivtes = native_update_ivtes, |
4752876c | 1289 | .support_attributes = native_support_attributes, |
5be587b1 | 1290 | .link_ok = cxl_adapter_link_ok, |
2b04cf31 FB |
1291 | .release_afu = cxl_pci_release_afu, |
1292 | .afu_read_err_buffer = cxl_pci_afu_read_err_buffer, | |
1293 | .afu_check_and_enable = native_afu_check_and_enable, | |
1294 | .afu_activate_mode = native_afu_activate_mode, | |
1295 | .afu_deactivate_mode = native_afu_deactivate_mode, | |
1296 | .afu_reset = native_afu_reset, | |
1297 | .afu_cr_read8 = native_afu_cr_read8, | |
1298 | .afu_cr_read16 = native_afu_cr_read16, | |
1299 | .afu_cr_read32 = native_afu_cr_read32, | |
1300 | .afu_cr_read64 = native_afu_cr_read64, | |
d601ea91 FB |
1301 | .afu_cr_write8 = native_afu_cr_write8, |
1302 | .afu_cr_write16 = native_afu_cr_write16, | |
1303 | .afu_cr_write32 = native_afu_cr_write32, | |
1304 | .read_adapter_vpd = cxl_pci_read_adapter_vpd, | |
5be587b1 | 1305 | }; |