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f204e0b8 IM |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/pci_regs.h> | |
11 | #include <linux/pci_ids.h> | |
12 | #include <linux/device.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/sort.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/delay.h> | |
20 | #include <asm/opal.h> | |
21 | #include <asm/msi_bitmap.h> | |
f204e0b8 | 22 | #include <asm/pnv-pci.h> |
62fa19d4 | 23 | #include <asm/io.h> |
aa14138a | 24 | #include <asm/reg.h> |
f204e0b8 IM |
25 | |
26 | #include "cxl.h" | |
9e8df8a2 | 27 | #include <misc/cxl.h> |
f204e0b8 IM |
28 | |
29 | ||
30 | #define CXL_PCI_VSEC_ID 0x1280 | |
31 | #define CXL_VSEC_MIN_SIZE 0x80 | |
32 | ||
33 | #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \ | |
34 | { \ | |
35 | pci_read_config_word(dev, vsec + 0x6, dest); \ | |
36 | *dest >>= 4; \ | |
37 | } | |
38 | #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \ | |
39 | pci_read_config_byte(dev, vsec + 0x8, dest) | |
40 | ||
41 | #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \ | |
42 | pci_read_config_byte(dev, vsec + 0x9, dest) | |
43 | #define CXL_STATUS_SECOND_PORT 0x80 | |
44 | #define CXL_STATUS_MSI_X_FULL 0x40 | |
45 | #define CXL_STATUS_MSI_X_SINGLE 0x20 | |
46 | #define CXL_STATUS_FLASH_RW 0x08 | |
47 | #define CXL_STATUS_FLASH_RO 0x04 | |
48 | #define CXL_STATUS_LOADABLE_AFU 0x02 | |
49 | #define CXL_STATUS_LOADABLE_PSL 0x01 | |
50 | /* If we see these features we won't try to use the card */ | |
51 | #define CXL_UNSUPPORTED_FEATURES \ | |
52 | (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE) | |
53 | ||
54 | #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \ | |
55 | pci_read_config_byte(dev, vsec + 0xa, dest) | |
56 | #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \ | |
57 | pci_write_config_byte(dev, vsec + 0xa, val) | |
b0b5e591 AD |
58 | #define CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, vsec, val) \ |
59 | pci_bus_write_config_byte(bus, devfn, vsec + 0xa, val) | |
f204e0b8 IM |
60 | #define CXL_VSEC_PROTOCOL_MASK 0xe0 |
61 | #define CXL_VSEC_PROTOCOL_1024TB 0x80 | |
62 | #define CXL_VSEC_PROTOCOL_512TB 0x40 | |
f24be42a | 63 | #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8/9 uses this */ |
f204e0b8 IM |
64 | #define CXL_VSEC_PROTOCOL_ENABLE 0x01 |
65 | ||
66 | #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \ | |
67 | pci_read_config_word(dev, vsec + 0xc, dest) | |
68 | #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \ | |
69 | pci_read_config_byte(dev, vsec + 0xe, dest) | |
70 | #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \ | |
71 | pci_read_config_byte(dev, vsec + 0xf, dest) | |
72 | #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \ | |
73 | pci_read_config_word(dev, vsec + 0x10, dest) | |
74 | ||
75 | #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \ | |
76 | pci_read_config_byte(dev, vsec + 0x13, dest) | |
77 | #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \ | |
78 | pci_write_config_byte(dev, vsec + 0x13, val) | |
79 | #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */ | |
80 | #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */ | |
81 | #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */ | |
82 | ||
83 | #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \ | |
84 | pci_read_config_dword(dev, vsec + 0x20, dest) | |
85 | #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \ | |
86 | pci_read_config_dword(dev, vsec + 0x24, dest) | |
87 | #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \ | |
88 | pci_read_config_dword(dev, vsec + 0x28, dest) | |
89 | #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \ | |
90 | pci_read_config_dword(dev, vsec + 0x2c, dest) | |
91 | ||
92 | ||
93 | /* This works a little different than the p1/p2 register accesses to make it | |
94 | * easier to pull out individual fields */ | |
cbffa3a5 CL |
95 | #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off) |
96 | #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off) | |
f204e0b8 IM |
97 | #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit))) |
98 | #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be)) | |
99 | ||
100 | #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0) | |
101 | #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15) | |
102 | #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31) | |
103 | #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47) | |
104 | #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48) | |
105 | #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55) | |
106 | #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59) | |
107 | #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61) | |
108 | #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63) | |
109 | #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20) | |
110 | #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) | |
111 | #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28) | |
112 | #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30) | |
113 | #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6) | |
114 | #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7) | |
115 | #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) | |
116 | #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38) | |
117 | #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40) | |
118 | #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) | |
119 | #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48) | |
120 | ||
f47f966f | 121 | static const struct pci_device_id cxl_pci_tbl[] = { |
f204e0b8 IM |
122 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), }, |
123 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), }, | |
124 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), }, | |
68adb7bf | 125 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), }, |
41e20d95 MO |
126 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), }, |
127 | { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), }, | |
f204e0b8 IM |
128 | { PCI_DEVICE_CLASS(0x120000, ~0), }, |
129 | ||
130 | { } | |
131 | }; | |
132 | MODULE_DEVICE_TABLE(pci, cxl_pci_tbl); | |
133 | ||
134 | ||
135 | /* | |
136 | * Mostly using these wrappers to avoid confusion: | |
137 | * priv 1 is BAR2, while priv 2 is BAR0 | |
138 | */ | |
139 | static inline resource_size_t p1_base(struct pci_dev *dev) | |
140 | { | |
141 | return pci_resource_start(dev, 2); | |
142 | } | |
143 | ||
144 | static inline resource_size_t p1_size(struct pci_dev *dev) | |
145 | { | |
146 | return pci_resource_len(dev, 2); | |
147 | } | |
148 | ||
149 | static inline resource_size_t p2_base(struct pci_dev *dev) | |
150 | { | |
151 | return pci_resource_start(dev, 0); | |
152 | } | |
153 | ||
154 | static inline resource_size_t p2_size(struct pci_dev *dev) | |
155 | { | |
156 | return pci_resource_len(dev, 0); | |
157 | } | |
158 | ||
159 | static int find_cxl_vsec(struct pci_dev *dev) | |
160 | { | |
161 | int vsec = 0; | |
162 | u16 val; | |
163 | ||
164 | while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) { | |
165 | pci_read_config_word(dev, vsec + 0x4, &val); | |
166 | if (val == CXL_PCI_VSEC_ID) | |
167 | return vsec; | |
168 | } | |
169 | return 0; | |
170 | ||
171 | } | |
172 | ||
173 | static void dump_cxl_config_space(struct pci_dev *dev) | |
174 | { | |
175 | int vsec; | |
176 | u32 val; | |
177 | ||
178 | dev_info(&dev->dev, "dump_cxl_config_space\n"); | |
179 | ||
180 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val); | |
181 | dev_info(&dev->dev, "BAR0: %#.8x\n", val); | |
182 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val); | |
183 | dev_info(&dev->dev, "BAR1: %#.8x\n", val); | |
184 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val); | |
185 | dev_info(&dev->dev, "BAR2: %#.8x\n", val); | |
186 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val); | |
187 | dev_info(&dev->dev, "BAR3: %#.8x\n", val); | |
188 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val); | |
189 | dev_info(&dev->dev, "BAR4: %#.8x\n", val); | |
190 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val); | |
191 | dev_info(&dev->dev, "BAR5: %#.8x\n", val); | |
192 | ||
193 | dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n", | |
194 | p1_base(dev), p1_size(dev)); | |
195 | dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n", | |
f2931069 | 196 | p2_base(dev), p2_size(dev)); |
f204e0b8 IM |
197 | dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n", |
198 | pci_resource_start(dev, 4), pci_resource_len(dev, 4)); | |
199 | ||
200 | if (!(vsec = find_cxl_vsec(dev))) | |
201 | return; | |
202 | ||
203 | #define show_reg(name, what) \ | |
204 | dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what) | |
205 | ||
206 | pci_read_config_dword(dev, vsec + 0x0, &val); | |
207 | show_reg("Cap ID", (val >> 0) & 0xffff); | |
208 | show_reg("Cap Ver", (val >> 16) & 0xf); | |
209 | show_reg("Next Cap Ptr", (val >> 20) & 0xfff); | |
210 | pci_read_config_dword(dev, vsec + 0x4, &val); | |
211 | show_reg("VSEC ID", (val >> 0) & 0xffff); | |
212 | show_reg("VSEC Rev", (val >> 16) & 0xf); | |
213 | show_reg("VSEC Length", (val >> 20) & 0xfff); | |
214 | pci_read_config_dword(dev, vsec + 0x8, &val); | |
215 | show_reg("Num AFUs", (val >> 0) & 0xff); | |
216 | show_reg("Status", (val >> 8) & 0xff); | |
217 | show_reg("Mode Control", (val >> 16) & 0xff); | |
218 | show_reg("Reserved", (val >> 24) & 0xff); | |
219 | pci_read_config_dword(dev, vsec + 0xc, &val); | |
220 | show_reg("PSL Rev", (val >> 0) & 0xffff); | |
221 | show_reg("CAIA Ver", (val >> 16) & 0xffff); | |
222 | pci_read_config_dword(dev, vsec + 0x10, &val); | |
223 | show_reg("Base Image Rev", (val >> 0) & 0xffff); | |
224 | show_reg("Reserved", (val >> 16) & 0x0fff); | |
225 | show_reg("Image Control", (val >> 28) & 0x3); | |
226 | show_reg("Reserved", (val >> 30) & 0x1); | |
227 | show_reg("Image Loaded", (val >> 31) & 0x1); | |
228 | ||
229 | pci_read_config_dword(dev, vsec + 0x14, &val); | |
230 | show_reg("Reserved", val); | |
231 | pci_read_config_dword(dev, vsec + 0x18, &val); | |
232 | show_reg("Reserved", val); | |
233 | pci_read_config_dword(dev, vsec + 0x1c, &val); | |
234 | show_reg("Reserved", val); | |
235 | ||
236 | pci_read_config_dword(dev, vsec + 0x20, &val); | |
237 | show_reg("AFU Descriptor Offset", val); | |
238 | pci_read_config_dword(dev, vsec + 0x24, &val); | |
239 | show_reg("AFU Descriptor Size", val); | |
240 | pci_read_config_dword(dev, vsec + 0x28, &val); | |
241 | show_reg("Problem State Offset", val); | |
242 | pci_read_config_dword(dev, vsec + 0x2c, &val); | |
243 | show_reg("Problem State Size", val); | |
244 | ||
245 | pci_read_config_dword(dev, vsec + 0x30, &val); | |
246 | show_reg("Reserved", val); | |
247 | pci_read_config_dword(dev, vsec + 0x34, &val); | |
248 | show_reg("Reserved", val); | |
249 | pci_read_config_dword(dev, vsec + 0x38, &val); | |
250 | show_reg("Reserved", val); | |
251 | pci_read_config_dword(dev, vsec + 0x3c, &val); | |
252 | show_reg("Reserved", val); | |
253 | ||
254 | pci_read_config_dword(dev, vsec + 0x40, &val); | |
255 | show_reg("PSL Programming Port", val); | |
256 | pci_read_config_dword(dev, vsec + 0x44, &val); | |
257 | show_reg("PSL Programming Control", val); | |
258 | ||
259 | pci_read_config_dword(dev, vsec + 0x48, &val); | |
260 | show_reg("Reserved", val); | |
261 | pci_read_config_dword(dev, vsec + 0x4c, &val); | |
262 | show_reg("Reserved", val); | |
263 | ||
264 | pci_read_config_dword(dev, vsec + 0x50, &val); | |
265 | show_reg("Flash Address Register", val); | |
266 | pci_read_config_dword(dev, vsec + 0x54, &val); | |
267 | show_reg("Flash Size Register", val); | |
268 | pci_read_config_dword(dev, vsec + 0x58, &val); | |
269 | show_reg("Flash Status/Control Register", val); | |
270 | pci_read_config_dword(dev, vsec + 0x58, &val); | |
271 | show_reg("Flash Data Port", val); | |
272 | ||
273 | #undef show_reg | |
274 | } | |
275 | ||
276 | static void dump_afu_descriptor(struct cxl_afu *afu) | |
277 | { | |
bfcdc8ff MN |
278 | u64 val, afu_cr_num, afu_cr_off, afu_cr_len; |
279 | int i; | |
f204e0b8 IM |
280 | |
281 | #define show_reg(name, what) \ | |
282 | dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what) | |
283 | ||
284 | val = AFUD_READ_INFO(afu); | |
285 | show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val)); | |
286 | show_reg("num_of_processes", AFUD_NUM_PROCS(val)); | |
287 | show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val)); | |
288 | show_reg("req_prog_mode", val & 0xffffULL); | |
bfcdc8ff | 289 | afu_cr_num = AFUD_NUM_CRS(val); |
f204e0b8 IM |
290 | |
291 | val = AFUD_READ(afu, 0x8); | |
292 | show_reg("Reserved", val); | |
293 | val = AFUD_READ(afu, 0x10); | |
294 | show_reg("Reserved", val); | |
295 | val = AFUD_READ(afu, 0x18); | |
296 | show_reg("Reserved", val); | |
297 | ||
298 | val = AFUD_READ_CR(afu); | |
299 | show_reg("Reserved", (val >> (63-7)) & 0xff); | |
300 | show_reg("AFU_CR_len", AFUD_CR_LEN(val)); | |
bfcdc8ff | 301 | afu_cr_len = AFUD_CR_LEN(val) * 256; |
f204e0b8 IM |
302 | |
303 | val = AFUD_READ_CR_OFF(afu); | |
bfcdc8ff | 304 | afu_cr_off = val; |
f204e0b8 IM |
305 | show_reg("AFU_CR_offset", val); |
306 | ||
307 | val = AFUD_READ_PPPSA(afu); | |
308 | show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff); | |
309 | show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val)); | |
310 | ||
311 | val = AFUD_READ_PPPSA_OFF(afu); | |
312 | show_reg("PerProcessPSA_offset", val); | |
313 | ||
314 | val = AFUD_READ_EB(afu); | |
315 | show_reg("Reserved", (val >> (63-7)) & 0xff); | |
316 | show_reg("AFU_EB_len", AFUD_EB_LEN(val)); | |
317 | ||
318 | val = AFUD_READ_EB_OFF(afu); | |
319 | show_reg("AFU_EB_offset", val); | |
320 | ||
bfcdc8ff MN |
321 | for (i = 0; i < afu_cr_num; i++) { |
322 | val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len); | |
323 | show_reg("CR Vendor", val & 0xffff); | |
324 | show_reg("CR Device", (val >> 16) & 0xffff); | |
325 | } | |
f204e0b8 IM |
326 | #undef show_reg |
327 | } | |
328 | ||
abd1d99b CL |
329 | #define P8_CAPP_UNIT0_ID 0xBA |
330 | #define P8_CAPP_UNIT1_ID 0XBE | |
f24be42a CL |
331 | #define P9_CAPP_UNIT0_ID 0xC0 |
332 | #define P9_CAPP_UNIT1_ID 0xE0 | |
aa14138a | 333 | |
f24be42a | 334 | static int get_phb_index(struct device_node *np, u32 *phb_index) |
aa14138a | 335 | { |
f24be42a CL |
336 | if (of_property_read_u32(np, "ibm,phb-index", phb_index)) |
337 | return -ENODEV; | |
338 | return 0; | |
339 | } | |
aa14138a | 340 | |
f24be42a CL |
341 | static u64 get_capp_unit_id(struct device_node *np, u32 phb_index) |
342 | { | |
aa14138a | 343 | /* |
abd1d99b CL |
344 | * POWER 8: |
345 | * - For chips other than POWER8NVL, we only have CAPP 0, | |
346 | * irrespective of which PHB is used. | |
347 | * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and | |
348 | * CAPP 1 is attached to PHB1. | |
aa14138a | 349 | */ |
abd1d99b CL |
350 | if (cxl_is_power8()) { |
351 | if (!pvr_version_is(PVR_POWER8NVL)) | |
352 | return P8_CAPP_UNIT0_ID; | |
aa14138a | 353 | |
abd1d99b CL |
354 | if (phb_index == 0) |
355 | return P8_CAPP_UNIT0_ID; | |
aa14138a | 356 | |
abd1d99b CL |
357 | if (phb_index == 1) |
358 | return P8_CAPP_UNIT1_ID; | |
359 | } | |
aa14138a PB |
360 | |
361 | /* | |
f24be42a CL |
362 | * POWER 9: |
363 | * PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000) | |
364 | * PEC1 (PHB1 - PHB2). No capi mode | |
365 | * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000) | |
aa14138a | 366 | */ |
f24be42a CL |
367 | if (cxl_is_power9()) { |
368 | if (phb_index == 0) | |
369 | return P9_CAPP_UNIT0_ID; | |
aa14138a | 370 | |
f24be42a CL |
371 | if (phb_index == 3) |
372 | return P9_CAPP_UNIT1_ID; | |
373 | } | |
aa14138a PB |
374 | |
375 | return 0; | |
376 | } | |
377 | ||
3ced8d73 | 378 | int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid, |
f24be42a | 379 | u32 *phb_index, u64 *capp_unit_id) |
f204e0b8 | 380 | { |
f24be42a | 381 | int rc; |
f204e0b8 IM |
382 | struct device_node *np; |
383 | const __be32 *prop; | |
f204e0b8 | 384 | |
6f963ec2 | 385 | if (!(np = pnv_pci_get_phb_node(dev))) |
f204e0b8 IM |
386 | return -ENODEV; |
387 | ||
388 | while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL))) | |
389 | np = of_get_next_parent(np); | |
390 | if (!np) | |
391 | return -ENODEV; | |
f24be42a | 392 | |
6d382616 | 393 | *chipid = be32_to_cpup(prop); |
f24be42a CL |
394 | |
395 | rc = get_phb_index(np, phb_index); | |
396 | if (rc) { | |
397 | pr_err("cxl: invalid phb index\n"); | |
398 | return rc; | |
399 | } | |
400 | ||
401 | *capp_unit_id = get_capp_unit_id(np, *phb_index); | |
f204e0b8 | 402 | of_node_put(np); |
6d382616 | 403 | if (!*capp_unit_id) { |
aa14138a PB |
404 | pr_err("cxl: invalid capp unit id\n"); |
405 | return -ENODEV; | |
406 | } | |
f204e0b8 | 407 | |
6d382616 FB |
408 | return 0; |
409 | } | |
410 | ||
3ced8d73 | 411 | int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg) |
f24be42a | 412 | { |
3ced8d73 | 413 | u64 xsl_dsnctl; |
f24be42a CL |
414 | |
415 | /* | |
416 | * CAPI Identifier bits [0:7] | |
417 | * bit 61:60 MSI bits --> 0 | |
418 | * bit 59 TVT selector --> 0 | |
419 | */ | |
420 | ||
421 | /* | |
422 | * Tell XSL where to route data to. | |
423 | * The field chipid should match the PHB CAPI_CMPM register | |
424 | */ | |
425 | xsl_dsnctl = ((u64)0x2 << (63-7)); /* Bit 57 */ | |
426 | xsl_dsnctl |= (capp_unit_id << (63-15)); | |
427 | ||
428 | /* nMMU_ID Defaults to: b’000001001’*/ | |
429 | xsl_dsnctl |= ((u64)0x09 << (63-28)); | |
430 | ||
797625de | 431 | if (!(cxl_is_power9_dd1())) { |
f24be42a CL |
432 | /* |
433 | * Used to identify CAPI packets which should be sorted into | |
434 | * the Non-Blocking queues by the PHB. This field should match | |
435 | * the PHB PBL_NBW_CMPM register | |
436 | * nbwind=0x03, bits [57:58], must include capi indicator. | |
437 | * Not supported on P9 DD1. | |
438 | */ | |
439 | xsl_dsnctl |= ((u64)0x03 << (63-47)); | |
440 | ||
441 | /* | |
442 | * Upper 16b address bits of ASB_Notify messages sent to the | |
443 | * system. Need to match the PHB’s ASN Compare/Mask Register. | |
444 | * Not supported on P9 DD1. | |
445 | */ | |
446 | xsl_dsnctl |= ((u64)0x04 << (63-55)); | |
447 | } | |
448 | ||
3ced8d73 CL |
449 | *reg = xsl_dsnctl; |
450 | return 0; | |
451 | } | |
452 | ||
453 | static int init_implementation_adapter_regs_psl9(struct cxl *adapter, | |
454 | struct pci_dev *dev) | |
455 | { | |
456 | u64 xsl_dsnctl, psl_fircntl; | |
457 | u64 chipid; | |
458 | u32 phb_index; | |
459 | u64 capp_unit_id; | |
460 | int rc; | |
461 | ||
462 | rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id); | |
463 | if (rc) | |
464 | return rc; | |
465 | ||
466 | rc = cxl_get_xsl9_dsnctl(capp_unit_id, &xsl_dsnctl); | |
467 | if (rc) | |
468 | return rc; | |
469 | ||
f24be42a CL |
470 | cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl); |
471 | ||
472 | /* Set fir_cntl to recommended value for production env */ | |
473 | psl_fircntl = (0x2ULL << (63-3)); /* ce_report */ | |
474 | psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */ | |
475 | psl_fircntl |= 0x1ULL; /* ce_thresh */ | |
476 | cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl); | |
477 | ||
478 | /* vccredits=0x1 pcklat=0x4 */ | |
479 | cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL); | |
480 | ||
481 | /* | |
482 | * For debugging with trace arrays. | |
483 | * Configure RX trace 0 segmented mode. | |
484 | * Configure CT trace 0 segmented mode. | |
485 | * Configure LA0 trace 0 segmented mode. | |
486 | * Configure LA1 trace 0 segmented mode. | |
487 | */ | |
488 | cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL); | |
489 | cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL); | |
490 | cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL); | |
491 | cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL); | |
492 | ||
493 | /* | |
494 | * A response to an ASB_Notify request is returned by the | |
495 | * system as an MMIO write to the address defined in | |
496 | * the PSL_TNR_ADDR register | |
497 | */ | |
498 | /* PSL_TNR_ADDR */ | |
499 | ||
500 | /* NORST */ | |
501 | cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL); | |
502 | ||
503 | /* allocate the apc machines */ | |
504 | cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL); | |
505 | ||
506 | /* Disable vc dd1 fix */ | |
797625de | 507 | if (cxl_is_power9_dd1()) |
f24be42a CL |
508 | cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL); |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
64663f37 | 513 | static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev) |
6d382616 | 514 | { |
c6d2ee09 | 515 | u64 psl_dsnctl, psl_fircntl; |
6d382616 | 516 | u64 chipid; |
f24be42a | 517 | u32 phb_index; |
6d382616 FB |
518 | u64 capp_unit_id; |
519 | int rc; | |
520 | ||
3ced8d73 | 521 | rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id); |
6d382616 FB |
522 | if (rc) |
523 | return rc; | |
524 | ||
4aec6ec0 FB |
525 | psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */ |
526 | psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */ | |
f204e0b8 | 527 | /* Tell PSL where to route data to */ |
4aec6ec0 | 528 | psl_dsnctl |= (chipid << (63-5)); |
aa14138a PB |
529 | psl_dsnctl |= (capp_unit_id << (63-13)); |
530 | ||
f204e0b8 IM |
531 | cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl); |
532 | cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL); | |
533 | /* snoop write mask */ | |
534 | cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL); | |
c6d2ee09 FB |
535 | /* set fir_cntl to recommended value for production env */ |
536 | psl_fircntl = (0x2ULL << (63-3)); /* ce_report */ | |
537 | psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */ | |
538 | psl_fircntl |= 0x1ULL; /* ce_thresh */ | |
539 | cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl); | |
f204e0b8 IM |
540 | /* for debugging with trace arrays */ |
541 | cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL); | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
bdd2e715 | 546 | static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_dev *dev) |
6d382616 FB |
547 | { |
548 | u64 xsl_dsnctl; | |
549 | u64 chipid; | |
f24be42a | 550 | u32 phb_index; |
6d382616 FB |
551 | u64 capp_unit_id; |
552 | int rc; | |
553 | ||
3ced8d73 | 554 | rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id); |
6d382616 FB |
555 | if (rc) |
556 | return rc; | |
557 | ||
558 | /* Tell XSL where to route data to */ | |
559 | xsl_dsnctl = 0x0000600000000000ULL | (chipid << (63-5)); | |
560 | xsl_dsnctl |= (capp_unit_id << (63-13)); | |
561 | cxl_p1_write(adapter, CXL_XSL_DSNCTL, xsl_dsnctl); | |
562 | ||
563 | return 0; | |
564 | } | |
565 | ||
566 | /* PSL & XSL */ | |
567 | #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3)) | |
390fd592 | 568 | #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6)) |
6d382616 FB |
569 | /* For the PSL this is a multiple for 0 < n <= 7: */ |
570 | #define PSL_2048_250MHZ_CYCLES 1 | |
571 | ||
f24be42a CL |
572 | static void write_timebase_ctrl_psl9(struct cxl *adapter) |
573 | { | |
574 | cxl_p1_write(adapter, CXL_PSL9_TB_CTLSTAT, | |
575 | TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES)); | |
576 | } | |
577 | ||
64663f37 | 578 | static void write_timebase_ctrl_psl8(struct cxl *adapter) |
6d382616 FB |
579 | { |
580 | cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT, | |
581 | TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES)); | |
582 | } | |
583 | ||
584 | /* XSL */ | |
585 | #define TBSYNC_ENA (1ULL << 63) | |
586 | /* For the XSL this is 2**n * 2000 clocks for 0 < n <= 6: */ | |
587 | #define XSL_2000_CLOCKS 1 | |
588 | #define XSL_4000_CLOCKS 2 | |
589 | #define XSL_8000_CLOCKS 3 | |
590 | ||
591 | static void write_timebase_ctrl_xsl(struct cxl *adapter) | |
592 | { | |
593 | cxl_p1_write(adapter, CXL_XSL_TB_CTLSTAT, | |
594 | TBSYNC_ENA | | |
595 | TBSYNC_CAL(3) | | |
596 | TBSYNC_CNT(XSL_4000_CLOCKS)); | |
597 | } | |
598 | ||
f24be42a CL |
599 | static u64 timebase_read_psl9(struct cxl *adapter) |
600 | { | |
601 | return cxl_p1_read(adapter, CXL_PSL9_Timebase); | |
602 | } | |
603 | ||
64663f37 | 604 | static u64 timebase_read_psl8(struct cxl *adapter) |
6d382616 FB |
605 | { |
606 | return cxl_p1_read(adapter, CXL_PSL_Timebase); | |
607 | } | |
608 | ||
609 | static u64 timebase_read_xsl(struct cxl *adapter) | |
610 | { | |
611 | return cxl_p1_read(adapter, CXL_XSL_Timebase); | |
612 | } | |
390fd592 | 613 | |
e009a7e8 | 614 | static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev) |
390fd592 PB |
615 | { |
616 | u64 psl_tb; | |
617 | int delta; | |
618 | unsigned int retry = 0; | |
619 | struct device_node *np; | |
620 | ||
e009a7e8 FB |
621 | adapter->psl_timebase_synced = false; |
622 | ||
390fd592 | 623 | if (!(np = pnv_pci_get_phb_node(dev))) |
e009a7e8 | 624 | return; |
390fd592 PB |
625 | |
626 | /* Do not fail when CAPP timebase sync is not supported by OPAL */ | |
627 | of_node_get(np); | |
628 | if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) { | |
629 | of_node_put(np); | |
e009a7e8 FB |
630 | dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n"); |
631 | return; | |
390fd592 PB |
632 | } |
633 | of_node_put(np); | |
634 | ||
635 | /* | |
636 | * Setup PSL Timebase Control and Status register | |
637 | * with the recommended Timebase Sync Count value | |
638 | */ | |
6d382616 | 639 | adapter->native->sl_ops->write_timebase_ctrl(adapter); |
390fd592 PB |
640 | |
641 | /* Enable PSL Timebase */ | |
642 | cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000); | |
643 | cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb); | |
644 | ||
645 | /* Wait until CORE TB and PSL TB difference <= 16usecs */ | |
646 | do { | |
647 | msleep(1); | |
648 | if (retry++ > 5) { | |
e009a7e8 FB |
649 | dev_info(&dev->dev, "PSL timebase can't synchronize\n"); |
650 | return; | |
390fd592 | 651 | } |
6d382616 | 652 | psl_tb = adapter->native->sl_ops->timebase_read(adapter); |
390fd592 PB |
653 | delta = mftb() - psl_tb; |
654 | if (delta < 0) | |
655 | delta = -delta; | |
923adb16 | 656 | } while (tb_to_ns(delta) > 16000); |
390fd592 | 657 | |
e009a7e8 FB |
658 | adapter->psl_timebase_synced = true; |
659 | return; | |
390fd592 PB |
660 | } |
661 | ||
f24be42a CL |
662 | static int init_implementation_afu_regs_psl9(struct cxl_afu *afu) |
663 | { | |
664 | return 0; | |
665 | } | |
666 | ||
64663f37 | 667 | static int init_implementation_afu_regs_psl8(struct cxl_afu *afu) |
f204e0b8 IM |
668 | { |
669 | /* read/write masks for this slice */ | |
670 | cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL); | |
671 | /* APC read/write masks for this slice */ | |
672 | cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL); | |
673 | /* for debugging with trace arrays */ | |
674 | cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL); | |
d6a6af2c | 675 | cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S); |
f204e0b8 IM |
676 | |
677 | return 0; | |
678 | } | |
679 | ||
2b04cf31 FB |
680 | int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, |
681 | unsigned int virq) | |
f204e0b8 IM |
682 | { |
683 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
684 | ||
685 | return pnv_cxl_ioda_msi_setup(dev, hwirq, virq); | |
686 | } | |
687 | ||
4beb5421 RG |
688 | int cxl_update_image_control(struct cxl *adapter) |
689 | { | |
690 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
691 | int rc; | |
692 | int vsec; | |
693 | u8 image_state; | |
694 | ||
695 | if (!(vsec = find_cxl_vsec(dev))) { | |
696 | dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); | |
697 | return -ENODEV; | |
698 | } | |
699 | ||
700 | if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) { | |
701 | dev_err(&dev->dev, "failed to read image state: %i\n", rc); | |
702 | return rc; | |
703 | } | |
704 | ||
705 | if (adapter->perst_loads_image) | |
706 | image_state |= CXL_VSEC_PERST_LOADS_IMAGE; | |
707 | else | |
708 | image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE; | |
709 | ||
710 | if (adapter->perst_select_user) | |
711 | image_state |= CXL_VSEC_PERST_SELECT_USER; | |
712 | else | |
713 | image_state &= ~CXL_VSEC_PERST_SELECT_USER; | |
714 | ||
715 | if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) { | |
716 | dev_err(&dev->dev, "failed to update image control: %i\n", rc); | |
717 | return rc; | |
718 | } | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
2b04cf31 | 723 | int cxl_pci_alloc_one_irq(struct cxl *adapter) |
f204e0b8 IM |
724 | { |
725 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
726 | ||
727 | return pnv_cxl_alloc_hwirqs(dev, 1); | |
728 | } | |
729 | ||
2b04cf31 | 730 | void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq) |
f204e0b8 IM |
731 | { |
732 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
733 | ||
734 | return pnv_cxl_release_hwirqs(dev, hwirq, 1); | |
735 | } | |
736 | ||
2b04cf31 FB |
737 | int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, |
738 | struct cxl *adapter, unsigned int num) | |
f204e0b8 IM |
739 | { |
740 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
741 | ||
742 | return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num); | |
743 | } | |
744 | ||
2b04cf31 FB |
745 | void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, |
746 | struct cxl *adapter) | |
f204e0b8 IM |
747 | { |
748 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
749 | ||
750 | pnv_cxl_release_hwirq_ranges(irqs, dev); | |
751 | } | |
752 | ||
753 | static int setup_cxl_bars(struct pci_dev *dev) | |
754 | { | |
755 | /* Safety check in case we get backported to < 3.17 without M64 */ | |
756 | if ((p1_base(dev) < 0x100000000ULL) || | |
757 | (p2_base(dev) < 0x100000000ULL)) { | |
758 | dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n"); | |
759 | return -ENODEV; | |
760 | } | |
761 | ||
762 | /* | |
763 | * BAR 4/5 has a special meaning for CXL and must be programmed with a | |
764 | * special value corresponding to the CXL protocol address range. | |
f24be42a | 765 | * For POWER 8/9 that means bits 48:49 must be set to 10 |
f204e0b8 IM |
766 | */ |
767 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000); | |
768 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000); | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
b0b5e591 AD |
773 | #ifdef CONFIG_CXL_BIMODAL |
774 | ||
775 | struct cxl_switch_work { | |
776 | struct pci_dev *dev; | |
777 | struct work_struct work; | |
f204e0b8 | 778 | int vsec; |
b0b5e591 AD |
779 | int mode; |
780 | }; | |
781 | ||
782 | static void switch_card_to_cxl(struct work_struct *work) | |
783 | { | |
784 | struct cxl_switch_work *switch_work = | |
785 | container_of(work, struct cxl_switch_work, work); | |
786 | struct pci_dev *dev = switch_work->dev; | |
787 | struct pci_bus *bus = dev->bus; | |
788 | struct pci_controller *hose = pci_bus_to_host(bus); | |
789 | struct pci_dev *bridge; | |
790 | struct pnv_php_slot *php_slot; | |
791 | unsigned int devfn; | |
f204e0b8 IM |
792 | u8 val; |
793 | int rc; | |
794 | ||
b0b5e591 AD |
795 | dev_info(&bus->dev, "cxl: Preparing for mode switch...\n"); |
796 | bridge = list_first_entry_or_null(&hose->bus->devices, struct pci_dev, | |
797 | bus_list); | |
798 | if (!bridge) { | |
799 | dev_WARN(&bus->dev, "cxl: Couldn't find root port!\n"); | |
800 | goto err_dev_put; | |
801 | } | |
f204e0b8 | 802 | |
b0b5e591 AD |
803 | php_slot = pnv_php_find_slot(pci_device_to_OF_node(bridge)); |
804 | if (!php_slot) { | |
805 | dev_err(&bus->dev, "cxl: Failed to find slot hotplug " | |
806 | "information. You may need to upgrade " | |
807 | "skiboot. Aborting.\n"); | |
808 | goto err_dev_put; | |
809 | } | |
810 | ||
811 | rc = CXL_READ_VSEC_MODE_CONTROL(dev, switch_work->vsec, &val); | |
812 | if (rc) { | |
813 | dev_err(&bus->dev, "cxl: Failed to read CAPI mode control: %i\n", rc); | |
814 | goto err_dev_put; | |
815 | } | |
816 | devfn = dev->devfn; | |
817 | ||
818 | /* Release the reference obtained in cxl_check_and_switch_mode() */ | |
819 | pci_dev_put(dev); | |
820 | ||
821 | dev_dbg(&bus->dev, "cxl: Removing PCI devices from kernel\n"); | |
822 | pci_lock_rescan_remove(); | |
823 | pci_hp_remove_devices(bridge->subordinate); | |
824 | pci_unlock_rescan_remove(); | |
825 | ||
826 | /* Switch the CXL protocol on the card */ | |
827 | if (switch_work->mode == CXL_BIMODE_CXL) { | |
828 | dev_info(&bus->dev, "cxl: Switching card to CXL mode\n"); | |
829 | val &= ~CXL_VSEC_PROTOCOL_MASK; | |
830 | val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE; | |
831 | rc = pnv_cxl_enable_phb_kernel_api(hose, true); | |
832 | if (rc) { | |
833 | dev_err(&bus->dev, "cxl: Failed to enable kernel API" | |
834 | " on real PHB, aborting\n"); | |
835 | goto err_free_work; | |
836 | } | |
837 | } else { | |
838 | dev_WARN(&bus->dev, "cxl: Switching card to PCI mode not supported!\n"); | |
839 | goto err_free_work; | |
840 | } | |
841 | ||
842 | rc = CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, switch_work->vsec, val); | |
843 | if (rc) { | |
844 | dev_err(&bus->dev, "cxl: Failed to configure CXL protocol: %i\n", rc); | |
845 | goto err_free_work; | |
846 | } | |
847 | ||
848 | /* | |
849 | * The CAIA spec (v1.1, Section 10.6 Bi-modal Device Support) states | |
850 | * we must wait 100ms after this mode switch before touching PCIe config | |
851 | * space. | |
852 | */ | |
853 | msleep(100); | |
854 | ||
855 | /* | |
856 | * Hot reset to cause the card to come back in cxl mode. A | |
857 | * OPAL_RESET_PCI_LINK would be sufficient, but currently lacks support | |
858 | * in skiboot, so we use a hot reset instead. | |
859 | * | |
860 | * We call pci_set_pcie_reset_state() on the bridge, as a CAPI card is | |
861 | * guaranteed to sit directly under the root port, and setting the reset | |
862 | * state on a device directly under the root port is equivalent to doing | |
863 | * it on the root port iself. | |
864 | */ | |
865 | dev_info(&bus->dev, "cxl: Configuration write complete, resetting card\n"); | |
866 | pci_set_pcie_reset_state(bridge, pcie_hot_reset); | |
867 | pci_set_pcie_reset_state(bridge, pcie_deassert_reset); | |
868 | ||
869 | dev_dbg(&bus->dev, "cxl: Offlining slot\n"); | |
870 | rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_OFFLINE); | |
871 | if (rc) { | |
872 | dev_err(&bus->dev, "cxl: OPAL offlining call failed: %i\n", rc); | |
873 | goto err_free_work; | |
874 | } | |
875 | ||
876 | dev_dbg(&bus->dev, "cxl: Onlining and probing slot\n"); | |
877 | rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_ONLINE); | |
878 | if (rc) { | |
879 | dev_err(&bus->dev, "cxl: OPAL onlining call failed: %i\n", rc); | |
880 | goto err_free_work; | |
881 | } | |
882 | ||
883 | pci_lock_rescan_remove(); | |
884 | pci_hp_add_devices(bridge->subordinate); | |
885 | pci_unlock_rescan_remove(); | |
886 | ||
887 | dev_info(&bus->dev, "cxl: CAPI mode switch completed\n"); | |
888 | kfree(switch_work); | |
889 | return; | |
890 | ||
891 | err_dev_put: | |
892 | /* Release the reference obtained in cxl_check_and_switch_mode() */ | |
893 | pci_dev_put(dev); | |
894 | err_free_work: | |
895 | kfree(switch_work); | |
896 | } | |
897 | ||
898 | int cxl_check_and_switch_mode(struct pci_dev *dev, int mode, int vsec) | |
899 | { | |
900 | struct cxl_switch_work *work; | |
901 | u8 val; | |
902 | int rc; | |
903 | ||
904 | if (!cpu_has_feature(CPU_FTR_HVMODE)) | |
f204e0b8 | 905 | return -ENODEV; |
b0b5e591 AD |
906 | |
907 | if (!vsec) { | |
908 | vsec = find_cxl_vsec(dev); | |
909 | if (!vsec) { | |
910 | dev_info(&dev->dev, "CXL VSEC not found\n"); | |
911 | return -ENODEV; | |
912 | } | |
f204e0b8 IM |
913 | } |
914 | ||
b0b5e591 AD |
915 | rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val); |
916 | if (rc) { | |
917 | dev_err(&dev->dev, "Failed to read current mode control: %i", rc); | |
f204e0b8 IM |
918 | return rc; |
919 | } | |
b0b5e591 AD |
920 | |
921 | if (mode == CXL_BIMODE_PCI) { | |
922 | if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) { | |
923 | dev_info(&dev->dev, "Card is already in PCI mode\n"); | |
924 | return 0; | |
925 | } | |
926 | /* | |
927 | * TODO: Before it's safe to switch the card back to PCI mode | |
928 | * we need to disable the CAPP and make sure any cachelines the | |
929 | * card holds have been flushed out. Needs skiboot support. | |
930 | */ | |
931 | dev_WARN(&dev->dev, "CXL mode switch to PCI unsupported!\n"); | |
932 | return -EIO; | |
f204e0b8 | 933 | } |
b0b5e591 AD |
934 | |
935 | if (val & CXL_VSEC_PROTOCOL_ENABLE) { | |
936 | dev_info(&dev->dev, "Card is already in CXL mode\n"); | |
937 | return 0; | |
938 | } | |
939 | ||
940 | dev_info(&dev->dev, "Card is in PCI mode, scheduling kernel thread " | |
941 | "to switch to CXL mode\n"); | |
942 | ||
943 | work = kmalloc(sizeof(struct cxl_switch_work), GFP_KERNEL); | |
944 | if (!work) | |
945 | return -ENOMEM; | |
946 | ||
947 | pci_dev_get(dev); | |
948 | work->dev = dev; | |
949 | work->vsec = vsec; | |
950 | work->mode = mode; | |
951 | INIT_WORK(&work->work, switch_card_to_cxl); | |
952 | ||
953 | schedule_work(&work->work); | |
954 | ||
f204e0b8 | 955 | /* |
b0b5e591 AD |
956 | * We return a failure now to abort the driver init. Once the |
957 | * link has been cycled and the card is in cxl mode we will | |
958 | * come back (possibly using the generic cxl driver), but | |
959 | * return success as the card should then be in cxl mode. | |
960 | * | |
961 | * TODO: What if the card comes back in PCI mode even after | |
962 | * the switch? Don't want to spin endlessly. | |
f204e0b8 | 963 | */ |
b0b5e591 AD |
964 | return -EBUSY; |
965 | } | |
966 | EXPORT_SYMBOL_GPL(cxl_check_and_switch_mode); | |
967 | ||
968 | #endif /* CONFIG_CXL_BIMODAL */ | |
969 | ||
970 | static int setup_cxl_protocol_area(struct pci_dev *dev) | |
971 | { | |
972 | u8 val; | |
973 | int rc; | |
974 | int vsec = find_cxl_vsec(dev); | |
975 | ||
976 | if (!vsec) { | |
977 | dev_info(&dev->dev, "CXL VSEC not found\n"); | |
978 | return -ENODEV; | |
979 | } | |
980 | ||
981 | rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val); | |
982 | if (rc) { | |
983 | dev_err(&dev->dev, "Failed to read current mode control: %i\n", rc); | |
984 | return rc; | |
985 | } | |
986 | ||
987 | if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) { | |
988 | dev_err(&dev->dev, "Card not in CAPI mode!\n"); | |
989 | return -EIO; | |
990 | } | |
991 | ||
992 | if ((val & CXL_VSEC_PROTOCOL_MASK) != CXL_VSEC_PROTOCOL_256TB) { | |
993 | val &= ~CXL_VSEC_PROTOCOL_MASK; | |
994 | val |= CXL_VSEC_PROTOCOL_256TB; | |
995 | rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val); | |
996 | if (rc) { | |
997 | dev_err(&dev->dev, "Failed to set CXL protocol area: %i\n", rc); | |
998 | return rc; | |
999 | } | |
1000 | } | |
f204e0b8 IM |
1001 | |
1002 | return 0; | |
1003 | } | |
1004 | ||
2b04cf31 | 1005 | static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) |
f204e0b8 IM |
1006 | { |
1007 | u64 p1n_base, p2n_base, afu_desc; | |
1008 | const u64 p1n_size = 0x100; | |
1009 | const u64 p2n_size = 0x1000; | |
1010 | ||
1011 | p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size); | |
1012 | p2n_base = p2_base(dev) + (afu->slice * p2n_size); | |
cbffa3a5 CL |
1013 | afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size)); |
1014 | afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size); | |
f204e0b8 | 1015 | |
cbffa3a5 | 1016 | if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size))) |
f204e0b8 IM |
1017 | goto err; |
1018 | if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size))) | |
1019 | goto err1; | |
1020 | if (afu_desc) { | |
cbffa3a5 | 1021 | if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size))) |
f204e0b8 IM |
1022 | goto err2; |
1023 | } | |
1024 | ||
1025 | return 0; | |
1026 | err2: | |
1027 | iounmap(afu->p2n_mmio); | |
1028 | err1: | |
cbffa3a5 | 1029 | iounmap(afu->native->p1n_mmio); |
f204e0b8 IM |
1030 | err: |
1031 | dev_err(&afu->dev, "Error mapping AFU MMIO regions\n"); | |
1032 | return -ENOMEM; | |
1033 | } | |
1034 | ||
2b04cf31 | 1035 | static void pci_unmap_slice_regs(struct cxl_afu *afu) |
f204e0b8 | 1036 | { |
575e6986 | 1037 | if (afu->p2n_mmio) { |
f204e0b8 | 1038 | iounmap(afu->p2n_mmio); |
575e6986 DA |
1039 | afu->p2n_mmio = NULL; |
1040 | } | |
cbffa3a5 CL |
1041 | if (afu->native->p1n_mmio) { |
1042 | iounmap(afu->native->p1n_mmio); | |
1043 | afu->native->p1n_mmio = NULL; | |
575e6986 | 1044 | } |
cbffa3a5 CL |
1045 | if (afu->native->afu_desc_mmio) { |
1046 | iounmap(afu->native->afu_desc_mmio); | |
1047 | afu->native->afu_desc_mmio = NULL; | |
575e6986 | 1048 | } |
f204e0b8 IM |
1049 | } |
1050 | ||
2b04cf31 | 1051 | void cxl_pci_release_afu(struct device *dev) |
f204e0b8 IM |
1052 | { |
1053 | struct cxl_afu *afu = to_cxl_afu(dev); | |
1054 | ||
2b04cf31 | 1055 | pr_devel("%s\n", __func__); |
f204e0b8 | 1056 | |
bd664f89 | 1057 | idr_destroy(&afu->contexts_idr); |
05155772 DA |
1058 | cxl_release_spa(afu); |
1059 | ||
cbffa3a5 | 1060 | kfree(afu->native); |
f204e0b8 IM |
1061 | kfree(afu); |
1062 | } | |
1063 | ||
f204e0b8 IM |
1064 | /* Expects AFU struct to have recently been zeroed out */ |
1065 | static int cxl_read_afu_descriptor(struct cxl_afu *afu) | |
1066 | { | |
1067 | u64 val; | |
1068 | ||
1069 | val = AFUD_READ_INFO(afu); | |
1070 | afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val); | |
1071 | afu->max_procs_virtualised = AFUD_NUM_PROCS(val); | |
b087e619 | 1072 | afu->crs_num = AFUD_NUM_CRS(val); |
f204e0b8 IM |
1073 | |
1074 | if (AFUD_AFU_DIRECTED(val)) | |
1075 | afu->modes_supported |= CXL_MODE_DIRECTED; | |
1076 | if (AFUD_DEDICATED_PROCESS(val)) | |
1077 | afu->modes_supported |= CXL_MODE_DEDICATED; | |
1078 | if (AFUD_TIME_SLICED(val)) | |
1079 | afu->modes_supported |= CXL_MODE_TIME_SLICED; | |
1080 | ||
1081 | val = AFUD_READ_PPPSA(afu); | |
1082 | afu->pp_size = AFUD_PPPSA_LEN(val) * 4096; | |
1083 | afu->psa = AFUD_PPPSA_PSA(val); | |
1084 | if ((afu->pp_psa = AFUD_PPPSA_PP(val))) | |
cbffa3a5 | 1085 | afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu); |
f204e0b8 | 1086 | |
b087e619 IM |
1087 | val = AFUD_READ_CR(afu); |
1088 | afu->crs_len = AFUD_CR_LEN(val) * 256; | |
1089 | afu->crs_offset = AFUD_READ_CR_OFF(afu); | |
1090 | ||
e36f6fe1 VJ |
1091 | |
1092 | /* eb_len is in multiple of 4K */ | |
1093 | afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096; | |
1094 | afu->eb_offset = AFUD_READ_EB_OFF(afu); | |
1095 | ||
1096 | /* eb_off is 4K aligned so lower 12 bits are always zero */ | |
1097 | if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) { | |
1098 | dev_warn(&afu->dev, | |
1099 | "Invalid AFU error buffer offset %Lx\n", | |
1100 | afu->eb_offset); | |
1101 | dev_info(&afu->dev, | |
1102 | "Ignoring AFU error buffer in the descriptor\n"); | |
1103 | /* indicate that no afu buffer exists */ | |
1104 | afu->eb_len = 0; | |
1105 | } | |
1106 | ||
f204e0b8 IM |
1107 | return 0; |
1108 | } | |
1109 | ||
1110 | static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu) | |
1111 | { | |
5be587b1 FB |
1112 | int i, rc; |
1113 | u32 val; | |
3d5be039 | 1114 | |
f204e0b8 | 1115 | if (afu->psa && afu->adapter->ps_size < |
cbffa3a5 | 1116 | (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) { |
f204e0b8 IM |
1117 | dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n"); |
1118 | return -ENODEV; | |
1119 | } | |
1120 | ||
1121 | if (afu->pp_psa && (afu->pp_size < PAGE_SIZE)) | |
abd1d99b | 1122 | dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size); |
f204e0b8 | 1123 | |
3d5be039 | 1124 | for (i = 0; i < afu->crs_num; i++) { |
5be587b1 FB |
1125 | rc = cxl_ops->afu_cr_read32(afu, i, 0, &val); |
1126 | if (rc || val == 0) { | |
3d5be039 IM |
1127 | dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i); |
1128 | return -EINVAL; | |
1129 | } | |
1130 | } | |
49e9c99f IM |
1131 | |
1132 | if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) { | |
1133 | /* | |
1134 | * We could also check this for the dedicated process model | |
1135 | * since the architecture indicates it should be set to 1, but | |
1136 | * in that case we ignore the value and I'd rather not risk | |
1137 | * breaking any existing dedicated process AFUs that left it as | |
1138 | * 0 (not that I'm aware of any). It is clearly an error for an | |
1139 | * AFU directed AFU to set this to 0, and would have previously | |
1140 | * triggered a bug resulting in the maximum not being enforced | |
1141 | * at all since idr_alloc treats 0 as no maximum. | |
1142 | */ | |
1143 | dev_err(&afu->dev, "AFU does not support any processes\n"); | |
1144 | return -EINVAL; | |
1145 | } | |
3d5be039 | 1146 | |
f204e0b8 IM |
1147 | return 0; |
1148 | } | |
1149 | ||
f24be42a CL |
1150 | static int sanitise_afu_regs_psl9(struct cxl_afu *afu) |
1151 | { | |
1152 | u64 reg; | |
1153 | ||
1154 | /* | |
1155 | * Clear out any regs that contain either an IVTE or address or may be | |
1156 | * waiting on an acknowledgment to try to be a bit safer as we bring | |
1157 | * it online | |
1158 | */ | |
1159 | reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
1160 | if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { | |
1161 | dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); | |
1162 | if (cxl_ops->afu_reset(afu)) | |
1163 | return -EIO; | |
1164 | if (cxl_afu_disable(afu)) | |
1165 | return -EIO; | |
1166 | if (cxl_psl_purge(afu)) | |
1167 | return -EIO; | |
1168 | } | |
1169 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000); | |
1170 | cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000); | |
1171 | reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
1172 | if (reg) { | |
1173 | dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); | |
1174 | if (reg & CXL_PSL9_DSISR_An_TF) | |
1175 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); | |
1176 | else | |
1177 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); | |
1178 | } | |
1179 | if (afu->adapter->native->sl_ops->register_serr_irq) { | |
1180 | reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
1181 | if (reg) { | |
1182 | if (reg & ~0x000000007fffffff) | |
1183 | dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); | |
1184 | cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); | |
1185 | } | |
1186 | } | |
1187 | reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
1188 | if (reg) { | |
1189 | dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); | |
1190 | cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); | |
1191 | } | |
1192 | ||
1193 | return 0; | |
1194 | } | |
1195 | ||
64663f37 | 1196 | static int sanitise_afu_regs_psl8(struct cxl_afu *afu) |
f204e0b8 IM |
1197 | { |
1198 | u64 reg; | |
1199 | ||
1200 | /* | |
1201 | * Clear out any regs that contain either an IVTE or address or may be | |
1202 | * waiting on an acknowledgement to try to be a bit safer as we bring | |
1203 | * it online | |
1204 | */ | |
1205 | reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
1206 | if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { | |
de369538 | 1207 | dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); |
5be587b1 | 1208 | if (cxl_ops->afu_reset(afu)) |
f204e0b8 IM |
1209 | return -EIO; |
1210 | if (cxl_afu_disable(afu)) | |
1211 | return -EIO; | |
1212 | if (cxl_psl_purge(afu)) | |
1213 | return -EIO; | |
1214 | } | |
1215 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000); | |
1216 | cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000); | |
1217 | cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000); | |
1218 | cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000); | |
1219 | cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000); | |
1220 | cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000); | |
1221 | cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000); | |
1222 | cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000); | |
1223 | cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000); | |
1224 | cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000); | |
1225 | cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000); | |
1226 | reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
1227 | if (reg) { | |
de369538 | 1228 | dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); |
f204e0b8 IM |
1229 | if (reg & CXL_PSL_DSISR_TRANS) |
1230 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); | |
1231 | else | |
1232 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); | |
1233 | } | |
6d382616 FB |
1234 | if (afu->adapter->native->sl_ops->register_serr_irq) { |
1235 | reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
1236 | if (reg) { | |
1237 | if (reg & ~0xffff) | |
1238 | dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); | |
1239 | cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); | |
1240 | } | |
f204e0b8 IM |
1241 | } |
1242 | reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
1243 | if (reg) { | |
de369538 | 1244 | dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); |
f204e0b8 IM |
1245 | cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); |
1246 | } | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
e36f6fe1 VJ |
1251 | #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE |
1252 | /* | |
1253 | * afu_eb_read: | |
1254 | * Called from sysfs and reads the afu error info buffer. The h/w only supports | |
1255 | * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte | |
1256 | * aligned the function uses a bounce buffer which can be max PAGE_SIZE. | |
1257 | */ | |
2b04cf31 | 1258 | ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf, |
e36f6fe1 VJ |
1259 | loff_t off, size_t count) |
1260 | { | |
1261 | loff_t aligned_start, aligned_end; | |
1262 | size_t aligned_length; | |
1263 | void *tbuf; | |
cbffa3a5 | 1264 | const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset; |
e36f6fe1 VJ |
1265 | |
1266 | if (count == 0 || off < 0 || (size_t)off >= afu->eb_len) | |
1267 | return 0; | |
1268 | ||
1269 | /* calculate aligned read window */ | |
1270 | count = min((size_t)(afu->eb_len - off), count); | |
1271 | aligned_start = round_down(off, 8); | |
1272 | aligned_end = round_up(off + count, 8); | |
1273 | aligned_length = aligned_end - aligned_start; | |
1274 | ||
1275 | /* max we can copy in one read is PAGE_SIZE */ | |
1276 | if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) { | |
1277 | aligned_length = ERR_BUFF_MAX_COPY_SIZE; | |
1278 | count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7); | |
1279 | } | |
1280 | ||
1281 | /* use bounce buffer for copy */ | |
0ee931c4 | 1282 | tbuf = (void *)__get_free_page(GFP_KERNEL); |
e36f6fe1 VJ |
1283 | if (!tbuf) |
1284 | return -ENOMEM; | |
1285 | ||
1286 | /* perform aligned read from the mmio region */ | |
1287 | memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length); | |
1288 | memcpy(buf, tbuf + (off & 0x7), count); | |
1289 | ||
1290 | free_page((unsigned long)tbuf); | |
1291 | ||
1292 | return count; | |
1293 | } | |
1294 | ||
2b04cf31 | 1295 | static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) |
f204e0b8 | 1296 | { |
f204e0b8 IM |
1297 | int rc; |
1298 | ||
2b04cf31 | 1299 | if ((rc = pci_map_slice_regs(afu, adapter, dev))) |
d76427b0 | 1300 | return rc; |
f204e0b8 | 1301 | |
bdd2e715 CL |
1302 | if (adapter->native->sl_ops->sanitise_afu_regs) { |
1303 | rc = adapter->native->sl_ops->sanitise_afu_regs(afu); | |
1304 | if (rc) | |
1305 | goto err1; | |
1306 | } | |
f204e0b8 IM |
1307 | |
1308 | /* We need to reset the AFU before we can read the AFU descriptor */ | |
5be587b1 | 1309 | if ((rc = cxl_ops->afu_reset(afu))) |
d76427b0 | 1310 | goto err1; |
f204e0b8 IM |
1311 | |
1312 | if (cxl_verbose) | |
1313 | dump_afu_descriptor(afu); | |
1314 | ||
1315 | if ((rc = cxl_read_afu_descriptor(afu))) | |
d76427b0 | 1316 | goto err1; |
f204e0b8 IM |
1317 | |
1318 | if ((rc = cxl_afu_descriptor_looks_ok(afu))) | |
d76427b0 | 1319 | goto err1; |
f204e0b8 | 1320 | |
6d382616 FB |
1321 | if (adapter->native->sl_ops->afu_regs_init) |
1322 | if ((rc = adapter->native->sl_ops->afu_regs_init(afu))) | |
1323 | goto err1; | |
f204e0b8 | 1324 | |
6d382616 FB |
1325 | if (adapter->native->sl_ops->register_serr_irq) |
1326 | if ((rc = adapter->native->sl_ops->register_serr_irq(afu))) | |
1327 | goto err1; | |
f204e0b8 | 1328 | |
2b04cf31 | 1329 | if ((rc = cxl_native_register_psl_irq(afu))) |
d76427b0 DA |
1330 | goto err2; |
1331 | ||
171ed0fc | 1332 | atomic_set(&afu->configured_state, 0); |
d76427b0 DA |
1333 | return 0; |
1334 | ||
1335 | err2: | |
6d382616 FB |
1336 | if (adapter->native->sl_ops->release_serr_irq) |
1337 | adapter->native->sl_ops->release_serr_irq(afu); | |
d76427b0 | 1338 | err1: |
2b04cf31 | 1339 | pci_unmap_slice_regs(afu); |
d76427b0 DA |
1340 | return rc; |
1341 | } | |
1342 | ||
2b04cf31 | 1343 | static void pci_deconfigure_afu(struct cxl_afu *afu) |
d76427b0 | 1344 | { |
171ed0fc AD |
1345 | /* |
1346 | * It's okay to deconfigure when AFU is already locked, otherwise wait | |
1347 | * until there are no readers | |
1348 | */ | |
1349 | if (atomic_read(&afu->configured_state) != -1) { | |
1350 | while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1) | |
1351 | schedule(); | |
1352 | } | |
2b04cf31 | 1353 | cxl_native_release_psl_irq(afu); |
6d382616 FB |
1354 | if (afu->adapter->native->sl_ops->release_serr_irq) |
1355 | afu->adapter->native->sl_ops->release_serr_irq(afu); | |
2b04cf31 | 1356 | pci_unmap_slice_regs(afu); |
d76427b0 DA |
1357 | } |
1358 | ||
2b04cf31 | 1359 | static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev) |
d76427b0 DA |
1360 | { |
1361 | struct cxl_afu *afu; | |
cbffa3a5 | 1362 | int rc = -ENOMEM; |
d76427b0 DA |
1363 | |
1364 | afu = cxl_alloc_afu(adapter, slice); | |
1365 | if (!afu) | |
1366 | return -ENOMEM; | |
1367 | ||
cbffa3a5 CL |
1368 | afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL); |
1369 | if (!afu->native) | |
1370 | goto err_free_afu; | |
1371 | ||
1372 | mutex_init(&afu->native->spa_mutex); | |
1373 | ||
d76427b0 DA |
1374 | rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice); |
1375 | if (rc) | |
cbffa3a5 | 1376 | goto err_free_native; |
d76427b0 | 1377 | |
2b04cf31 | 1378 | rc = pci_configure_afu(afu, adapter, dev); |
d76427b0 | 1379 | if (rc) |
cbffa3a5 | 1380 | goto err_free_native; |
f204e0b8 IM |
1381 | |
1382 | /* Don't care if this fails */ | |
1383 | cxl_debugfs_afu_add(afu); | |
1384 | ||
1385 | /* | |
1386 | * After we call this function we must not free the afu directly, even | |
1387 | * if it returns an error! | |
1388 | */ | |
1389 | if ((rc = cxl_register_afu(afu))) | |
1390 | goto err_put1; | |
1391 | ||
1392 | if ((rc = cxl_sysfs_afu_add(afu))) | |
1393 | goto err_put1; | |
1394 | ||
f204e0b8 IM |
1395 | adapter->afu[afu->slice] = afu; |
1396 | ||
6f7f0b3d MN |
1397 | if ((rc = cxl_pci_vphb_add(afu))) |
1398 | dev_info(&afu->dev, "Can't register vPHB\n"); | |
1399 | ||
f204e0b8 IM |
1400 | return 0; |
1401 | ||
f204e0b8 | 1402 | err_put1: |
2b04cf31 | 1403 | pci_deconfigure_afu(afu); |
f204e0b8 | 1404 | cxl_debugfs_afu_remove(afu); |
d76427b0 | 1405 | device_unregister(&afu->dev); |
f204e0b8 | 1406 | return rc; |
d76427b0 | 1407 | |
cbffa3a5 CL |
1408 | err_free_native: |
1409 | kfree(afu->native); | |
1410 | err_free_afu: | |
d76427b0 DA |
1411 | kfree(afu); |
1412 | return rc; | |
1413 | ||
f204e0b8 IM |
1414 | } |
1415 | ||
2b04cf31 | 1416 | static void cxl_pci_remove_afu(struct cxl_afu *afu) |
f204e0b8 | 1417 | { |
2b04cf31 | 1418 | pr_devel("%s\n", __func__); |
f204e0b8 IM |
1419 | |
1420 | if (!afu) | |
1421 | return; | |
1422 | ||
d601ea91 | 1423 | cxl_pci_vphb_remove(afu); |
f204e0b8 IM |
1424 | cxl_sysfs_afu_remove(afu); |
1425 | cxl_debugfs_afu_remove(afu); | |
1426 | ||
1427 | spin_lock(&afu->adapter->afu_list_lock); | |
1428 | afu->adapter->afu[afu->slice] = NULL; | |
1429 | spin_unlock(&afu->adapter->afu_list_lock); | |
1430 | ||
1431 | cxl_context_detach_all(afu); | |
5be587b1 | 1432 | cxl_ops->afu_deactivate_mode(afu, afu->current_mode); |
f204e0b8 | 1433 | |
2b04cf31 | 1434 | pci_deconfigure_afu(afu); |
f204e0b8 IM |
1435 | device_unregister(&afu->dev); |
1436 | } | |
1437 | ||
2b04cf31 | 1438 | int cxl_pci_reset(struct cxl *adapter) |
62fa19d4 RG |
1439 | { |
1440 | struct pci_dev *dev = to_pci_dev(adapter->dev.parent); | |
1441 | int rc; | |
62fa19d4 | 1442 | |
13e68d8b DA |
1443 | if (adapter->perst_same_image) { |
1444 | dev_warn(&dev->dev, | |
1445 | "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n"); | |
1446 | return -EINVAL; | |
1447 | } | |
1448 | ||
62fa19d4 | 1449 | dev_info(&dev->dev, "CXL reset\n"); |
aaa2245e | 1450 | |
abd1d99b CL |
1451 | /* |
1452 | * The adapter is about to be reset, so ignore errors. | |
f24be42a | 1453 | * Not supported on P9 DD1 |
abd1d99b | 1454 | */ |
797625de | 1455 | if ((cxl_is_power8()) || (!(cxl_is_power9_dd1()))) |
abd1d99b | 1456 | cxl_data_cache_flush(adapter); |
62fa19d4 | 1457 | |
62fa19d4 RG |
1458 | /* pcie_warm_reset requests a fundamental pci reset which includes a |
1459 | * PERST assert/deassert. PERST triggers a loading of the image | |
1460 | * if "user" or "factory" is selected in sysfs */ | |
1461 | if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) { | |
1462 | dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n"); | |
1463 | return rc; | |
1464 | } | |
1465 | ||
62fa19d4 RG |
1466 | return rc; |
1467 | } | |
f204e0b8 IM |
1468 | |
1469 | static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev) | |
1470 | { | |
1471 | if (pci_request_region(dev, 2, "priv 2 regs")) | |
1472 | goto err1; | |
1473 | if (pci_request_region(dev, 0, "priv 1 regs")) | |
1474 | goto err2; | |
1475 | ||
de369538 | 1476 | pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx", |
f204e0b8 IM |
1477 | p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev)); |
1478 | ||
cbffa3a5 | 1479 | if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev)))) |
f204e0b8 IM |
1480 | goto err3; |
1481 | ||
cbffa3a5 | 1482 | if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev)))) |
f204e0b8 IM |
1483 | goto err4; |
1484 | ||
1485 | return 0; | |
1486 | ||
1487 | err4: | |
cbffa3a5 CL |
1488 | iounmap(adapter->native->p1_mmio); |
1489 | adapter->native->p1_mmio = NULL; | |
f204e0b8 IM |
1490 | err3: |
1491 | pci_release_region(dev, 0); | |
1492 | err2: | |
1493 | pci_release_region(dev, 2); | |
1494 | err1: | |
1495 | return -ENOMEM; | |
1496 | } | |
1497 | ||
1498 | static void cxl_unmap_adapter_regs(struct cxl *adapter) | |
1499 | { | |
cbffa3a5 CL |
1500 | if (adapter->native->p1_mmio) { |
1501 | iounmap(adapter->native->p1_mmio); | |
1502 | adapter->native->p1_mmio = NULL; | |
575e6986 DA |
1503 | pci_release_region(to_pci_dev(adapter->dev.parent), 2); |
1504 | } | |
cbffa3a5 CL |
1505 | if (adapter->native->p2_mmio) { |
1506 | iounmap(adapter->native->p2_mmio); | |
1507 | adapter->native->p2_mmio = NULL; | |
575e6986 DA |
1508 | pci_release_region(to_pci_dev(adapter->dev.parent), 0); |
1509 | } | |
f204e0b8 IM |
1510 | } |
1511 | ||
1512 | static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev) | |
1513 | { | |
1514 | int vsec; | |
1515 | u32 afu_desc_off, afu_desc_size; | |
1516 | u32 ps_off, ps_size; | |
1517 | u16 vseclen; | |
1518 | u8 image_state; | |
1519 | ||
1520 | if (!(vsec = find_cxl_vsec(dev))) { | |
bee30c70 | 1521 | dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); |
f204e0b8 IM |
1522 | return -ENODEV; |
1523 | } | |
1524 | ||
1525 | CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen); | |
1526 | if (vseclen < CXL_VSEC_MIN_SIZE) { | |
bee30c70 | 1527 | dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n"); |
f204e0b8 IM |
1528 | return -EINVAL; |
1529 | } | |
1530 | ||
1531 | CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status); | |
1532 | CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev); | |
1533 | CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major); | |
1534 | CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor); | |
1535 | CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image); | |
1536 | CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state); | |
1537 | adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); | |
4beb5421 | 1538 | adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); |
aba81433 | 1539 | adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE); |
f204e0b8 IM |
1540 | |
1541 | CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); | |
1542 | CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off); | |
1543 | CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size); | |
1544 | CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off); | |
1545 | CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size); | |
1546 | ||
1547 | /* Convert everything to bytes, because there is NO WAY I'd look at the | |
1548 | * code a month later and forget what units these are in ;-) */ | |
cbffa3a5 | 1549 | adapter->native->ps_off = ps_off * 64 * 1024; |
f204e0b8 | 1550 | adapter->ps_size = ps_size * 64 * 1024; |
cbffa3a5 CL |
1551 | adapter->native->afu_desc_off = afu_desc_off * 64 * 1024; |
1552 | adapter->native->afu_desc_size = afu_desc_size * 64 * 1024; | |
f204e0b8 IM |
1553 | |
1554 | /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */ | |
1555 | adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; | |
1556 | ||
1557 | return 0; | |
1558 | } | |
1559 | ||
d79e6801 PB |
1560 | /* |
1561 | * Workaround a PCIe Host Bridge defect on some cards, that can cause | |
1562 | * malformed Transaction Layer Packet (TLP) errors to be erroneously | |
1563 | * reported. Mask this error in the Uncorrectable Error Mask Register. | |
1564 | * | |
1565 | * The upper nibble of the PSL revision is used to distinguish between | |
1566 | * different cards. The affected ones have it set to 0. | |
1567 | */ | |
1568 | static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev) | |
1569 | { | |
1570 | int aer; | |
1571 | u32 data; | |
1572 | ||
1573 | if (adapter->psl_rev & 0xf000) | |
1574 | return; | |
1575 | if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))) | |
1576 | return; | |
1577 | pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data); | |
1578 | if (data & PCI_ERR_UNC_MALF_TLP) | |
1579 | if (data & PCI_ERR_UNC_INTN) | |
1580 | return; | |
1581 | data |= PCI_ERR_UNC_MALF_TLP; | |
1582 | data |= PCI_ERR_UNC_INTN; | |
1583 | pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data); | |
1584 | } | |
1585 | ||
abd1d99b CL |
1586 | static bool cxl_compatible_caia_version(struct cxl *adapter) |
1587 | { | |
1588 | if (cxl_is_power8() && (adapter->caia_major == 1)) | |
1589 | return true; | |
1590 | ||
f24be42a CL |
1591 | if (cxl_is_power9() && (adapter->caia_major == 2)) |
1592 | return true; | |
1593 | ||
abd1d99b CL |
1594 | return false; |
1595 | } | |
1596 | ||
f204e0b8 IM |
1597 | static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev) |
1598 | { | |
1599 | if (adapter->vsec_status & CXL_STATUS_SECOND_PORT) | |
1600 | return -EBUSY; | |
1601 | ||
1602 | if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) { | |
bee30c70 | 1603 | dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n"); |
f204e0b8 IM |
1604 | return -EINVAL; |
1605 | } | |
1606 | ||
abd1d99b CL |
1607 | if (!cxl_compatible_caia_version(adapter)) { |
1608 | dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n", | |
1609 | adapter->caia_major); | |
1610 | return -ENODEV; | |
1611 | } | |
1612 | ||
f204e0b8 IM |
1613 | if (!adapter->slices) { |
1614 | /* Once we support dynamic reprogramming we can use the card if | |
1615 | * it supports loadable AFUs */ | |
bee30c70 | 1616 | dev_err(&dev->dev, "ABORTING: Device has no AFUs\n"); |
f204e0b8 IM |
1617 | return -EINVAL; |
1618 | } | |
1619 | ||
cbffa3a5 | 1620 | if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) { |
bee30c70 | 1621 | dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n"); |
f204e0b8 IM |
1622 | return -EINVAL; |
1623 | } | |
1624 | ||
cbffa3a5 | 1625 | if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) { |
bee30c70 | 1626 | dev_err(&dev->dev, "ABORTING: Problem state size larger than " |
f204e0b8 | 1627 | "available in BAR2: 0x%llx > 0x%llx\n", |
cbffa3a5 | 1628 | adapter->ps_size, p2_size(dev) - adapter->native->ps_off); |
f204e0b8 IM |
1629 | return -EINVAL; |
1630 | } | |
1631 | ||
1632 | return 0; | |
1633 | } | |
1634 | ||
d601ea91 FB |
1635 | ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len) |
1636 | { | |
1637 | return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf); | |
1638 | } | |
1639 | ||
f204e0b8 IM |
1640 | static void cxl_release_adapter(struct device *dev) |
1641 | { | |
1642 | struct cxl *adapter = to_cxl_adapter(dev); | |
1643 | ||
1644 | pr_devel("cxl_release_adapter\n"); | |
1645 | ||
c044c415 DA |
1646 | cxl_remove_adapter_nr(adapter); |
1647 | ||
cbffa3a5 | 1648 | kfree(adapter->native); |
f204e0b8 IM |
1649 | kfree(adapter); |
1650 | } | |
1651 | ||
390fd592 PB |
1652 | #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31)) |
1653 | ||
f204e0b8 IM |
1654 | static int sanitise_adapter_regs(struct cxl *adapter) |
1655 | { | |
bdd2e715 CL |
1656 | int rc = 0; |
1657 | ||
390fd592 PB |
1658 | /* Clear PSL tberror bit by writing 1 to it */ |
1659 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror); | |
bdd2e715 | 1660 | |
f24be42a CL |
1661 | if (adapter->native->sl_ops->invalidate_all) { |
1662 | /* do not invalidate ERAT entries when not reloading on PERST */ | |
1663 | if (cxl_is_power9() && (adapter->perst_loads_image)) | |
1664 | return 0; | |
bdd2e715 | 1665 | rc = adapter->native->sl_ops->invalidate_all(adapter); |
f24be42a | 1666 | } |
bdd2e715 CL |
1667 | |
1668 | return rc; | |
f204e0b8 IM |
1669 | } |
1670 | ||
c044c415 DA |
1671 | /* This should contain *only* operations that can safely be done in |
1672 | * both creation and recovery. | |
1673 | */ | |
1674 | static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev) | |
f204e0b8 | 1675 | { |
f204e0b8 IM |
1676 | int rc; |
1677 | ||
c044c415 DA |
1678 | adapter->dev.parent = &dev->dev; |
1679 | adapter->dev.release = cxl_release_adapter; | |
1680 | pci_set_drvdata(dev, adapter); | |
f204e0b8 | 1681 | |
c044c415 DA |
1682 | rc = pci_enable_device(dev); |
1683 | if (rc) { | |
1684 | dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc); | |
1685 | return rc; | |
1686 | } | |
f204e0b8 | 1687 | |
bee30c70 | 1688 | if ((rc = cxl_read_vsec(adapter, dev))) |
c044c415 | 1689 | return rc; |
bee30c70 IM |
1690 | |
1691 | if ((rc = cxl_vsec_looks_ok(adapter, dev))) | |
c044c415 | 1692 | return rc; |
bee30c70 | 1693 | |
d79e6801 PB |
1694 | cxl_fixup_malformed_tlp(adapter, dev); |
1695 | ||
bee30c70 | 1696 | if ((rc = setup_cxl_bars(dev))) |
c044c415 | 1697 | return rc; |
bee30c70 | 1698 | |
b0b5e591 | 1699 | if ((rc = setup_cxl_protocol_area(dev))) |
c044c415 | 1700 | return rc; |
f204e0b8 | 1701 | |
4beb5421 | 1702 | if ((rc = cxl_update_image_control(adapter))) |
c044c415 | 1703 | return rc; |
4beb5421 | 1704 | |
f204e0b8 | 1705 | if ((rc = cxl_map_adapter_regs(adapter, dev))) |
c044c415 | 1706 | return rc; |
f204e0b8 IM |
1707 | |
1708 | if ((rc = sanitise_adapter_regs(adapter))) | |
c044c415 | 1709 | goto err; |
f204e0b8 | 1710 | |
6d382616 | 1711 | if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev))) |
c044c415 | 1712 | goto err; |
f204e0b8 | 1713 | |
48b3adf3 IM |
1714 | /* Required for devices using CAPP DMA mode, harmless for others */ |
1715 | pci_set_master(dev); | |
1716 | ||
b385c9e9 | 1717 | if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode))) |
c044c415 | 1718 | goto err; |
f204e0b8 | 1719 | |
1212aa1c RG |
1720 | /* If recovery happened, the last step is to turn on snooping. |
1721 | * In the non-recovery case this has no effect */ | |
c044c415 DA |
1722 | if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) |
1723 | goto err; | |
1212aa1c | 1724 | |
e009a7e8 FB |
1725 | /* Ignore error, adapter init is not dependant on timebase sync */ |
1726 | cxl_setup_psl_timebase(adapter, dev); | |
390fd592 | 1727 | |
2b04cf31 | 1728 | if ((rc = cxl_native_register_psl_err_irq(adapter))) |
c044c415 DA |
1729 | goto err; |
1730 | ||
1731 | return 0; | |
1732 | ||
1733 | err: | |
1734 | cxl_unmap_adapter_regs(adapter); | |
1735 | return rc; | |
1736 | ||
1737 | } | |
1738 | ||
1739 | static void cxl_deconfigure_adapter(struct cxl *adapter) | |
1740 | { | |
1741 | struct pci_dev *pdev = to_pci_dev(adapter->dev.parent); | |
1742 | ||
2b04cf31 | 1743 | cxl_native_release_psl_err_irq(adapter); |
c044c415 DA |
1744 | cxl_unmap_adapter_regs(adapter); |
1745 | ||
1746 | pci_disable_device(pdev); | |
1747 | } | |
1748 | ||
f24be42a CL |
1749 | static const struct cxl_service_layer_ops psl9_ops = { |
1750 | .adapter_regs_init = init_implementation_adapter_regs_psl9, | |
1751 | .invalidate_all = cxl_invalidate_all_psl9, | |
1752 | .afu_regs_init = init_implementation_afu_regs_psl9, | |
1753 | .sanitise_afu_regs = sanitise_afu_regs_psl9, | |
6d382616 FB |
1754 | .register_serr_irq = cxl_native_register_serr_irq, |
1755 | .release_serr_irq = cxl_native_release_serr_irq, | |
f24be42a CL |
1756 | .handle_interrupt = cxl_irq_psl9, |
1757 | .fail_irq = cxl_fail_irq_psl, | |
1758 | .activate_dedicated_process = cxl_activate_dedicated_process_psl9, | |
1759 | .attach_afu_directed = cxl_attach_afu_directed_psl9, | |
1760 | .attach_dedicated_process = cxl_attach_dedicated_process_psl9, | |
1761 | .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9, | |
1762 | .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9, | |
1763 | .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9, | |
1764 | .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9, | |
f24be42a CL |
1765 | .debugfs_stop_trace = cxl_stop_trace_psl9, |
1766 | .write_timebase_ctrl = write_timebase_ctrl_psl9, | |
1767 | .timebase_read = timebase_read_psl9, | |
1768 | .capi_mode = OPAL_PHB_CAPI_MODE_CAPI, | |
1769 | .needs_reset_before_disable = true, | |
1770 | }; | |
1771 | ||
64663f37 CL |
1772 | static const struct cxl_service_layer_ops psl8_ops = { |
1773 | .adapter_regs_init = init_implementation_adapter_regs_psl8, | |
1774 | .invalidate_all = cxl_invalidate_all_psl8, | |
1775 | .afu_regs_init = init_implementation_afu_regs_psl8, | |
1776 | .sanitise_afu_regs = sanitise_afu_regs_psl8, | |
6d382616 FB |
1777 | .register_serr_irq = cxl_native_register_serr_irq, |
1778 | .release_serr_irq = cxl_native_release_serr_irq, | |
64663f37 | 1779 | .handle_interrupt = cxl_irq_psl8, |
bdd2e715 | 1780 | .fail_irq = cxl_fail_irq_psl, |
64663f37 CL |
1781 | .activate_dedicated_process = cxl_activate_dedicated_process_psl8, |
1782 | .attach_afu_directed = cxl_attach_afu_directed_psl8, | |
1783 | .attach_dedicated_process = cxl_attach_dedicated_process_psl8, | |
1784 | .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8, | |
1785 | .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8, | |
1786 | .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8, | |
1787 | .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8, | |
6d382616 | 1788 | .err_irq_dump_registers = cxl_native_err_irq_dump_regs, |
64663f37 CL |
1789 | .debugfs_stop_trace = cxl_stop_trace_psl8, |
1790 | .write_timebase_ctrl = write_timebase_ctrl_psl8, | |
1791 | .timebase_read = timebase_read_psl8, | |
b385c9e9 | 1792 | .capi_mode = OPAL_PHB_CAPI_MODE_CAPI, |
5e7823c9 | 1793 | .needs_reset_before_disable = true, |
6d382616 FB |
1794 | }; |
1795 | ||
1796 | static const struct cxl_service_layer_ops xsl_ops = { | |
bdd2e715 | 1797 | .adapter_regs_init = init_implementation_adapter_regs_xsl, |
64663f37 CL |
1798 | .invalidate_all = cxl_invalidate_all_psl8, |
1799 | .sanitise_afu_regs = sanitise_afu_regs_psl8, | |
1800 | .handle_interrupt = cxl_irq_psl8, | |
bdd2e715 | 1801 | .fail_irq = cxl_fail_irq_psl, |
64663f37 CL |
1802 | .activate_dedicated_process = cxl_activate_dedicated_process_psl8, |
1803 | .attach_afu_directed = cxl_attach_afu_directed_psl8, | |
1804 | .attach_dedicated_process = cxl_attach_dedicated_process_psl8, | |
1805 | .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8, | |
bdd2e715 | 1806 | .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_xsl, |
6d382616 FB |
1807 | .write_timebase_ctrl = write_timebase_ctrl_xsl, |
1808 | .timebase_read = timebase_read_xsl, | |
b385c9e9 | 1809 | .capi_mode = OPAL_PHB_CAPI_MODE_DMA, |
6d382616 FB |
1810 | }; |
1811 | ||
1812 | static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev) | |
1813 | { | |
1814 | if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) { | |
16479337 | 1815 | /* Mellanox CX-4 */ |
b135077b | 1816 | dev_info(&dev->dev, "Device uses an XSL\n"); |
6d382616 | 1817 | adapter->native->sl_ops = &xsl_ops; |
16479337 | 1818 | adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */ |
6d382616 | 1819 | } else { |
abd1d99b CL |
1820 | if (cxl_is_power8()) { |
1821 | dev_info(&dev->dev, "Device uses a PSL8\n"); | |
1822 | adapter->native->sl_ops = &psl8_ops; | |
f24be42a CL |
1823 | } else { |
1824 | dev_info(&dev->dev, "Device uses a PSL9\n"); | |
1825 | adapter->native->sl_ops = &psl9_ops; | |
abd1d99b | 1826 | } |
6d382616 FB |
1827 | } |
1828 | } | |
1829 | ||
1830 | ||
2b04cf31 | 1831 | static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev) |
c044c415 DA |
1832 | { |
1833 | struct cxl *adapter; | |
1834 | int rc; | |
1835 | ||
1836 | adapter = cxl_alloc_adapter(); | |
1837 | if (!adapter) | |
1838 | return ERR_PTR(-ENOMEM); | |
1839 | ||
cbffa3a5 CL |
1840 | adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL); |
1841 | if (!adapter->native) { | |
1842 | rc = -ENOMEM; | |
1843 | goto err_release; | |
1844 | } | |
1845 | ||
6d382616 FB |
1846 | set_sl_ops(adapter, dev); |
1847 | ||
c044c415 DA |
1848 | /* Set defaults for parameters which need to persist over |
1849 | * configure/reconfigure | |
1850 | */ | |
1851 | adapter->perst_loads_image = true; | |
13e68d8b | 1852 | adapter->perst_same_image = false; |
c044c415 DA |
1853 | |
1854 | rc = cxl_configure_adapter(adapter, dev); | |
1855 | if (rc) { | |
1856 | pci_disable_device(dev); | |
cbffa3a5 | 1857 | goto err_release; |
c044c415 | 1858 | } |
f204e0b8 IM |
1859 | |
1860 | /* Don't care if this one fails: */ | |
1861 | cxl_debugfs_adapter_add(adapter); | |
1862 | ||
1863 | /* | |
1864 | * After we call this function we must not free the adapter directly, | |
1865 | * even if it returns an error! | |
1866 | */ | |
1867 | if ((rc = cxl_register_adapter(adapter))) | |
1868 | goto err_put1; | |
1869 | ||
1870 | if ((rc = cxl_sysfs_adapter_add(adapter))) | |
1871 | goto err_put1; | |
1872 | ||
ea9a26d1 VJ |
1873 | /* Release the context lock as adapter is configured */ |
1874 | cxl_adapter_context_unlock(adapter); | |
1875 | ||
f204e0b8 IM |
1876 | return adapter; |
1877 | ||
1878 | err_put1: | |
c044c415 DA |
1879 | /* This should mirror cxl_remove_adapter, except without the |
1880 | * sysfs parts | |
1881 | */ | |
f204e0b8 | 1882 | cxl_debugfs_adapter_remove(adapter); |
c044c415 DA |
1883 | cxl_deconfigure_adapter(adapter); |
1884 | device_unregister(&adapter->dev); | |
f204e0b8 | 1885 | return ERR_PTR(rc); |
cbffa3a5 CL |
1886 | |
1887 | err_release: | |
1888 | cxl_release_adapter(&adapter->dev); | |
1889 | return ERR_PTR(rc); | |
f204e0b8 IM |
1890 | } |
1891 | ||
2b04cf31 | 1892 | static void cxl_pci_remove_adapter(struct cxl *adapter) |
f204e0b8 | 1893 | { |
c044c415 | 1894 | pr_devel("cxl_remove_adapter\n"); |
f204e0b8 IM |
1895 | |
1896 | cxl_sysfs_adapter_remove(adapter); | |
1897 | cxl_debugfs_adapter_remove(adapter); | |
f204e0b8 | 1898 | |
f24be42a CL |
1899 | /* |
1900 | * Flush adapter datacache as its about to be removed. | |
1901 | * Not supported on P9 DD1. | |
1902 | */ | |
797625de | 1903 | if ((cxl_is_power8()) || (!(cxl_is_power9_dd1()))) |
f24be42a | 1904 | cxl_data_cache_flush(adapter); |
d7b1946c | 1905 | |
c044c415 | 1906 | cxl_deconfigure_adapter(adapter); |
f204e0b8 | 1907 | |
c044c415 | 1908 | device_unregister(&adapter->dev); |
f204e0b8 IM |
1909 | } |
1910 | ||
3b3dcd61 PB |
1911 | #define CXL_MAX_PCIEX_PARENT 2 |
1912 | ||
3ced8d73 | 1913 | int cxl_slot_is_switched(struct pci_dev *dev) |
3b3dcd61 PB |
1914 | { |
1915 | struct device_node *np; | |
1916 | int depth = 0; | |
1917 | const __be32 *prop; | |
1918 | ||
1919 | if (!(np = pci_device_to_OF_node(dev))) { | |
1920 | pr_err("cxl: np = NULL\n"); | |
1921 | return -ENODEV; | |
1922 | } | |
1923 | of_node_get(np); | |
1924 | while (np) { | |
1925 | np = of_get_next_parent(np); | |
1926 | prop = of_get_property(np, "device_type", NULL); | |
1927 | if (!prop || strcmp((char *)prop, "pciex")) | |
1928 | break; | |
1929 | depth++; | |
1930 | } | |
1931 | of_node_put(np); | |
1932 | return (depth > CXL_MAX_PCIEX_PARENT); | |
1933 | } | |
1934 | ||
4e56f858 IM |
1935 | bool cxl_slot_is_supported(struct pci_dev *dev, int flags) |
1936 | { | |
1937 | if (!cpu_has_feature(CPU_FTR_HVMODE)) | |
1938 | return false; | |
1939 | ||
1940 | if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) { | |
1941 | /* | |
1942 | * CAPP DMA mode is technically supported on regular P8, but | |
1943 | * will EEH if the card attempts to access memory < 4GB, which | |
1944 | * we cannot realistically avoid. We might be able to work | |
1945 | * around the issue, but until then return unsupported: | |
1946 | */ | |
1947 | return false; | |
1948 | } | |
1949 | ||
1950 | if (cxl_slot_is_switched(dev)) | |
1951 | return false; | |
1952 | ||
1953 | /* | |
1954 | * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since | |
1955 | * the CAPP can be connected to PHB 0, 1 or 2 on a first come first | |
1956 | * served basis, which is racy to check from here. If we need to | |
1957 | * support this in future we might need to consider having this | |
1958 | * function effectively reserve it ahead of time. | |
1959 | * | |
1960 | * Currently, the only user of this API is the Mellanox CX4, which is | |
1961 | * only supported on P8NVL due to the above mentioned limitation of | |
1962 | * CAPP DMA mode and therefore does not need to worry about this. If the | |
1963 | * issue with CAPP DMA mode is later worked around on P8 we might need | |
1964 | * to revisit this. | |
1965 | */ | |
1966 | ||
1967 | return true; | |
1968 | } | |
1969 | EXPORT_SYMBOL_GPL(cxl_slot_is_supported); | |
1970 | ||
1971 | ||
f204e0b8 IM |
1972 | static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1973 | { | |
1974 | struct cxl *adapter; | |
1975 | int slice; | |
1976 | int rc; | |
1977 | ||
17eb3eef VJ |
1978 | if (cxl_pci_is_vphb_device(dev)) { |
1979 | dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n"); | |
1980 | return -ENODEV; | |
1981 | } | |
1982 | ||
3b3dcd61 PB |
1983 | if (cxl_slot_is_switched(dev)) { |
1984 | dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n"); | |
1985 | return -ENODEV; | |
1986 | } | |
1987 | ||
f24be42a CL |
1988 | if (cxl_is_power9() && !radix_enabled()) { |
1989 | dev_info(&dev->dev, "Only Radix mode supported\n"); | |
1990 | return -ENODEV; | |
1991 | } | |
1992 | ||
f204e0b8 IM |
1993 | if (cxl_verbose) |
1994 | dump_cxl_config_space(dev); | |
1995 | ||
2b04cf31 | 1996 | adapter = cxl_pci_init_adapter(dev); |
f204e0b8 IM |
1997 | if (IS_ERR(adapter)) { |
1998 | dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter)); | |
1999 | return PTR_ERR(adapter); | |
2000 | } | |
2001 | ||
2002 | for (slice = 0; slice < adapter->slices; slice++) { | |
2b04cf31 | 2003 | if ((rc = pci_init_afu(adapter, slice, dev))) { |
f204e0b8 | 2004 | dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc); |
d76427b0 DA |
2005 | continue; |
2006 | } | |
2007 | ||
2008 | rc = cxl_afu_select_best_mode(adapter->afu[slice]); | |
2009 | if (rc) | |
2010 | dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc); | |
f204e0b8 IM |
2011 | } |
2012 | ||
317f5ef1 IM |
2013 | if (pnv_pci_on_cxl_phb(dev) && adapter->slices >= 1) |
2014 | pnv_cxl_phb_set_peer_afu(dev, adapter->afu[0]); | |
2015 | ||
f204e0b8 IM |
2016 | return 0; |
2017 | } | |
2018 | ||
2019 | static void cxl_remove(struct pci_dev *dev) | |
2020 | { | |
2021 | struct cxl *adapter = pci_get_drvdata(dev); | |
6f7f0b3d MN |
2022 | struct cxl_afu *afu; |
2023 | int i; | |
f204e0b8 | 2024 | |
f204e0b8 IM |
2025 | /* |
2026 | * Lock to prevent someone grabbing a ref through the adapter list as | |
2027 | * we are removing it | |
2028 | */ | |
6f7f0b3d MN |
2029 | for (i = 0; i < adapter->slices; i++) { |
2030 | afu = adapter->afu[i]; | |
2b04cf31 | 2031 | cxl_pci_remove_afu(afu); |
6f7f0b3d | 2032 | } |
2b04cf31 | 2033 | cxl_pci_remove_adapter(adapter); |
f204e0b8 IM |
2034 | } |
2035 | ||
9e8df8a2 DA |
2036 | static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu, |
2037 | pci_channel_state_t state) | |
2038 | { | |
2039 | struct pci_dev *afu_dev; | |
2040 | pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET; | |
2041 | pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET; | |
2042 | ||
2043 | /* There should only be one entry, but go through the list | |
2044 | * anyway | |
2045 | */ | |
2046 | list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { | |
2047 | if (!afu_dev->driver) | |
2048 | continue; | |
2049 | ||
2050 | afu_dev->error_state = state; | |
2051 | ||
2052 | if (afu_dev->driver->err_handler) | |
2053 | afu_result = afu_dev->driver->err_handler->error_detected(afu_dev, | |
2054 | state); | |
2055 | /* Disconnect trumps all, NONE trumps NEED_RESET */ | |
2056 | if (afu_result == PCI_ERS_RESULT_DISCONNECT) | |
2057 | result = PCI_ERS_RESULT_DISCONNECT; | |
2058 | else if ((afu_result == PCI_ERS_RESULT_NONE) && | |
2059 | (result == PCI_ERS_RESULT_NEED_RESET)) | |
2060 | result = PCI_ERS_RESULT_NONE; | |
2061 | } | |
2062 | return result; | |
2063 | } | |
2064 | ||
2065 | static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, | |
2066 | pci_channel_state_t state) | |
2067 | { | |
2068 | struct cxl *adapter = pci_get_drvdata(pdev); | |
2069 | struct cxl_afu *afu; | |
4f58f0bf | 2070 | pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET, afu_result; |
9e8df8a2 DA |
2071 | int i; |
2072 | ||
2073 | /* At this point, we could still have an interrupt pending. | |
2074 | * Let's try to get them out of the way before they do | |
2075 | * anything we don't like. | |
2076 | */ | |
2077 | schedule(); | |
2078 | ||
2079 | /* If we're permanently dead, give up. */ | |
2080 | if (state == pci_channel_io_perm_failure) { | |
9e8df8a2 DA |
2081 | for (i = 0; i < adapter->slices; i++) { |
2082 | afu = adapter->afu[i]; | |
07f5ab60 VJ |
2083 | /* |
2084 | * Tell the AFU drivers; but we don't care what they | |
2085 | * say, we're going away. | |
2086 | */ | |
2087 | if (afu->phb != NULL) | |
2088 | cxl_vphb_error_detected(afu, state); | |
9e8df8a2 DA |
2089 | } |
2090 | return PCI_ERS_RESULT_DISCONNECT; | |
2091 | } | |
2092 | ||
2093 | /* Are we reflashing? | |
2094 | * | |
2095 | * If we reflash, we could come back as something entirely | |
2096 | * different, including a non-CAPI card. As such, by default | |
2097 | * we don't participate in the process. We'll be unbound and | |
2098 | * the slot re-probed. (TODO: check EEH doesn't blindly rebind | |
2099 | * us!) | |
2100 | * | |
2101 | * However, this isn't the entire story: for reliablity | |
2102 | * reasons, we usually want to reflash the FPGA on PERST in | |
2103 | * order to get back to a more reliable known-good state. | |
2104 | * | |
2105 | * This causes us a bit of a problem: if we reflash we can't | |
2106 | * trust that we'll come back the same - we could have a new | |
2107 | * image and been PERSTed in order to load that | |
2108 | * image. However, most of the time we actually *will* come | |
2109 | * back the same - for example a regular EEH event. | |
2110 | * | |
2111 | * Therefore, we allow the user to assert that the image is | |
2112 | * indeed the same and that we should continue on into EEH | |
2113 | * anyway. | |
2114 | */ | |
2115 | if (adapter->perst_loads_image && !adapter->perst_same_image) { | |
2116 | /* TODO take the PHB out of CXL mode */ | |
2117 | dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n"); | |
2118 | return PCI_ERS_RESULT_NONE; | |
2119 | } | |
2120 | ||
2121 | /* | |
2122 | * At this point, we want to try to recover. We'll always | |
2123 | * need a complete slot reset: we don't trust any other reset. | |
2124 | * | |
2125 | * Now, we go through each AFU: | |
2126 | * - We send the driver, if bound, an error_detected callback. | |
2127 | * We expect it to clean up, but it can also tell us to give | |
2128 | * up and permanently detach the card. To simplify things, if | |
2129 | * any bound AFU driver doesn't support EEH, we give up on EEH. | |
2130 | * | |
2131 | * - We detach all contexts associated with the AFU. This | |
2132 | * does not free them, but puts them into a CLOSED state | |
2133 | * which causes any the associated files to return useful | |
2134 | * errors to userland. It also unmaps, but does not free, | |
2135 | * any IRQs. | |
2136 | * | |
2137 | * - We clean up our side: releasing and unmapping resources we hold | |
2138 | * so we can wire them up again when the hardware comes back up. | |
2139 | * | |
2140 | * Driver authors should note: | |
2141 | * | |
2142 | * - Any contexts you create in your kernel driver (except | |
2143 | * those associated with anonymous file descriptors) are | |
2144 | * your responsibility to free and recreate. Likewise with | |
2145 | * any attached resources. | |
2146 | * | |
2147 | * - We will take responsibility for re-initialising the | |
2148 | * device context (the one set up for you in | |
2149 | * cxl_pci_enable_device_hook and accessed through | |
2150 | * cxl_get_context). If you've attached IRQs or other | |
2151 | * resources to it, they remains yours to free. | |
2152 | * | |
2153 | * You can call the same functions to release resources as you | |
2154 | * normally would: we make sure that these functions continue | |
2155 | * to work when the hardware is down. | |
2156 | * | |
2157 | * Two examples: | |
2158 | * | |
2159 | * 1) If you normally free all your resources at the end of | |
2160 | * each request, or if you use anonymous FDs, your | |
2161 | * error_detected callback can simply set a flag to tell | |
2162 | * your driver not to start any new calls. You can then | |
2163 | * clear the flag in the resume callback. | |
2164 | * | |
2165 | * 2) If you normally allocate your resources on startup: | |
2166 | * * Set a flag in error_detected as above. | |
2167 | * * Let CXL detach your contexts. | |
2168 | * * In slot_reset, free the old resources and allocate new ones. | |
2169 | * * In resume, clear the flag to allow things to start. | |
2170 | */ | |
2171 | for (i = 0; i < adapter->slices; i++) { | |
2172 | afu = adapter->afu[i]; | |
2173 | ||
4f58f0bf | 2174 | afu_result = cxl_vphb_error_detected(afu, state); |
9e8df8a2 DA |
2175 | |
2176 | cxl_context_detach_all(afu); | |
5be587b1 | 2177 | cxl_ops->afu_deactivate_mode(afu, afu->current_mode); |
2b04cf31 | 2178 | pci_deconfigure_afu(afu); |
4f58f0bf VJ |
2179 | |
2180 | /* Disconnect trumps all, NONE trumps NEED_RESET */ | |
2181 | if (afu_result == PCI_ERS_RESULT_DISCONNECT) | |
2182 | result = PCI_ERS_RESULT_DISCONNECT; | |
2183 | else if ((afu_result == PCI_ERS_RESULT_NONE) && | |
2184 | (result == PCI_ERS_RESULT_NEED_RESET)) | |
2185 | result = PCI_ERS_RESULT_NONE; | |
9e8df8a2 | 2186 | } |
ea9a26d1 VJ |
2187 | |
2188 | /* should take the context lock here */ | |
2189 | if (cxl_adapter_context_lock(adapter) != 0) | |
2190 | dev_warn(&adapter->dev, | |
2191 | "Couldn't take context lock with %d active-contexts\n", | |
2192 | atomic_read(&adapter->contexts_num)); | |
2193 | ||
9e8df8a2 DA |
2194 | cxl_deconfigure_adapter(adapter); |
2195 | ||
2196 | return result; | |
2197 | } | |
2198 | ||
2199 | static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev) | |
2200 | { | |
2201 | struct cxl *adapter = pci_get_drvdata(pdev); | |
2202 | struct cxl_afu *afu; | |
2203 | struct cxl_context *ctx; | |
2204 | struct pci_dev *afu_dev; | |
2205 | pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED; | |
2206 | pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; | |
2207 | int i; | |
2208 | ||
2209 | if (cxl_configure_adapter(adapter, pdev)) | |
2210 | goto err; | |
2211 | ||
ea9a26d1 VJ |
2212 | /* |
2213 | * Unlock context activation for the adapter. Ideally this should be | |
2214 | * done in cxl_pci_resume but cxlflash module tries to activate the | |
2215 | * master context as part of slot_reset callback. | |
2216 | */ | |
2217 | cxl_adapter_context_unlock(adapter); | |
2218 | ||
9e8df8a2 DA |
2219 | for (i = 0; i < adapter->slices; i++) { |
2220 | afu = adapter->afu[i]; | |
2221 | ||
2b04cf31 | 2222 | if (pci_configure_afu(afu, adapter, pdev)) |
9e8df8a2 DA |
2223 | goto err; |
2224 | ||
2225 | if (cxl_afu_select_best_mode(afu)) | |
2226 | goto err; | |
2227 | ||
9e8df8a2 DA |
2228 | list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { |
2229 | /* Reset the device context. | |
2230 | * TODO: make this less disruptive | |
2231 | */ | |
2232 | ctx = cxl_get_context(afu_dev); | |
2233 | ||
2234 | if (ctx && cxl_release_context(ctx)) | |
2235 | goto err; | |
2236 | ||
2237 | ctx = cxl_dev_context_init(afu_dev); | |
bb81733d | 2238 | if (IS_ERR(ctx)) |
9e8df8a2 DA |
2239 | goto err; |
2240 | ||
2241 | afu_dev->dev.archdata.cxl_ctx = ctx; | |
2242 | ||
5be587b1 | 2243 | if (cxl_ops->afu_check_and_enable(afu)) |
9e8df8a2 DA |
2244 | goto err; |
2245 | ||
2246 | afu_dev->error_state = pci_channel_io_normal; | |
2247 | ||
2248 | /* If there's a driver attached, allow it to | |
2249 | * chime in on recovery. Drivers should check | |
2250 | * if everything has come back OK, but | |
2251 | * shouldn't start new work until we call | |
2252 | * their resume function. | |
2253 | */ | |
2254 | if (!afu_dev->driver) | |
2255 | continue; | |
2256 | ||
2257 | if (afu_dev->driver->err_handler && | |
2258 | afu_dev->driver->err_handler->slot_reset) | |
2259 | afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev); | |
2260 | ||
2261 | if (afu_result == PCI_ERS_RESULT_DISCONNECT) | |
2262 | result = PCI_ERS_RESULT_DISCONNECT; | |
2263 | } | |
2264 | } | |
2265 | return result; | |
2266 | ||
2267 | err: | |
2268 | /* All the bits that happen in both error_detected and cxl_remove | |
2269 | * should be idempotent, so we don't need to worry about leaving a mix | |
2270 | * of unconfigured and reconfigured resources. | |
2271 | */ | |
2272 | dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n"); | |
2273 | return PCI_ERS_RESULT_DISCONNECT; | |
2274 | } | |
2275 | ||
2276 | static void cxl_pci_resume(struct pci_dev *pdev) | |
2277 | { | |
2278 | struct cxl *adapter = pci_get_drvdata(pdev); | |
2279 | struct cxl_afu *afu; | |
2280 | struct pci_dev *afu_dev; | |
2281 | int i; | |
2282 | ||
2283 | /* Everything is back now. Drivers should restart work now. | |
2284 | * This is not the place to be checking if everything came back up | |
2285 | * properly, because there's no return value: do that in slot_reset. | |
2286 | */ | |
2287 | for (i = 0; i < adapter->slices; i++) { | |
2288 | afu = adapter->afu[i]; | |
2289 | ||
2290 | list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { | |
2291 | if (afu_dev->driver && afu_dev->driver->err_handler && | |
2292 | afu_dev->driver->err_handler->resume) | |
2293 | afu_dev->driver->err_handler->resume(afu_dev); | |
2294 | } | |
2295 | } | |
2296 | } | |
2297 | ||
2298 | static const struct pci_error_handlers cxl_err_handler = { | |
2299 | .error_detected = cxl_pci_error_detected, | |
2300 | .slot_reset = cxl_pci_slot_reset, | |
2301 | .resume = cxl_pci_resume, | |
2302 | }; | |
2303 | ||
f204e0b8 IM |
2304 | struct pci_driver cxl_pci_driver = { |
2305 | .name = "cxl-pci", | |
2306 | .id_table = cxl_pci_tbl, | |
2307 | .probe = cxl_probe, | |
2308 | .remove = cxl_remove, | |
aa70775e | 2309 | .shutdown = cxl_remove, |
9e8df8a2 | 2310 | .err_handler = &cxl_err_handler, |
f204e0b8 | 2311 | }; |