[mirror_ubuntu-zesty-kernel.git] / drivers / misc / cxl / vphb.c

/*
 * Copyright 2014 IBM Corp.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/pci.h>
#include <misc/cxl.h>
#include "cxl.h"

static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
{
	if (dma_mask < DMA_BIT_MASK(64)) {
		pr_info("%s only 64bit DMA supported on CXL", __func__);
		return -EIO;
	}

	*(pdev->dev.dma_mask) = dma_mask;
	return 0;
}

static int cxl_pci_probe_mode(struct pci_bus *bus)
{
	return PCI_PROBE_NORMAL;
}

static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
{
	return -ENODEV;
}

static void cxl_teardown_msi_irqs(struct pci_dev *pdev)
{
	/*
	 * MSI should never be set but need still need to provide this call
	 * back.
	 */
}

static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
{
	struct pci_controller *phb;
	struct cxl_afu *afu;
	struct cxl_context *ctx;

	phb = pci_bus_to_host(dev->bus);
	afu = (struct cxl_afu *)phb->private_data;
	set_dma_ops(&dev->dev, &dma_direct_ops);
	set_dma_offset(&dev->dev, PAGE_OFFSET);

	/*
	 * Allocate a context to do cxl things too.  If we eventually do real
	 * DMA ops, we'll need a default context to attach them to
	 */
	ctx = cxl_dev_context_init(dev);
	if (!ctx)
		return false;
	dev->dev.archdata.cxl_ctx = ctx;

	return (cxl_afu_check_and_enable(afu) == 0);
}

static void cxl_pci_disable_device(struct pci_dev *dev)
{
	struct cxl_context *ctx = cxl_get_context(dev);

	if (ctx) {
		if (ctx->status == STARTED) {
			dev_err(&dev->dev, "Default context started\n");
			return;
		}
		dev->dev.archdata.cxl_ctx = NULL;
		cxl_release_context(ctx);
	}
}

static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus,
						unsigned long type)
{
	return 1;
}

static void cxl_pci_reset_secondary_bus(struct pci_dev *dev)
{
	/* Should we do an AFU reset here ? */
}

static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
{
	return (bus << 8) + devfn;
}

static unsigned long cxl_pcie_cfg_addr(struct pci_controller* phb,
				       u8 bus, u8 devfn, int offset)
{
	int record = cxl_pcie_cfg_record(bus, devfn);

	return (unsigned long)phb->cfg_addr + ((unsigned long)phb->cfg_data * record) + offset;
}


static int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
				int offset, int len,
				volatile void __iomem **ioaddr,
				u32 *mask, int *shift)
{
	struct pci_controller *phb;
	struct cxl_afu *afu;
	unsigned long addr;

	phb = pci_bus_to_host(bus);
	afu = (struct cxl_afu *)phb->private_data;
	if (phb == NULL)
		return PCIBIOS_DEVICE_NOT_FOUND;
	if (cxl_pcie_cfg_record(bus->number, devfn) > afu->crs_num)
		return PCIBIOS_DEVICE_NOT_FOUND;
	if (offset >= (unsigned long)phb->cfg_data)
		return PCIBIOS_BAD_REGISTER_NUMBER;
	addr = cxl_pcie_cfg_addr(phb, bus->number, devfn, offset);

	*ioaddr = (void *)(addr & ~0x3ULL);
	*shift = ((addr & 0x3) * 8);
	switch (len) {
	case 1:
		*mask = 0xff;
		break;
	case 2:
		*mask = 0xffff;
		break;
	default:
		*mask = 0xffffffff;
		break;
	}
	return 0;
}

static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
				int offset, int len, u32 *val)
{
	volatile void __iomem *ioaddr;
	int shift, rc;
	u32 mask;

	rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr,
				  &mask, &shift);
	if (rc)
		return rc;

	/* Can only read 32 bits */
	*val = (in_le32(ioaddr) >> shift) & mask;
	return PCIBIOS_SUCCESSFUL;
}

static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
				 int offset, int len, u32 val)
{
	volatile void __iomem *ioaddr;
	u32 v, mask;
	int shift, rc;

	rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr,
				  &mask, &shift);
	if (rc)
		return rc;

	/* Can only write 32 bits so do read-modify-write */
	mask <<= shift;
	val <<= shift;

	v = (in_le32(ioaddr) & ~mask) || (val & mask);

	out_le32(ioaddr, v);
	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops cxl_pcie_pci_ops =
{
	.read = cxl_pcie_read_config,
	.write = cxl_pcie_write_config,
};


static struct pci_controller_ops cxl_pci_controller_ops =
{
	.probe_mode = cxl_pci_probe_mode,
	.enable_device_hook = cxl_pci_enable_device_hook,
	.disable_device = cxl_pci_disable_device,
	.release_device = cxl_pci_disable_device,
	.window_alignment = cxl_pci_window_alignment,
	.reset_secondary_bus = cxl_pci_reset_secondary_bus,
	.setup_msi_irqs = cxl_setup_msi_irqs,
	.teardown_msi_irqs = cxl_teardown_msi_irqs,
	.dma_set_mask = cxl_dma_set_mask,
};

int cxl_pci_vphb_add(struct cxl_afu *afu)
{
	struct pci_dev *phys_dev;
	struct pci_controller *phb, *phys_phb;

	phys_dev = to_pci_dev(afu->adapter->dev.parent);
	phys_phb = pci_bus_to_host(phys_dev->bus);

	/* Alloc and setup PHB data structure */
	phb = pcibios_alloc_controller(phys_phb->dn);

	if (!phb)
		return -ENODEV;

	/* Setup parent in sysfs */
	phb->parent = &phys_dev->dev;

	/* Setup the PHB using arch provided callback */
	phb->ops = &cxl_pcie_pci_ops;
	phb->cfg_addr = afu->afu_desc_mmio + afu->crs_offset;
	phb->cfg_data = (void *)(u64)afu->crs_len;
	phb->private_data = afu;
	phb->controller_ops = cxl_pci_controller_ops;

	/* Scan the bus */
	pcibios_scan_phb(phb);
	if (phb->bus == NULL)
		return -ENXIO;

	/* Claim resources. This might need some rework as well depending
	 * whether we are doing probe-only or not, like assigning unassigned
	 * resources etc...
	 */
	pcibios_claim_one_bus(phb->bus);

	/* Add probed PCI devices to the device model */
	pci_bus_add_devices(phb->bus);

	afu->phb = phb;

	return 0;
}


void cxl_pci_vphb_remove(struct cxl_afu *afu)
{
	struct pci_controller *phb;

	/* If there is no configuration record we won't have one of these */
	if (!afu || !afu->phb)
		return;

	phb = afu->phb;

	pci_remove_root_bus(phb->bus);
}

struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev)
{
	struct pci_controller *phb;

	phb = pci_bus_to_host(dev->bus);

	return (struct cxl_afu *)phb->private_data;
}
EXPORT_SYMBOL_GPL(cxl_pci_to_afu);

unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev)
{
	return cxl_pcie_cfg_record(dev->bus->number, dev->devfn);
}
EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record);
Commit	Line	Data
6f7f0b3d MN	1	/*
	2	* Copyright 2014 IBM Corp.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9
	10	#include <linux/pci.h>
	11	#include <misc/cxl.h>
	12	#include "cxl.h"
	13
	14	static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
	15	{
	16	if (dma_mask < DMA_BIT_MASK(64)) {
	17	pr_info("%s only 64bit DMA supported on CXL", __func__);
	18	return -EIO;
	19	}
	20
	21	*(pdev->dev.dma_mask) = dma_mask;
	22	return 0;
	23	}
	24
	25	static int cxl_pci_probe_mode(struct pci_bus *bus)
	26	{
	27	return PCI_PROBE_NORMAL;
	28	}
	29
	30	static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
	31	{
	32	return -ENODEV;
	33	}
	34
	35	static void cxl_teardown_msi_irqs(struct pci_dev *pdev)
	36	{
	37	/*
	38	* MSI should never be set but need still need to provide this call
	39	* back.
	40	*/
	41	}
	42
	43	static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
	44	{
	45	struct pci_controller *phb;
	46	struct cxl_afu *afu;
	47	struct cxl_context *ctx;
	48
	49	phb = pci_bus_to_host(dev->bus);
	50	afu = (struct cxl_afu *)phb->private_data;
	51	set_dma_ops(&dev->dev, &dma_direct_ops);
	52	set_dma_offset(&dev->dev, PAGE_OFFSET);
	53
	54	/*
	55	* Allocate a context to do cxl things too. If we eventually do real
	56	* DMA ops, we'll need a default context to attach them to
	57	*/
	58	ctx = cxl_dev_context_init(dev);
	59	if (!ctx)
	60	return false;
	61	dev->dev.archdata.cxl_ctx = ctx;
	62
	63	return (cxl_afu_check_and_enable(afu) == 0);
	64	}
65
66	static void cxl_pci_disable_device(struct pci_dev *dev)
67	{
68	struct cxl_context *ctx = cxl_get_context(dev);
69
70	if (ctx) {
71	if (ctx->status == STARTED) {
72	dev_err(&dev->dev, "Default context started\n");
73	return;
74	}
f67b4938	75	dev->dev.archdata.cxl_ctx = NULL;
6f7f0b3d MN	76	cxl_release_context(ctx);
	77	}
	78	}
	79
	80	static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus,
	81	unsigned long type)
	82	{
	83	return 1;
	84	}
	85
	86	static void cxl_pci_reset_secondary_bus(struct pci_dev *dev)
	87	{
	88	/* Should we do an AFU reset here ? */
	89	}
	90
	91	static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
	92	{
	93	return (bus << 8) + devfn;
	94	}
	95
	96	static unsigned long cxl_pcie_cfg_addr(struct pci_controller* phb,
	97	u8 bus, u8 devfn, int offset)
	98	{
	99	int record = cxl_pcie_cfg_record(bus, devfn);
	100
	101	return (unsigned long)phb->cfg_addr + ((unsigned long)phb->cfg_data * record) + offset;
	102	}
	103
	104
	105	static int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
	106	int offset, int len,
	107	volatile void __iomem **ioaddr,
	108	u32 mask, int shift)
	109	{
	110	struct pci_controller *phb;
	111	struct cxl_afu *afu;
	112	unsigned long addr;
	113
	114	phb = pci_bus_to_host(bus);
	115	afu = (struct cxl_afu *)phb->private_data;
	116	if (phb == NULL)
	117	return PCIBIOS_DEVICE_NOT_FOUND;
	118	if (cxl_pcie_cfg_record(bus->number, devfn) > afu->crs_num)
	119	return PCIBIOS_DEVICE_NOT_FOUND;
	120	if (offset >= (unsigned long)phb->cfg_data)
	121	return PCIBIOS_BAD_REGISTER_NUMBER;
	122	addr = cxl_pcie_cfg_addr(phb, bus->number, devfn, offset);
	123
	124	ioaddr = (void )(addr & ~0x3ULL);
	125	shift = ((addr & 0x3) 8);
	126	switch (len) {
	127	case 1:
	128	*mask = 0xff;
	129	break;
	130	case 2:
	131	*mask = 0xffff;
	132	break;
	133	default:
	134	*mask = 0xffffffff;
	135	break;
	136	}
	137	return 0;
	138	}
	139
140	static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
141	int offset, int len, u32 *val)
142	{
143	volatile void __iomem *ioaddr;
144	int shift, rc;
145	u32 mask;
146
147	rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr,
148	&mask, &shift);
149	if (rc)
150	return rc;
151
152	/* Can only read 32 bits */
153	*val = (in_le32(ioaddr) >> shift) & mask;
154	return PCIBIOS_SUCCESSFUL;
155	}
156
157	static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
158	int offset, int len, u32 val)
159	{
160	volatile void __iomem *ioaddr;
161	u32 v, mask;
162	int shift, rc;
163
164	rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr,
165	&mask, &shift);
166	if (rc)
167	return rc;
168
169	/* Can only write 32 bits so do read-modify-write */
170	mask <<= shift;
171	val <<= shift;
172
173	v = (in_le32(ioaddr) & ~mask) \|\| (val & mask);
174
175	out_le32(ioaddr, v);
176	return PCIBIOS_SUCCESSFUL;
177	}
178
179	static struct pci_ops cxl_pcie_pci_ops =
180	{
181	.read = cxl_pcie_read_config,
182	.write = cxl_pcie_write_config,
183	};
184
185
186	static struct pci_controller_ops cxl_pci_controller_ops =
187	{
188	.probe_mode = cxl_pci_probe_mode,
189	.enable_device_hook = cxl_pci_enable_device_hook,
190	.disable_device = cxl_pci_disable_device,
191	.release_device = cxl_pci_disable_device,
192	.window_alignment = cxl_pci_window_alignment,
193	.reset_secondary_bus = cxl_pci_reset_secondary_bus,
194	.setup_msi_irqs = cxl_setup_msi_irqs,
195	.teardown_msi_irqs = cxl_teardown_msi_irqs,
196	.dma_set_mask = cxl_dma_set_mask,
197	};
198
199	int cxl_pci_vphb_add(struct cxl_afu *afu)
200	{
201	struct pci_dev *phys_dev;
202	struct pci_controller phb, phys_phb;
203
204	phys_dev = to_pci_dev(afu->adapter->dev.parent);
205	phys_phb = pci_bus_to_host(phys_dev->bus);
206
207	/* Alloc and setup PHB data structure */
208	phb = pcibios_alloc_controller(phys_phb->dn);
209
210	if (!phb)
211	return -ENODEV;
212
213	/* Setup parent in sysfs */
214	phb->parent = &phys_dev->dev;
215
216	/* Setup the PHB using arch provided callback */
217	phb->ops = &cxl_pcie_pci_ops;
218	phb->cfg_addr = afu->afu_desc_mmio + afu->crs_offset;
219	phb->cfg_data = (void *)(u64)afu->crs_len;
220	phb->private_data = afu;
221	phb->controller_ops = cxl_pci_controller_ops;
222
223	/* Scan the bus */
224	pcibios_scan_phb(phb);
225	if (phb->bus == NULL)
226	return -ENXIO;
227
228	/* Claim resources. This might need some rework as well depending
229	* whether we are doing probe-only or not, like assigning unassigned
230	* resources etc...
231	*/
232	pcibios_claim_one_bus(phb->bus);
233
234	/* Add probed PCI devices to the device model */
235	pci_bus_add_devices(phb->bus);
236
237	afu->phb = phb;
238
239	return 0;
240	}
241
242
243	void cxl_pci_vphb_remove(struct cxl_afu *afu)
244	{
245	struct pci_controller *phb;
246
247	/* If there is no configuration record we won't have one of these */
248	if (!afu \|\| !afu->phb)
249	return;
250
251	phb = afu->phb;
252
253	pci_remove_root_bus(phb->bus);
254	}
255
256	struct cxl_afu cxl_pci_to_afu(struct pci_dev dev)
257	{
258	struct pci_controller *phb;
259
260	phb = pci_bus_to_host(dev->bus);
261
262	return (struct cxl_afu *)phb->private_data;
263	}
264	EXPORT_SYMBOL_GPL(cxl_pci_to_afu);
265
266	unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev)
267	{
268	return cxl_pcie_cfg_record(dev->bus->number, dev->devfn);
269	}
270	EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record);