[mirror_ubuntu-bionic-kernel.git] / drivers / misc / eeprom / at25.c

/*
 * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
 *
 * Copyright (C) 2006 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/sched.h>

#include <linux/nvmem-provider.h>
#include <linux/spi/spi.h>
#include <linux/spi/eeprom.h>
#include <linux/property.h>

/*
 * NOTE: this is an *EEPROM* driver.  The vagaries of product naming
 * mean that some AT25 products are EEPROMs, and others are FLASH.
 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
 * not this one!
 */

struct at25_data {
	struct spi_device	*spi;
	struct mutex		lock;
	struct spi_eeprom	chip;
	unsigned		addrlen;
	struct nvmem_config	nvmem_config;
	struct nvmem_device	*nvmem;
};

#define	AT25_WREN	0x06		/* latch the write enable */
#define	AT25_WRDI	0x04		/* reset the write enable */
#define	AT25_RDSR	0x05		/* read status register */
#define	AT25_WRSR	0x01		/* write status register */
#define	AT25_READ	0x03		/* read byte(s) */
#define	AT25_WRITE	0x02		/* write byte(s)/sector */

#define	AT25_SR_nRDY	0x01		/* nRDY = write-in-progress */
#define	AT25_SR_WEN	0x02		/* write enable (latched) */
#define	AT25_SR_BP0	0x04		/* BP for software writeprotect */
#define	AT25_SR_BP1	0x08
#define	AT25_SR_WPEN	0x80		/* writeprotect enable */

#define	AT25_INSTR_BIT3	0x08		/* Additional address bit in instr */

#define EE_MAXADDRLEN	3		/* 24 bit addresses, up to 2 MBytes */

/* Specs often allow 5 msec for a page write, sometimes 20 msec;
 * it's important to recover from write timeouts.
 */
#define	EE_TIMEOUT	25

/*-------------------------------------------------------------------------*/

#define	io_limit	PAGE_SIZE	/* bytes */

static int at25_ee_read(void *priv, unsigned int offset,
			void *val, size_t count)
{
	struct at25_data *at25 = priv;
	char *buf = val;
	u8			command[EE_MAXADDRLEN + 1];
	u8			*cp;
	ssize_t			status;
	struct spi_transfer	t[2];
	struct spi_message	m;
	u8			instr;

	if (unlikely(offset >= at25->chip.byte_len))
		return -EINVAL;
	if ((offset + count) > at25->chip.byte_len)
		count = at25->chip.byte_len - offset;
	if (unlikely(!count))
		return -EINVAL;

	cp = command;

	instr = AT25_READ;
	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
		if (offset >= (1U << (at25->addrlen * 8)))
			instr |= AT25_INSTR_BIT3;
	*cp++ = instr;

	/* 8/16/24-bit address is written MSB first */
	switch (at25->addrlen) {
	default:	/* case 3 */
		*cp++ = offset >> 16;
	case 2:
		*cp++ = offset >> 8;
	case 1:
	case 0:	/* can't happen: for better codegen */
		*cp++ = offset >> 0;
	}

	spi_message_init(&m);
	memset(t, 0, sizeof t);

	t[0].tx_buf = command;
	t[0].len = at25->addrlen + 1;
	spi_message_add_tail(&t[0], &m);

	t[1].rx_buf = buf;
	t[1].len = count;
	spi_message_add_tail(&t[1], &m);

	mutex_lock(&at25->lock);

	/* Read it all at once.
	 *
	 * REVISIT that's potentially a problem with large chips, if
	 * other devices on the bus need to be accessed regularly or
	 * this chip is clocked very slowly
	 */
	status = spi_sync(at25->spi, &m);
	dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n",
		count, offset, status);

	mutex_unlock(&at25->lock);
	return status;
}

static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
{
	struct at25_data *at25 = priv;
	const char *buf = val;
	int			status = 0;
	unsigned		buf_size;
	u8			*bounce;

	if (unlikely(off >= at25->chip.byte_len))
		return -EFBIG;
	if ((off + count) > at25->chip.byte_len)
		count = at25->chip.byte_len - off;
	if (unlikely(!count))
		return -EINVAL;

	/* Temp buffer starts with command and address */
	buf_size = at25->chip.page_size;
	if (buf_size > io_limit)
		buf_size = io_limit;
	bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
	if (!bounce)
		return -ENOMEM;

	/* For write, rollover is within the page ... so we write at
	 * most one page, then manually roll over to the next page.
	 */
	mutex_lock(&at25->lock);
	do {
		unsigned long	timeout, retries;
		unsigned	segment;
		unsigned	offset = (unsigned) off;
		u8		*cp = bounce;
		int		sr;
		u8		instr;

		*cp = AT25_WREN;
		status = spi_write(at25->spi, cp, 1);
		if (status < 0) {
			dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
			break;
		}

		instr = AT25_WRITE;
		if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
			if (offset >= (1U << (at25->addrlen * 8)))
				instr |= AT25_INSTR_BIT3;
		*cp++ = instr;

		/* 8/16/24-bit address is written MSB first */
		switch (at25->addrlen) {
		default:	/* case 3 */
			*cp++ = offset >> 16;
		case 2:
			*cp++ = offset >> 8;
		case 1:
		case 0:	/* can't happen: for better codegen */
			*cp++ = offset >> 0;
		}

		/* Write as much of a page as we can */
		segment = buf_size - (offset % buf_size);
		if (segment > count)
			segment = count;
		memcpy(cp, buf, segment);
		status = spi_write(at25->spi, bounce,
				segment + at25->addrlen + 1);
		dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
			segment, offset, status);
		if (status < 0)
			break;

		/* REVISIT this should detect (or prevent) failed writes
		 * to readonly sections of the EEPROM...
		 */

		/* Wait for non-busy status */
		timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
		retries = 0;
		do {

			sr = spi_w8r8(at25->spi, AT25_RDSR);
			if (sr < 0 || (sr & AT25_SR_nRDY)) {
				dev_dbg(&at25->spi->dev,
					"rdsr --> %d (%02x)\n", sr, sr);
				/* at HZ=100, this is sloooow */
				msleep(1);
				continue;
			}
			if (!(sr & AT25_SR_nRDY))
				break;
		} while (retries++ < 3 || time_before_eq(jiffies, timeout));

		if ((sr < 0) || (sr & AT25_SR_nRDY)) {
			dev_err(&at25->spi->dev,
				"write %u bytes offset %u, timeout after %u msecs\n",
				segment, offset,
				jiffies_to_msecs(jiffies -
					(timeout - EE_TIMEOUT)));
			status = -ETIMEDOUT;
			break;
		}

		off += segment;
		buf += segment;
		count -= segment;

	} while (count > 0);

	mutex_unlock(&at25->lock);

	kfree(bounce);
	return status;
}

/*-------------------------------------------------------------------------*/

static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
{
	u32 val;

	memset(chip, 0, sizeof(*chip));
	strncpy(chip->name, "at25", sizeof(chip->name));

	if (device_property_read_u32(dev, "size", &val) == 0 ||
	    device_property_read_u32(dev, "at25,byte-len", &val) == 0) {
		chip->byte_len = val;
	} else {
		dev_err(dev, "Error: missing \"size\" property\n");
		return -ENODEV;
	}

	if (device_property_read_u32(dev, "pagesize", &val) == 0 ||
	    device_property_read_u32(dev, "at25,page-size", &val) == 0) {
		chip->page_size = (u16)val;
	} else {
		dev_err(dev, "Error: missing \"pagesize\" property\n");
		return -ENODEV;
	}

	if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) {
		chip->flags = (u16)val;
	} else {
		if (device_property_read_u32(dev, "address-width", &val)) {
			dev_err(dev,
				"Error: missing \"address-width\" property\n");
			return -ENODEV;
		}
		switch (val) {
		case 8:
			chip->flags |= EE_ADDR1;
			break;
		case 16:
			chip->flags |= EE_ADDR2;
			break;
		case 24:
			chip->flags |= EE_ADDR3;
			break;
		default:
			dev_err(dev,
				"Error: bad \"address-width\" property: %u\n",
				val);
			return -ENODEV;
		}
		if (device_property_present(dev, "read-only"))
			chip->flags |= EE_READONLY;
	}
	return 0;
}

static int at25_probe(struct spi_device *spi)
{
	struct at25_data	*at25 = NULL;
	struct spi_eeprom	chip;
	int			err;
	int			sr;
	int			addrlen;

	/* Chip description */
	if (!spi->dev.platform_data) {
		err = at25_fw_to_chip(&spi->dev, &chip);
		if (err)
			return err;
	} else
		chip = *(struct spi_eeprom *)spi->dev.platform_data;

	/* For now we only support 8/16/24 bit addressing */
	if (chip.flags & EE_ADDR1)
		addrlen = 1;
	else if (chip.flags & EE_ADDR2)
		addrlen = 2;
	else if (chip.flags & EE_ADDR3)
		addrlen = 3;
	else {
		dev_dbg(&spi->dev, "unsupported address type\n");
		return -EINVAL;
	}

	/* Ping the chip ... the status register is pretty portable,
	 * unlike probing manufacturer IDs.  We do expect that system
	 * firmware didn't write it in the past few milliseconds!
	 */
	sr = spi_w8r8(spi, AT25_RDSR);
	if (sr < 0 || sr & AT25_SR_nRDY) {
		dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
		return -ENXIO;
	}

	at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL);
	if (!at25)
		return -ENOMEM;

	mutex_init(&at25->lock);
	at25->chip = chip;
	at25->spi = spi;
	spi_set_drvdata(spi, at25);
	at25->addrlen = addrlen;

	at25->nvmem_config.name = dev_name(&spi->dev);
	at25->nvmem_config.dev = &spi->dev;
	at25->nvmem_config.read_only = chip.flags & EE_READONLY;
	at25->nvmem_config.root_only = true;
	at25->nvmem_config.owner = THIS_MODULE;
	at25->nvmem_config.compat = true;
	at25->nvmem_config.base_dev = &spi->dev;
	at25->nvmem_config.reg_read = at25_ee_read;
	at25->nvmem_config.reg_write = at25_ee_write;
	at25->nvmem_config.priv = at25;
	at25->nvmem_config.stride = 4;
	at25->nvmem_config.word_size = 1;
	at25->nvmem_config.size = chip.byte_len;

	at25->nvmem = nvmem_register(&at25->nvmem_config);
	if (IS_ERR(at25->nvmem))
		return PTR_ERR(at25->nvmem);

	dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n",
		(chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024),
		(chip.byte_len < 1024) ? "Byte" : "KByte",
		at25->chip.name,
		(chip.flags & EE_READONLY) ? " (readonly)" : "",
		at25->chip.page_size);
	return 0;
}

static int at25_remove(struct spi_device *spi)
{
	struct at25_data	*at25;

	at25 = spi_get_drvdata(spi);
	nvmem_unregister(at25->nvmem);

	return 0;
}

/*-------------------------------------------------------------------------*/

static const struct of_device_id at25_of_match[] = {
	{ .compatible = "atmel,at25", },
	{ }
};
MODULE_DEVICE_TABLE(of, at25_of_match);

static struct spi_driver at25_driver = {
	.driver = {
		.name		= "at25",
		.of_match_table = at25_of_match,
	},
	.probe		= at25_probe,
	.remove		= at25_remove,
};

module_spi_driver(at25_driver);

MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
MODULE_AUTHOR("David Brownell");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:at25");
Commit	Line	Data
b587b13a DB	1	/*
	2	* at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
	3	*
	4	* Copyright (C) 2006 David Brownell
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/kernel.h>
b587b13a DB	13	#include <linux/module.h>
	14	#include <linux/slab.h>
	15	#include <linux/delay.h>
	16	#include <linux/device.h>
	17	#include <linux/sched.h>
	18
5a99f570	19	#include <linux/nvmem-provider.h>
b587b13a DB	20	#include <linux/spi/spi.h>
b587b13a DB	21	#include <linux/spi/eeprom.h>
f60e7074	22	#include <linux/property.h>
b587b13a	23
3f86f14c DB	24	/*
	25	* NOTE: this is an EEPROM driver. The vagaries of product naming
	26	* mean that some AT25 products are EEPROMs, and others are FLASH.
	27	* Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
	28	* not this one!
	29	*/
	30
b587b13a DB	31	struct at25_data {
	32	struct spi_device *spi;
	33	struct mutex lock;
	34	struct spi_eeprom chip;
b587b13a	35	unsigned addrlen;
5a99f570 AL	36	struct nvmem_config nvmem_config;
5a99f570 AL	37	struct nvmem_device *nvmem;
b587b13a DB	38	};
	39
	40	#define AT25_WREN 0x06 /* latch the write enable */
	41	#define AT25_WRDI 0x04 /* reset the write enable */
	42	#define AT25_RDSR 0x05 /* read status register */
	43	#define AT25_WRSR 0x01 /* write status register */
	44	#define AT25_READ 0x03 /* read byte(s) */
	45	#define AT25_WRITE 0x02 /* write byte(s)/sector */
	46
	47	#define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
	48	#define AT25_SR_WEN 0x02 /* write enable (latched) */
	49	#define AT25_SR_BP0 0x04 /* BP for software writeprotect */
	50	#define AT25_SR_BP1 0x08
	51	#define AT25_SR_WPEN 0x80 /* writeprotect enable */
	52
b4161f0b	53	#define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */
b587b13a DB	54
	55	#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
	56
	57	/* Specs often allow 5 msec for a page write, sometimes 20 msec;
	58	* it's important to recover from write timeouts.
	59	*/
	60	#define EE_TIMEOUT 25
	61
	62	/-------------------------------------------------------------------------/
	63
	64	#define io_limit PAGE_SIZE /* bytes */
	65
01973a01 SK	66	static int at25_ee_read(void *priv, unsigned int offset,
01973a01 SK	67	void *val, size_t count)
b587b13a	68	{
01973a01 SK	69	struct at25_data *at25 = priv;
01973a01 SK	70	char *buf = val;
b587b13a DB	71	u8 command[EE_MAXADDRLEN + 1];
	72	u8 *cp;
	73	ssize_t status;
	74	struct spi_transfer t[2];
	75	struct spi_message m;
b4161f0b	76	u8 instr;
b587b13a	77
5a99f570	78	if (unlikely(offset >= at25->chip.byte_len))
01973a01	79	return -EINVAL;
5a99f570 AL	80	if ((offset + count) > at25->chip.byte_len)
5a99f570 AL	81	count = at25->chip.byte_len - offset;
14dd1ff0	82	if (unlikely(!count))
01973a01	83	return -EINVAL;
14dd1ff0	84
b587b13a	85	cp = command;
b4161f0b IS	86
	87	instr = AT25_READ;
	88	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
	89	if (offset >= (1U << (at25->addrlen * 8)))
	90	instr \|= AT25_INSTR_BIT3;
	91	*cp++ = instr;
b587b13a DB	92
	93	/* 8/16/24-bit address is written MSB first */
	94	switch (at25->addrlen) {
	95	default: /* case 3 */
	96	*cp++ = offset >> 16;
	97	case 2:
	98	*cp++ = offset >> 8;
	99	case 1:
	100	case 0: /* can't happen: for better codegen */
	101	*cp++ = offset >> 0;
	102	}
	103
	104	spi_message_init(&m);
	105	memset(t, 0, sizeof t);
	106
	107	t[0].tx_buf = command;
	108	t[0].len = at25->addrlen + 1;
	109	spi_message_add_tail(&t[0], &m);
	110
	111	t[1].rx_buf = buf;
	112	t[1].len = count;
	113	spi_message_add_tail(&t[1], &m);
	114
	115	mutex_lock(&at25->lock);
	116
	117	/* Read it all at once.
	118	*
	119	* REVISIT that's potentially a problem with large chips, if
	120	* other devices on the bus need to be accessed regularly or
	121	* this chip is clocked very slowly
	122	*/
	123	status = spi_sync(at25->spi, &m);
3936e4c8 AS	124	dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n",
3936e4c8 AS	125	count, offset, status);
b587b13a DB	126
b587b13a DB	127	mutex_unlock(&at25->lock);
01973a01	128	return status;
b587b13a DB	129	}
b587b13a DB	130
01973a01	131	static int at25_ee_write(void priv, unsigned int off, void val, size_t count)
b587b13a	132	{
01973a01 SK	133	struct at25_data *at25 = priv;
	134	const char *buf = val;
	135	int status = 0;
b587b13a DB	136	unsigned buf_size;
	137	u8 *bounce;
	138
5a99f570	139	if (unlikely(off >= at25->chip.byte_len))
14dd1ff0	140	return -EFBIG;
5a99f570 AL	141	if ((off + count) > at25->chip.byte_len)
5a99f570 AL	142	count = at25->chip.byte_len - off;
14dd1ff0	143	if (unlikely(!count))
01973a01	144	return -EINVAL;
14dd1ff0	145
b587b13a DB	146	/* Temp buffer starts with command and address */
	147	buf_size = at25->chip.page_size;
	148	if (buf_size > io_limit)
	149	buf_size = io_limit;
	150	bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
	151	if (!bounce)
	152	return -ENOMEM;
	153
	154	/* For write, rollover is within the page ... so we write at
	155	* most one page, then manually roll over to the next page.
	156	*/
b587b13a DB	157	mutex_lock(&at25->lock);
	158	do {
	159	unsigned long timeout, retries;
	160	unsigned segment;
	161	unsigned offset = (unsigned) off;
b4161f0b	162	u8 *cp = bounce;
f0d83679	163	int sr;
b4161f0b	164	u8 instr;
b587b13a DB	165
	166	*cp = AT25_WREN;
	167	status = spi_write(at25->spi, cp, 1);
	168	if (status < 0) {
3936e4c8	169	dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
b587b13a DB	170	break;
	171	}
	172
b4161f0b IS	173	instr = AT25_WRITE;
	174	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
	175	if (offset >= (1U << (at25->addrlen * 8)))
	176	instr \|= AT25_INSTR_BIT3;
	177	*cp++ = instr;
	178
b587b13a DB	179	/* 8/16/24-bit address is written MSB first */
	180	switch (at25->addrlen) {
	181	default: /* case 3 */
	182	*cp++ = offset >> 16;
	183	case 2:
	184	*cp++ = offset >> 8;
	185	case 1:
	186	case 0: /* can't happen: for better codegen */
	187	*cp++ = offset >> 0;
	188	}
	189
	190	/* Write as much of a page as we can */
	191	segment = buf_size - (offset % buf_size);
	192	if (segment > count)
	193	segment = count;
	194	memcpy(cp, buf, segment);
	195	status = spi_write(at25->spi, bounce,
	196	segment + at25->addrlen + 1);
3936e4c8 AS	197	dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
3936e4c8 AS	198	segment, offset, status);
b587b13a DB	199	if (status < 0)
	200	break;
	201
	202	/* REVISIT this should detect (or prevent) failed writes
	203	* to readonly sections of the EEPROM...
	204	*/
	205
	206	/* Wait for non-busy status */
	207	timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
	208	retries = 0;
	209	do {
b587b13a DB	210
	211	sr = spi_w8r8(at25->spi, AT25_RDSR);
	212	if (sr < 0 \|\| (sr & AT25_SR_nRDY)) {
	213	dev_dbg(&at25->spi->dev,
	214	"rdsr --> %d (%02x)\n", sr, sr);
	215	/* at HZ=100, this is sloooow */
	216	msleep(1);
	217	continue;
	218	}
	219	if (!(sr & AT25_SR_nRDY))
	220	break;
	221	} while (retries++ < 3 \|\| time_before_eq(jiffies, timeout));
	222
f0d83679	223	if ((sr < 0) \|\| (sr & AT25_SR_nRDY)) {
b587b13a	224	dev_err(&at25->spi->dev,
3936e4c8	225	"write %u bytes offset %u, timeout after %u msecs\n",
b587b13a DB	226	segment, offset,
	227	jiffies_to_msecs(jiffies -
	228	(timeout - EE_TIMEOUT)));
	229	status = -ETIMEDOUT;
	230	break;
	231	}
	232
	233	off += segment;
	234	buf += segment;
	235	count -= segment;
b587b13a DB	236
	237	} while (count > 0);
	238
	239	mutex_unlock(&at25->lock);
	240
	241	kfree(bounce);
01973a01	242	return status;
b587b13a DB	243	}
b587b13a DB	244
b587b13a DB	245	/-------------------------------------------------------------------------/
b587b13a DB	246
f60e7074	247	static int at25_fw_to_chip(struct device dev, struct spi_eeprom chip)
d6ae0d57 DD	248	{
	249	u32 val;
	250
	251	memset(chip, 0, sizeof(*chip));
f60e7074	252	strncpy(chip->name, "at25", sizeof(chip->name));
d6ae0d57	253
f60e7074 MW	254	if (device_property_read_u32(dev, "size", &val) == 0 \|\|
f60e7074 MW	255	device_property_read_u32(dev, "at25,byte-len", &val) == 0) {
d6ae0d57 DD	256	chip->byte_len = val;
	257	} else {
	258	dev_err(dev, "Error: missing \"size\" property\n");
	259	return -ENODEV;
	260	}
	261
f60e7074 MW	262	if (device_property_read_u32(dev, "pagesize", &val) == 0 \|\|
f60e7074 MW	263	device_property_read_u32(dev, "at25,page-size", &val) == 0) {
d6ae0d57 DD	264	chip->page_size = (u16)val;
	265	} else {
	266	dev_err(dev, "Error: missing \"pagesize\" property\n");
	267	return -ENODEV;
	268	}
	269
f60e7074	270	if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) {
d6ae0d57 DD	271	chip->flags = (u16)val;
d6ae0d57 DD	272	} else {
f60e7074	273	if (device_property_read_u32(dev, "address-width", &val)) {
d6ae0d57 DD	274	dev_err(dev,
	275	"Error: missing \"address-width\" property\n");
	276	return -ENODEV;
	277	}
	278	switch (val) {
	279	case 8:
	280	chip->flags \|= EE_ADDR1;
	281	break;
	282	case 16:
	283	chip->flags \|= EE_ADDR2;
	284	break;
	285	case 24:
	286	chip->flags \|= EE_ADDR3;
	287	break;
	288	default:
	289	dev_err(dev,
	290	"Error: bad \"address-width\" property: %u\n",
	291	val);
	292	return -ENODEV;
	293	}
f60e7074	294	if (device_property_present(dev, "read-only"))
d6ae0d57 DD	295	chip->flags \|= EE_READONLY;
	296	}
	297	return 0;
	298	}
	299
b587b13a DB	300	static int at25_probe(struct spi_device *spi)
	301	{
	302	struct at25_data *at25 = NULL;
002176db	303	struct spi_eeprom chip;
b587b13a DB	304	int err;
	305	int sr;
	306	int addrlen;
	307
	308	/* Chip description */
002176db	309	if (!spi->dev.platform_data) {
f60e7074 MW	310	err = at25_fw_to_chip(&spi->dev, &chip);
	311	if (err)
	312	return err;
002176db APS	313	} else
002176db APS	314	chip = (struct spi_eeprom )spi->dev.platform_data;
b587b13a DB	315
b587b13a DB	316	/* For now we only support 8/16/24 bit addressing */
002176db	317	if (chip.flags & EE_ADDR1)
b587b13a	318	addrlen = 1;
002176db	319	else if (chip.flags & EE_ADDR2)
b587b13a	320	addrlen = 2;
002176db	321	else if (chip.flags & EE_ADDR3)
b587b13a DB	322	addrlen = 3;
	323	else {
	324	dev_dbg(&spi->dev, "unsupported address type\n");
01fe7b43	325	return -EINVAL;
b587b13a DB	326	}
	327
	328	/* Ping the chip ... the status register is pretty portable,
	329	* unlike probing manufacturer IDs. We do expect that system
	330	* firmware didn't write it in the past few milliseconds!
	331	*/
	332	sr = spi_w8r8(spi, AT25_RDSR);
	333	if (sr < 0 \|\| sr & AT25_SR_nRDY) {
c6ca97d2	334	dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
01fe7b43	335	return -ENXIO;
b587b13a DB	336	}
b587b13a DB	337
01fe7b43 NB	338	at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL);
	339	if (!at25)
	340	return -ENOMEM;
b587b13a DB	341
b587b13a DB	342	mutex_init(&at25->lock);
002176db	343	at25->chip = chip;
96b2a45c	344	at25->spi = spi;
41ddcf67	345	spi_set_drvdata(spi, at25);
b587b13a DB	346	at25->addrlen = addrlen;
b587b13a DB	347
5a99f570 AL	348	at25->nvmem_config.name = dev_name(&spi->dev);
	349	at25->nvmem_config.dev = &spi->dev;
	350	at25->nvmem_config.read_only = chip.flags & EE_READONLY;
	351	at25->nvmem_config.root_only = true;
	352	at25->nvmem_config.owner = THIS_MODULE;
	353	at25->nvmem_config.compat = true;
	354	at25->nvmem_config.base_dev = &spi->dev;
01973a01 SK	355	at25->nvmem_config.reg_read = at25_ee_read;
	356	at25->nvmem_config.reg_write = at25_ee_write;
	357	at25->nvmem_config.priv = at25;
	358	at25->nvmem_config.stride = 4;
	359	at25->nvmem_config.word_size = 1;
	360	at25->nvmem_config.size = chip.byte_len;
5a99f570 AL	361
	362	at25->nvmem = nvmem_register(&at25->nvmem_config);
	363	if (IS_ERR(at25->nvmem))
	364	return PTR_ERR(at25->nvmem);
	365
	366	dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n",
3936e4c8	367	(chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024),
5a99f570	368	(chip.byte_len < 1024) ? "Byte" : "KByte",
b587b13a	369	at25->chip.name,
002176db	370	(chip.flags & EE_READONLY) ? " (readonly)" : "",
b587b13a DB	371	at25->chip.page_size);
b587b13a DB	372	return 0;
b587b13a DB	373	}
b587b13a DB	374
486a5c28	375	static int at25_remove(struct spi_device *spi)
b587b13a DB	376	{
	377	struct at25_data *at25;
	378
41ddcf67	379	at25 = spi_get_drvdata(spi);
5a99f570 AL	380	nvmem_unregister(at25->nvmem);
5a99f570 AL	381
b587b13a DB	382	return 0;
	383	}
	384
	385	/-------------------------------------------------------------------------/
	386
fbfdb6ed JL	387	static const struct of_device_id at25_of_match[] = {
	388	{ .compatible = "atmel,at25", },
	389	{ }
	390	};
	391	MODULE_DEVICE_TABLE(of, at25_of_match);
	392
b587b13a DB	393	static struct spi_driver at25_driver = {
	394	.driver = {
	395	.name = "at25",
fbfdb6ed	396	.of_match_table = at25_of_match,
b587b13a DB	397	},
b587b13a DB	398	.probe = at25_probe,
2d6bed9c	399	.remove = at25_remove,
b587b13a DB	400	};
b587b13a DB	401
a3dc3c9e	402	module_spi_driver(at25_driver);
b587b13a DB	403
	404	MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
	405	MODULE_AUTHOR("David Brownell");
	406	MODULE_LICENSE("GPL");
e0626e38	407	MODULE_ALIAS("spi:at25");