[mirror_ubuntu-focal-kernel.git] / drivers / misc / eeprom / at25.c

/*
 * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
 *
 * Copyright (C) 2006 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/sched.h>

#include <linux/nvmem-provider.h>
#include <linux/spi/spi.h>
#include <linux/spi/eeprom.h>
#include <linux/property.h>

/*
 * NOTE: this is an *EEPROM* driver.  The vagaries of product naming
 * mean that some AT25 products are EEPROMs, and others are FLASH.
 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
 * not this one!
 */

struct at25_data {
	struct spi_device	*spi;
	struct mutex		lock;
	struct spi_eeprom	chip;
	unsigned		addrlen;
	struct nvmem_config	nvmem_config;
	struct nvmem_device	*nvmem;
};

#define	AT25_WREN	0x06		/* latch the write enable */
#define	AT25_WRDI	0x04		/* reset the write enable */
#define	AT25_RDSR	0x05		/* read status register */
#define	AT25_WRSR	0x01		/* write status register */
#define	AT25_READ	0x03		/* read byte(s) */
#define	AT25_WRITE	0x02		/* write byte(s)/sector */

#define	AT25_SR_nRDY	0x01		/* nRDY = write-in-progress */
#define	AT25_SR_WEN	0x02		/* write enable (latched) */
#define	AT25_SR_BP0	0x04		/* BP for software writeprotect */
#define	AT25_SR_BP1	0x08
#define	AT25_SR_WPEN	0x80		/* writeprotect enable */

#define	AT25_INSTR_BIT3	0x08		/* Additional address bit in instr */

#define EE_MAXADDRLEN	3		/* 24 bit addresses, up to 2 MBytes */

/* Specs often allow 5 msec for a page write, sometimes 20 msec;
 * it's important to recover from write timeouts.
 */
#define	EE_TIMEOUT	25

/*-------------------------------------------------------------------------*/

#define	io_limit	PAGE_SIZE	/* bytes */

static int at25_ee_read(void *priv, unsigned int offset,
			void *val, size_t count)
{
	struct at25_data *at25 = priv;
	char *buf = val;
	u8			command[EE_MAXADDRLEN + 1];
	u8			*cp;
	ssize_t			status;
	struct spi_transfer	t[2];
	struct spi_message	m;
	u8			instr;

	if (unlikely(offset >= at25->chip.byte_len))
		return -EINVAL;
	if ((offset + count) > at25->chip.byte_len)
		count = at25->chip.byte_len - offset;
	if (unlikely(!count))
		return -EINVAL;

	cp = command;

	instr = AT25_READ;
	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
		if (offset >= (1U << (at25->addrlen * 8)))
			instr |= AT25_INSTR_BIT3;
	*cp++ = instr;

	/* 8/16/24-bit address is written MSB first */
	switch (at25->addrlen) {
	default:	/* case 3 */
		*cp++ = offset >> 16;
		/* fall through */
	case 2:
		*cp++ = offset >> 8;
		/* fall through */
	case 1:
	case 0:	/* can't happen: for better codegen */
		*cp++ = offset >> 0;
	}

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	t[0].tx_buf = command;
	t[0].len = at25->addrlen + 1;
	spi_message_add_tail(&t[0], &m);

	t[1].rx_buf = buf;
	t[1].len = count;
	spi_message_add_tail(&t[1], &m);

	mutex_lock(&at25->lock);

	/* Read it all at once.
	 *
	 * REVISIT that's potentially a problem with large chips, if
	 * other devices on the bus need to be accessed regularly or
	 * this chip is clocked very slowly
	 */
	status = spi_sync(at25->spi, &m);
	dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n",
		count, offset, status);

	mutex_unlock(&at25->lock);
	return status;
}

static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
{
	struct at25_data *at25 = priv;
	const char *buf = val;
	int			status = 0;
	unsigned		buf_size;
	u8			*bounce;

	if (unlikely(off >= at25->chip.byte_len))
		return -EFBIG;
	if ((off + count) > at25->chip.byte_len)
		count = at25->chip.byte_len - off;
	if (unlikely(!count))
		return -EINVAL;

	/* Temp buffer starts with command and address */
	buf_size = at25->chip.page_size;
	if (buf_size > io_limit)
		buf_size = io_limit;
	bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
	if (!bounce)
		return -ENOMEM;

	/* For write, rollover is within the page ... so we write at
	 * most one page, then manually roll over to the next page.
	 */
	mutex_lock(&at25->lock);
	do {
		unsigned long	timeout, retries;
		unsigned	segment;
		unsigned	offset = (unsigned) off;
		u8		*cp = bounce;
		int		sr;
		u8		instr;

		*cp = AT25_WREN;
		status = spi_write(at25->spi, cp, 1);
		if (status < 0) {
			dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
			break;
		}

		instr = AT25_WRITE;
		if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
			if (offset >= (1U << (at25->addrlen * 8)))
				instr |= AT25_INSTR_BIT3;
		*cp++ = instr;

		/* 8/16/24-bit address is written MSB first */
		switch (at25->addrlen) {
		default:	/* case 3 */
			*cp++ = offset >> 16;
			/* fall through */
		case 2:
			*cp++ = offset >> 8;
			/* fall through */
		case 1:
		case 0:	/* can't happen: for better codegen */
			*cp++ = offset >> 0;
		}

		/* Write as much of a page as we can */
		segment = buf_size - (offset % buf_size);
		if (segment > count)
			segment = count;
		memcpy(cp, buf, segment);
		status = spi_write(at25->spi, bounce,
				segment + at25->addrlen + 1);
		dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
			segment, offset, status);
		if (status < 0)
			break;

		/* REVISIT this should detect (or prevent) failed writes
		 * to readonly sections of the EEPROM...
		 */

		/* Wait for non-busy status */
		timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
		retries = 0;
		do {

			sr = spi_w8r8(at25->spi, AT25_RDSR);
			if (sr < 0 || (sr & AT25_SR_nRDY)) {
				dev_dbg(&at25->spi->dev,
					"rdsr --> %d (%02x)\n", sr, sr);
				/* at HZ=100, this is sloooow */
				msleep(1);
				continue;
			}
			if (!(sr & AT25_SR_nRDY))
				break;
		} while (retries++ < 3 || time_before_eq(jiffies, timeout));

		if ((sr < 0) || (sr & AT25_SR_nRDY)) {
			dev_err(&at25->spi->dev,
				"write %u bytes offset %u, timeout after %u msecs\n",
				segment, offset,
				jiffies_to_msecs(jiffies -
					(timeout - EE_TIMEOUT)));
			status = -ETIMEDOUT;
			break;
		}

		off += segment;
		buf += segment;
		count -= segment;

	} while (count > 0);

	mutex_unlock(&at25->lock);

	kfree(bounce);
	return status;
}

/*-------------------------------------------------------------------------*/

static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
{
	u32 val;

	memset(chip, 0, sizeof(*chip));
	strncpy(chip->name, "at25", sizeof(chip->name));

	if (device_property_read_u32(dev, "size", &val) == 0 ||
	    device_property_read_u32(dev, "at25,byte-len", &val) == 0) {
		chip->byte_len = val;
	} else {
		dev_err(dev, "Error: missing \"size\" property\n");
		return -ENODEV;
	}

	if (device_property_read_u32(dev, "pagesize", &val) == 0 ||
	    device_property_read_u32(dev, "at25,page-size", &val) == 0) {
		chip->page_size = (u16)val;
	} else {
		dev_err(dev, "Error: missing \"pagesize\" property\n");
		return -ENODEV;
	}

	if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) {
		chip->flags = (u16)val;
	} else {
		if (device_property_read_u32(dev, "address-width", &val)) {
			dev_err(dev,
				"Error: missing \"address-width\" property\n");
			return -ENODEV;
		}
		switch (val) {
		case 9:
			chip->flags |= EE_INSTR_BIT3_IS_ADDR;
			/* fall through */
		case 8:
			chip->flags |= EE_ADDR1;
			break;
		case 16:
			chip->flags |= EE_ADDR2;
			break;
		case 24:
			chip->flags |= EE_ADDR3;
			break;
		default:
			dev_err(dev,
				"Error: bad \"address-width\" property: %u\n",
				val);
			return -ENODEV;
		}
		if (device_property_present(dev, "read-only"))
			chip->flags |= EE_READONLY;
	}
	return 0;
}

static int at25_probe(struct spi_device *spi)
{
	struct at25_data	*at25 = NULL;
	struct spi_eeprom	chip;
	int			err;
	int			sr;
	int			addrlen;

	/* Chip description */
	if (!spi->dev.platform_data) {
		err = at25_fw_to_chip(&spi->dev, &chip);
		if (err)
			return err;
	} else
		chip = *(struct spi_eeprom *)spi->dev.platform_data;

	/* For now we only support 8/16/24 bit addressing */
	if (chip.flags & EE_ADDR1)
		addrlen = 1;
	else if (chip.flags & EE_ADDR2)
		addrlen = 2;
	else if (chip.flags & EE_ADDR3)
		addrlen = 3;
	else {
		dev_dbg(&spi->dev, "unsupported address type\n");
		return -EINVAL;
	}

	/* Ping the chip ... the status register is pretty portable,
	 * unlike probing manufacturer IDs.  We do expect that system
	 * firmware didn't write it in the past few milliseconds!
	 */
	sr = spi_w8r8(spi, AT25_RDSR);
	if (sr < 0 || sr & AT25_SR_nRDY) {
		dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
		return -ENXIO;
	}

	at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL);
	if (!at25)
		return -ENOMEM;

	mutex_init(&at25->lock);
	at25->chip = chip;
	at25->spi = spi;
	spi_set_drvdata(spi, at25);
	at25->addrlen = addrlen;

	at25->nvmem_config.name = dev_name(&spi->dev);
	at25->nvmem_config.dev = &spi->dev;
	at25->nvmem_config.read_only = chip.flags & EE_READONLY;
	at25->nvmem_config.root_only = true;
	at25->nvmem_config.owner = THIS_MODULE;
	at25->nvmem_config.compat = true;
	at25->nvmem_config.base_dev = &spi->dev;
	at25->nvmem_config.reg_read = at25_ee_read;
	at25->nvmem_config.reg_write = at25_ee_write;
	at25->nvmem_config.priv = at25;
	at25->nvmem_config.stride = 4;
	at25->nvmem_config.word_size = 1;
	at25->nvmem_config.size = chip.byte_len;

	at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
	if (IS_ERR(at25->nvmem))
		return PTR_ERR(at25->nvmem);

	dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n",
		(chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024),
		(chip.byte_len < 1024) ? "Byte" : "KByte",
		at25->chip.name,
		(chip.flags & EE_READONLY) ? " (readonly)" : "",
		at25->chip.page_size);
	return 0;
}

/*-------------------------------------------------------------------------*/

static const struct of_device_id at25_of_match[] = {
	{ .compatible = "atmel,at25", },
	{ }
};
MODULE_DEVICE_TABLE(of, at25_of_match);

static struct spi_driver at25_driver = {
	.driver = {
		.name		= "at25",
		.of_match_table = at25_of_match,
	},
	.probe		= at25_probe,
};

module_spi_driver(at25_driver);

MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
MODULE_AUTHOR("David Brownell");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:at25");
Commit	Line	Data
b587b13a DB	1	/*
	2	* at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
	3	*
	4	* Copyright (C) 2006 David Brownell
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/kernel.h>
b587b13a DB	13	#include <linux/module.h>
	14	#include <linux/slab.h>
	15	#include <linux/delay.h>
	16	#include <linux/device.h>
	17	#include <linux/sched.h>
	18
5a99f570	19	#include <linux/nvmem-provider.h>
b587b13a DB	20	#include <linux/spi/spi.h>
b587b13a DB	21	#include <linux/spi/eeprom.h>
f60e7074	22	#include <linux/property.h>
b587b13a	23
3f86f14c DB	24	/*
	25	* NOTE: this is an EEPROM driver. The vagaries of product naming
	26	* mean that some AT25 products are EEPROMs, and others are FLASH.
	27	* Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
	28	* not this one!
	29	*/
	30
b587b13a DB	31	struct at25_data {
	32	struct spi_device *spi;
	33	struct mutex lock;
	34	struct spi_eeprom chip;
b587b13a	35	unsigned addrlen;
5a99f570 AL	36	struct nvmem_config nvmem_config;
5a99f570 AL	37	struct nvmem_device *nvmem;
b587b13a DB	38	};
	39
	40	#define AT25_WREN 0x06 /* latch the write enable */
	41	#define AT25_WRDI 0x04 /* reset the write enable */
	42	#define AT25_RDSR 0x05 /* read status register */
	43	#define AT25_WRSR 0x01 /* write status register */
	44	#define AT25_READ 0x03 /* read byte(s) */
	45	#define AT25_WRITE 0x02 /* write byte(s)/sector */
	46
	47	#define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
	48	#define AT25_SR_WEN 0x02 /* write enable (latched) */
	49	#define AT25_SR_BP0 0x04 /* BP for software writeprotect */
	50	#define AT25_SR_BP1 0x08
	51	#define AT25_SR_WPEN 0x80 /* writeprotect enable */
	52
b4161f0b	53	#define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */
b587b13a DB	54
	55	#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
	56
	57	/* Specs often allow 5 msec for a page write, sometimes 20 msec;
	58	* it's important to recover from write timeouts.
	59	*/
	60	#define EE_TIMEOUT 25
	61
	62	/-------------------------------------------------------------------------/
	63
	64	#define io_limit PAGE_SIZE /* bytes */
	65
01973a01 SK	66	static int at25_ee_read(void *priv, unsigned int offset,
01973a01 SK	67	void *val, size_t count)
b587b13a	68	{
01973a01 SK	69	struct at25_data *at25 = priv;
01973a01 SK	70	char *buf = val;
b587b13a DB	71	u8 command[EE_MAXADDRLEN + 1];
	72	u8 *cp;
	73	ssize_t status;
	74	struct spi_transfer t[2];
	75	struct spi_message m;
b4161f0b	76	u8 instr;
b587b13a	77
5a99f570	78	if (unlikely(offset >= at25->chip.byte_len))
01973a01	79	return -EINVAL;
5a99f570 AL	80	if ((offset + count) > at25->chip.byte_len)
5a99f570 AL	81	count = at25->chip.byte_len - offset;
14dd1ff0	82	if (unlikely(!count))
01973a01	83	return -EINVAL;
14dd1ff0	84
b587b13a	85	cp = command;
b4161f0b IS	86
	87	instr = AT25_READ;
	88	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
	89	if (offset >= (1U << (at25->addrlen * 8)))
	90	instr \|= AT25_INSTR_BIT3;
	91	*cp++ = instr;
b587b13a DB	92
	93	/* 8/16/24-bit address is written MSB first */
	94	switch (at25->addrlen) {
	95	default: /* case 3 */
	96	*cp++ = offset >> 16;
0c2ccd8c	97	/* fall through */
b587b13a DB	98	case 2:
b587b13a DB	99	*cp++ = offset >> 8;
0c2ccd8c	100	/* fall through */
b587b13a DB	101	case 1:
	102	case 0: /* can't happen: for better codegen */
	103	*cp++ = offset >> 0;
	104	}
	105
	106	spi_message_init(&m);
c84f259c	107	memset(t, 0, sizeof(t));
b587b13a DB	108
	109	t[0].tx_buf = command;
	110	t[0].len = at25->addrlen + 1;
	111	spi_message_add_tail(&t[0], &m);
	112
	113	t[1].rx_buf = buf;
	114	t[1].len = count;
	115	spi_message_add_tail(&t[1], &m);
	116
	117	mutex_lock(&at25->lock);
	118
	119	/* Read it all at once.
	120	*
	121	* REVISIT that's potentially a problem with large chips, if
	122	* other devices on the bus need to be accessed regularly or
	123	* this chip is clocked very slowly
	124	*/
	125	status = spi_sync(at25->spi, &m);
3936e4c8 AS	126	dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n",
3936e4c8 AS	127	count, offset, status);
b587b13a DB	128
b587b13a DB	129	mutex_unlock(&at25->lock);
01973a01	130	return status;
b587b13a DB	131	}
b587b13a DB	132
01973a01	133	static int at25_ee_write(void priv, unsigned int off, void val, size_t count)
b587b13a	134	{
01973a01 SK	135	struct at25_data *at25 = priv;
	136	const char *buf = val;
	137	int status = 0;
b587b13a DB	138	unsigned buf_size;
	139	u8 *bounce;
	140
5a99f570	141	if (unlikely(off >= at25->chip.byte_len))
14dd1ff0	142	return -EFBIG;
5a99f570 AL	143	if ((off + count) > at25->chip.byte_len)
5a99f570 AL	144	count = at25->chip.byte_len - off;
14dd1ff0	145	if (unlikely(!count))
01973a01	146	return -EINVAL;
14dd1ff0	147
b587b13a DB	148	/* Temp buffer starts with command and address */
	149	buf_size = at25->chip.page_size;
	150	if (buf_size > io_limit)
	151	buf_size = io_limit;
	152	bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
	153	if (!bounce)
	154	return -ENOMEM;
	155
	156	/* For write, rollover is within the page ... so we write at
	157	* most one page, then manually roll over to the next page.
	158	*/
b587b13a DB	159	mutex_lock(&at25->lock);
	160	do {
	161	unsigned long timeout, retries;
	162	unsigned segment;
	163	unsigned offset = (unsigned) off;
b4161f0b	164	u8 *cp = bounce;
f0d83679	165	int sr;
b4161f0b	166	u8 instr;
b587b13a DB	167
	168	*cp = AT25_WREN;
	169	status = spi_write(at25->spi, cp, 1);
	170	if (status < 0) {
3936e4c8	171	dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
b587b13a DB	172	break;
	173	}
	174
b4161f0b IS	175	instr = AT25_WRITE;
	176	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
	177	if (offset >= (1U << (at25->addrlen * 8)))
	178	instr \|= AT25_INSTR_BIT3;
	179	*cp++ = instr;
	180
b587b13a DB	181	/* 8/16/24-bit address is written MSB first */
	182	switch (at25->addrlen) {
	183	default: /* case 3 */
	184	*cp++ = offset >> 16;
0c2ccd8c	185	/* fall through */
b587b13a DB	186	case 2:
b587b13a DB	187	*cp++ = offset >> 8;
0c2ccd8c	188	/* fall through */
b587b13a DB	189	case 1:
	190	case 0: /* can't happen: for better codegen */
	191	*cp++ = offset >> 0;
	192	}
	193
	194	/* Write as much of a page as we can */
	195	segment = buf_size - (offset % buf_size);
	196	if (segment > count)
	197	segment = count;
	198	memcpy(cp, buf, segment);
	199	status = spi_write(at25->spi, bounce,
	200	segment + at25->addrlen + 1);
3936e4c8 AS	201	dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
3936e4c8 AS	202	segment, offset, status);
b587b13a DB	203	if (status < 0)
	204	break;
	205
	206	/* REVISIT this should detect (or prevent) failed writes
	207	* to readonly sections of the EEPROM...
	208	*/
	209
	210	/* Wait for non-busy status */
	211	timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
	212	retries = 0;
	213	do {
b587b13a DB	214
	215	sr = spi_w8r8(at25->spi, AT25_RDSR);
	216	if (sr < 0 \|\| (sr & AT25_SR_nRDY)) {
	217	dev_dbg(&at25->spi->dev,
	218	"rdsr --> %d (%02x)\n", sr, sr);
	219	/* at HZ=100, this is sloooow */
	220	msleep(1);
	221	continue;
	222	}
	223	if (!(sr & AT25_SR_nRDY))
	224	break;
	225	} while (retries++ < 3 \|\| time_before_eq(jiffies, timeout));
	226
f0d83679	227	if ((sr < 0) \|\| (sr & AT25_SR_nRDY)) {
b587b13a	228	dev_err(&at25->spi->dev,
3936e4c8	229	"write %u bytes offset %u, timeout after %u msecs\n",
b587b13a DB	230	segment, offset,
	231	jiffies_to_msecs(jiffies -
	232	(timeout - EE_TIMEOUT)));
	233	status = -ETIMEDOUT;
	234	break;
	235	}
	236
	237	off += segment;
	238	buf += segment;
	239	count -= segment;
b587b13a DB	240
	241	} while (count > 0);
	242
	243	mutex_unlock(&at25->lock);
	244
	245	kfree(bounce);
01973a01	246	return status;
b587b13a DB	247	}
b587b13a DB	248
b587b13a DB	249	/-------------------------------------------------------------------------/
b587b13a DB	250
f60e7074	251	static int at25_fw_to_chip(struct device dev, struct spi_eeprom chip)
d6ae0d57 DD	252	{
	253	u32 val;
	254
	255	memset(chip, 0, sizeof(*chip));
f60e7074	256	strncpy(chip->name, "at25", sizeof(chip->name));
d6ae0d57	257
f60e7074 MW	258	if (device_property_read_u32(dev, "size", &val) == 0 \|\|
f60e7074 MW	259	device_property_read_u32(dev, "at25,byte-len", &val) == 0) {
d6ae0d57 DD	260	chip->byte_len = val;
	261	} else {
	262	dev_err(dev, "Error: missing \"size\" property\n");
	263	return -ENODEV;
	264	}
	265
f60e7074 MW	266	if (device_property_read_u32(dev, "pagesize", &val) == 0 \|\|
f60e7074 MW	267	device_property_read_u32(dev, "at25,page-size", &val) == 0) {
d6ae0d57 DD	268	chip->page_size = (u16)val;
	269	} else {
	270	dev_err(dev, "Error: missing \"pagesize\" property\n");
	271	return -ENODEV;
	272	}
	273
f60e7074	274	if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) {
d6ae0d57 DD	275	chip->flags = (u16)val;
d6ae0d57 DD	276	} else {
f60e7074	277	if (device_property_read_u32(dev, "address-width", &val)) {
d6ae0d57 DD	278	dev_err(dev,
	279	"Error: missing \"address-width\" property\n");
	280	return -ENODEV;
	281	}
	282	switch (val) {
f8d3bc10 GU	283	case 9:
	284	chip->flags \|= EE_INSTR_BIT3_IS_ADDR;
	285	/* fall through */
d6ae0d57 DD	286	case 8:
	287	chip->flags \|= EE_ADDR1;
	288	break;
	289	case 16:
	290	chip->flags \|= EE_ADDR2;
	291	break;
	292	case 24:
	293	chip->flags \|= EE_ADDR3;
	294	break;
	295	default:
	296	dev_err(dev,
	297	"Error: bad \"address-width\" property: %u\n",
	298	val);
	299	return -ENODEV;
	300	}
f60e7074	301	if (device_property_present(dev, "read-only"))
d6ae0d57 DD	302	chip->flags \|= EE_READONLY;
	303	}
	304	return 0;
	305	}
	306
b587b13a DB	307	static int at25_probe(struct spi_device *spi)
	308	{
	309	struct at25_data *at25 = NULL;
002176db	310	struct spi_eeprom chip;
b587b13a DB	311	int err;
	312	int sr;
	313	int addrlen;
	314
	315	/* Chip description */
002176db	316	if (!spi->dev.platform_data) {
f60e7074 MW	317	err = at25_fw_to_chip(&spi->dev, &chip);
	318	if (err)
	319	return err;
002176db APS	320	} else
002176db APS	321	chip = (struct spi_eeprom )spi->dev.platform_data;
b587b13a DB	322
b587b13a DB	323	/* For now we only support 8/16/24 bit addressing */
002176db	324	if (chip.flags & EE_ADDR1)
b587b13a	325	addrlen = 1;
002176db	326	else if (chip.flags & EE_ADDR2)
b587b13a	327	addrlen = 2;
002176db	328	else if (chip.flags & EE_ADDR3)
b587b13a DB	329	addrlen = 3;
	330	else {
	331	dev_dbg(&spi->dev, "unsupported address type\n");
01fe7b43	332	return -EINVAL;
b587b13a DB	333	}
	334
	335	/* Ping the chip ... the status register is pretty portable,
	336	* unlike probing manufacturer IDs. We do expect that system
	337	* firmware didn't write it in the past few milliseconds!
	338	*/
	339	sr = spi_w8r8(spi, AT25_RDSR);
	340	if (sr < 0 \|\| sr & AT25_SR_nRDY) {
c6ca97d2	341	dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
01fe7b43	342	return -ENXIO;
b587b13a DB	343	}
b587b13a DB	344
01fe7b43 NB	345	at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL);
	346	if (!at25)
	347	return -ENOMEM;
b587b13a DB	348
b587b13a DB	349	mutex_init(&at25->lock);
002176db	350	at25->chip = chip;
96b2a45c	351	at25->spi = spi;
41ddcf67	352	spi_set_drvdata(spi, at25);
b587b13a DB	353	at25->addrlen = addrlen;
b587b13a DB	354
5a99f570 AL	355	at25->nvmem_config.name = dev_name(&spi->dev);
	356	at25->nvmem_config.dev = &spi->dev;
	357	at25->nvmem_config.read_only = chip.flags & EE_READONLY;
	358	at25->nvmem_config.root_only = true;
	359	at25->nvmem_config.owner = THIS_MODULE;
	360	at25->nvmem_config.compat = true;
	361	at25->nvmem_config.base_dev = &spi->dev;
01973a01 SK	362	at25->nvmem_config.reg_read = at25_ee_read;
	363	at25->nvmem_config.reg_write = at25_ee_write;
	364	at25->nvmem_config.priv = at25;
	365	at25->nvmem_config.stride = 4;
	366	at25->nvmem_config.word_size = 1;
	367	at25->nvmem_config.size = chip.byte_len;
5a99f570	368
96d08fb4	369	at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
5a99f570 AL	370	if (IS_ERR(at25->nvmem))
	371	return PTR_ERR(at25->nvmem);
	372
	373	dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n",
3936e4c8	374	(chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024),
5a99f570	375	(chip.byte_len < 1024) ? "Byte" : "KByte",
b587b13a	376	at25->chip.name,
002176db	377	(chip.flags & EE_READONLY) ? " (readonly)" : "",
b587b13a DB	378	at25->chip.page_size);
b587b13a DB	379	return 0;
b587b13a DB	380	}
b587b13a DB	381
b587b13a DB	382	/-------------------------------------------------------------------------/
b587b13a DB	383
fbfdb6ed JL	384	static const struct of_device_id at25_of_match[] = {
	385	{ .compatible = "atmel,at25", },
	386	{ }
	387	};
	388	MODULE_DEVICE_TABLE(of, at25_of_match);
	389
b587b13a DB	390	static struct spi_driver at25_driver = {
	391	.driver = {
	392	.name = "at25",
fbfdb6ed	393	.of_match_table = at25_of_match,
b587b13a DB	394	},
b587b13a DB	395	.probe = at25_probe,
b587b13a DB	396	};
b587b13a DB	397
a3dc3c9e	398	module_spi_driver(at25_driver);
b587b13a DB	399
	400	MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
	401	MODULE_AUTHOR("David Brownell");
	402	MODULE_LICENSE("GPL");
e0626e38	403	MODULE_ALIAS("spi:at25");