[mirror_ubuntu-focal-kernel.git] / drivers / misc / eeprom / at25.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
 *
 * Copyright (C) 2006 David Brownell
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/sched.h>

#include <linux/nvmem-provider.h>
#include <linux/spi/spi.h>
#include <linux/spi/eeprom.h>
#include <linux/property.h>

/*
 * NOTE: this is an *EEPROM* driver.  The vagaries of product naming
 * mean that some AT25 products are EEPROMs, and others are FLASH.
 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
 * not this one!
 */

struct at25_data {
	struct spi_device	*spi;
	struct mutex		lock;
	struct spi_eeprom	chip;
	unsigned		addrlen;
	struct nvmem_config	nvmem_config;
	struct nvmem_device	*nvmem;
};

#define	AT25_WREN	0x06		/* latch the write enable */
#define	AT25_WRDI	0x04		/* reset the write enable */
#define	AT25_RDSR	0x05		/* read status register */
#define	AT25_WRSR	0x01		/* write status register */
#define	AT25_READ	0x03		/* read byte(s) */
#define	AT25_WRITE	0x02		/* write byte(s)/sector */

#define	AT25_SR_nRDY	0x01		/* nRDY = write-in-progress */
#define	AT25_SR_WEN	0x02		/* write enable (latched) */
#define	AT25_SR_BP0	0x04		/* BP for software writeprotect */
#define	AT25_SR_BP1	0x08
#define	AT25_SR_WPEN	0x80		/* writeprotect enable */

#define	AT25_INSTR_BIT3	0x08		/* Additional address bit in instr */

#define EE_MAXADDRLEN	3		/* 24 bit addresses, up to 2 MBytes */

/* Specs often allow 5 msec for a page write, sometimes 20 msec;
 * it's important to recover from write timeouts.
 */
#define	EE_TIMEOUT	25

/*-------------------------------------------------------------------------*/

#define	io_limit	PAGE_SIZE	/* bytes */

static int at25_ee_read(void *priv, unsigned int offset,
			void *val, size_t count)
{
	struct at25_data *at25 = priv;
	char *buf = val;
	u8			command[EE_MAXADDRLEN + 1];
	u8			*cp;
	ssize_t			status;
	struct spi_transfer	t[2];
	struct spi_message	m;
	u8			instr;

	if (unlikely(offset >= at25->chip.byte_len))
		return -EINVAL;
	if ((offset + count) > at25->chip.byte_len)
		count = at25->chip.byte_len - offset;
	if (unlikely(!count))
		return -EINVAL;

	cp = command;

	instr = AT25_READ;
	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
		if (offset >= (1U << (at25->addrlen * 8)))
			instr |= AT25_INSTR_BIT3;
	*cp++ = instr;

	/* 8/16/24-bit address is written MSB first */
	switch (at25->addrlen) {
	default:	/* case 3 */
		*cp++ = offset >> 16;
		/* fall through */
	case 2:
		*cp++ = offset >> 8;
		/* fall through */
	case 1:
	case 0:	/* can't happen: for better codegen */
		*cp++ = offset >> 0;
	}

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	t[0].tx_buf = command;
	t[0].len = at25->addrlen + 1;
	spi_message_add_tail(&t[0], &m);

	t[1].rx_buf = buf;
	t[1].len = count;
	spi_message_add_tail(&t[1], &m);

	mutex_lock(&at25->lock);

	/* Read it all at once.
	 *
	 * REVISIT that's potentially a problem with large chips, if
	 * other devices on the bus need to be accessed regularly or
	 * this chip is clocked very slowly
	 */
	status = spi_sync(at25->spi, &m);
	dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n",
		count, offset, status);

	mutex_unlock(&at25->lock);
	return status;
}

static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
{
	struct at25_data *at25 = priv;
	const char *buf = val;
	int			status = 0;
	unsigned		buf_size;
	u8			*bounce;

	if (unlikely(off >= at25->chip.byte_len))
		return -EFBIG;
	if ((off + count) > at25->chip.byte_len)
		count = at25->chip.byte_len - off;
	if (unlikely(!count))
		return -EINVAL;

	/* Temp buffer starts with command and address */
	buf_size = at25->chip.page_size;
	if (buf_size > io_limit)
		buf_size = io_limit;
	bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
	if (!bounce)
		return -ENOMEM;

	/* For write, rollover is within the page ... so we write at
	 * most one page, then manually roll over to the next page.
	 */
	mutex_lock(&at25->lock);
	do {
		unsigned long	timeout, retries;
		unsigned	segment;
		unsigned	offset = (unsigned) off;
		u8		*cp = bounce;
		int		sr;
		u8		instr;

		*cp = AT25_WREN;
		status = spi_write(at25->spi, cp, 1);
		if (status < 0) {
			dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
			break;
		}

		instr = AT25_WRITE;
		if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
			if (offset >= (1U << (at25->addrlen * 8)))
				instr |= AT25_INSTR_BIT3;
		*cp++ = instr;

		/* 8/16/24-bit address is written MSB first */
		switch (at25->addrlen) {
		default:	/* case 3 */
			*cp++ = offset >> 16;
			/* fall through */
		case 2:
			*cp++ = offset >> 8;
			/* fall through */
		case 1:
		case 0:	/* can't happen: for better codegen */
			*cp++ = offset >> 0;
		}

		/* Write as much of a page as we can */
		segment = buf_size - (offset % buf_size);
		if (segment > count)
			segment = count;
		memcpy(cp, buf, segment);
		status = spi_write(at25->spi, bounce,
				segment + at25->addrlen + 1);
		dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
			segment, offset, status);
		if (status < 0)
			break;

		/* REVISIT this should detect (or prevent) failed writes
		 * to readonly sections of the EEPROM...
		 */

		/* Wait for non-busy status */
		timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
		retries = 0;
		do {

			sr = spi_w8r8(at25->spi, AT25_RDSR);
			if (sr < 0 || (sr & AT25_SR_nRDY)) {
				dev_dbg(&at25->spi->dev,
					"rdsr --> %d (%02x)\n", sr, sr);
				/* at HZ=100, this is sloooow */
				msleep(1);
				continue;
			}
			if (!(sr & AT25_SR_nRDY))
				break;
		} while (retries++ < 3 || time_before_eq(jiffies, timeout));

		if ((sr < 0) || (sr & AT25_SR_nRDY)) {
			dev_err(&at25->spi->dev,
				"write %u bytes offset %u, timeout after %u msecs\n",
				segment, offset,
				jiffies_to_msecs(jiffies -
					(timeout - EE_TIMEOUT)));
			status = -ETIMEDOUT;
			break;
		}

		off += segment;
		buf += segment;
		count -= segment;

	} while (count > 0);

	mutex_unlock(&at25->lock);

	kfree(bounce);
	return status;
}

/*-------------------------------------------------------------------------*/

static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
{
	u32 val;

	memset(chip, 0, sizeof(*chip));
	strncpy(chip->name, "at25", sizeof(chip->name));

	if (device_property_read_u32(dev, "size", &val) == 0 ||
	    device_property_read_u32(dev, "at25,byte-len", &val) == 0) {
		chip->byte_len = val;
	} else {
		dev_err(dev, "Error: missing \"size\" property\n");
		return -ENODEV;
	}

	if (device_property_read_u32(dev, "pagesize", &val) == 0 ||
	    device_property_read_u32(dev, "at25,page-size", &val) == 0) {
		chip->page_size = (u16)val;
	} else {
		dev_err(dev, "Error: missing \"pagesize\" property\n");
		return -ENODEV;
	}

	if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) {
		chip->flags = (u16)val;
	} else {
		if (device_property_read_u32(dev, "address-width", &val)) {
			dev_err(dev,
				"Error: missing \"address-width\" property\n");
			return -ENODEV;
		}
		switch (val) {
		case 9:
			chip->flags |= EE_INSTR_BIT3_IS_ADDR;
			/* fall through */
		case 8:
			chip->flags |= EE_ADDR1;
			break;
		case 16:
			chip->flags |= EE_ADDR2;
			break;
		case 24:
			chip->flags |= EE_ADDR3;
			break;
		default:
			dev_err(dev,
				"Error: bad \"address-width\" property: %u\n",
				val);
			return -ENODEV;
		}
		if (device_property_present(dev, "read-only"))
			chip->flags |= EE_READONLY;
	}
	return 0;
}

static int at25_probe(struct spi_device *spi)
{
	struct at25_data	*at25 = NULL;
	struct spi_eeprom	chip;
	int			err;
	int			sr;
	int			addrlen;

	/* Chip description */
	if (!spi->dev.platform_data) {
		err = at25_fw_to_chip(&spi->dev, &chip);
		if (err)
			return err;
	} else
		chip = *(struct spi_eeprom *)spi->dev.platform_data;

	/* For now we only support 8/16/24 bit addressing */
	if (chip.flags & EE_ADDR1)
		addrlen = 1;
	else if (chip.flags & EE_ADDR2)
		addrlen = 2;
	else if (chip.flags & EE_ADDR3)
		addrlen = 3;
	else {
		dev_dbg(&spi->dev, "unsupported address type\n");
		return -EINVAL;
	}

	/* Ping the chip ... the status register is pretty portable,
	 * unlike probing manufacturer IDs.  We do expect that system
	 * firmware didn't write it in the past few milliseconds!
	 */
	sr = spi_w8r8(spi, AT25_RDSR);
	if (sr < 0 || sr & AT25_SR_nRDY) {
		dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
		return -ENXIO;
	}

	at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL);
	if (!at25)
		return -ENOMEM;

	mutex_init(&at25->lock);
	at25->chip = chip;
	at25->spi = spi;
	spi_set_drvdata(spi, at25);
	at25->addrlen = addrlen;

	at25->nvmem_config.name = dev_name(&spi->dev);
	at25->nvmem_config.dev = &spi->dev;
	at25->nvmem_config.read_only = chip.flags & EE_READONLY;
	at25->nvmem_config.root_only = true;
	at25->nvmem_config.owner = THIS_MODULE;
	at25->nvmem_config.compat = true;
	at25->nvmem_config.base_dev = &spi->dev;
	at25->nvmem_config.reg_read = at25_ee_read;
	at25->nvmem_config.reg_write = at25_ee_write;
	at25->nvmem_config.priv = at25;
	at25->nvmem_config.stride = 1;
	at25->nvmem_config.word_size = 1;
	at25->nvmem_config.size = chip.byte_len;

	at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
	if (IS_ERR(at25->nvmem))
		return PTR_ERR(at25->nvmem);

	dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n",
		(chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024),
		(chip.byte_len < 1024) ? "Byte" : "KByte",
		at25->chip.name,
		(chip.flags & EE_READONLY) ? " (readonly)" : "",
		at25->chip.page_size);
	return 0;
}

/*-------------------------------------------------------------------------*/

static const struct of_device_id at25_of_match[] = {
	{ .compatible = "atmel,at25", },
	{ }
};
MODULE_DEVICE_TABLE(of, at25_of_match);

static struct spi_driver at25_driver = {
	.driver = {
		.name		= "at25",
		.of_match_table = at25_of_match,
	},
	.probe		= at25_probe,
};

module_spi_driver(at25_driver);

MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
MODULE_AUTHOR("David Brownell");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:at25");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
b587b13a DB	2	/*
	3	* at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
	4	*
	5	* Copyright (C) 2006 David Brownell
b587b13a DB	6	*/
	7
	8	#include <linux/kernel.h>
b587b13a DB	9	#include <linux/module.h>
	10	#include <linux/slab.h>
	11	#include <linux/delay.h>
	12	#include <linux/device.h>
	13	#include <linux/sched.h>
	14
5a99f570	15	#include <linux/nvmem-provider.h>
b587b13a DB	16	#include <linux/spi/spi.h>
b587b13a DB	17	#include <linux/spi/eeprom.h>
f60e7074	18	#include <linux/property.h>
b587b13a	19
3f86f14c DB	20	/*
	21	* NOTE: this is an EEPROM driver. The vagaries of product naming
	22	* mean that some AT25 products are EEPROMs, and others are FLASH.
	23	* Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
	24	* not this one!
	25	*/
	26
b587b13a DB	27	struct at25_data {
	28	struct spi_device *spi;
	29	struct mutex lock;
	30	struct spi_eeprom chip;
b587b13a	31	unsigned addrlen;
5a99f570 AL	32	struct nvmem_config nvmem_config;
5a99f570 AL	33	struct nvmem_device *nvmem;
b587b13a DB	34	};
	35
	36	#define AT25_WREN 0x06 /* latch the write enable */
	37	#define AT25_WRDI 0x04 /* reset the write enable */
	38	#define AT25_RDSR 0x05 /* read status register */
	39	#define AT25_WRSR 0x01 /* write status register */
	40	#define AT25_READ 0x03 /* read byte(s) */
	41	#define AT25_WRITE 0x02 /* write byte(s)/sector */
	42
	43	#define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
	44	#define AT25_SR_WEN 0x02 /* write enable (latched) */
	45	#define AT25_SR_BP0 0x04 /* BP for software writeprotect */
	46	#define AT25_SR_BP1 0x08
	47	#define AT25_SR_WPEN 0x80 /* writeprotect enable */
	48
b4161f0b	49	#define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */
b587b13a DB	50
	51	#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
	52
	53	/* Specs often allow 5 msec for a page write, sometimes 20 msec;
	54	* it's important to recover from write timeouts.
	55	*/
	56	#define EE_TIMEOUT 25
	57
	58	/-------------------------------------------------------------------------/
	59
	60	#define io_limit PAGE_SIZE /* bytes */
	61
01973a01 SK	62	static int at25_ee_read(void *priv, unsigned int offset,
01973a01 SK	63	void *val, size_t count)
b587b13a	64	{
01973a01 SK	65	struct at25_data *at25 = priv;
01973a01 SK	66	char *buf = val;
b587b13a DB	67	u8 command[EE_MAXADDRLEN + 1];
	68	u8 *cp;
	69	ssize_t status;
	70	struct spi_transfer t[2];
	71	struct spi_message m;
b4161f0b	72	u8 instr;
b587b13a	73
5a99f570	74	if (unlikely(offset >= at25->chip.byte_len))
01973a01	75	return -EINVAL;
5a99f570 AL	76	if ((offset + count) > at25->chip.byte_len)
5a99f570 AL	77	count = at25->chip.byte_len - offset;
14dd1ff0	78	if (unlikely(!count))
01973a01	79	return -EINVAL;
14dd1ff0	80
b587b13a	81	cp = command;
b4161f0b IS	82
	83	instr = AT25_READ;
	84	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
	85	if (offset >= (1U << (at25->addrlen * 8)))
	86	instr \|= AT25_INSTR_BIT3;
	87	*cp++ = instr;
b587b13a DB	88
	89	/* 8/16/24-bit address is written MSB first */
	90	switch (at25->addrlen) {
	91	default: /* case 3 */
	92	*cp++ = offset >> 16;
0c2ccd8c	93	/* fall through */
b587b13a DB	94	case 2:
b587b13a DB	95	*cp++ = offset >> 8;
0c2ccd8c	96	/* fall through */
b587b13a DB	97	case 1:
	98	case 0: /* can't happen: for better codegen */
	99	*cp++ = offset >> 0;
	100	}
	101
	102	spi_message_init(&m);
c84f259c	103	memset(t, 0, sizeof(t));
b587b13a DB	104
	105	t[0].tx_buf = command;
	106	t[0].len = at25->addrlen + 1;
	107	spi_message_add_tail(&t[0], &m);
	108
	109	t[1].rx_buf = buf;
	110	t[1].len = count;
	111	spi_message_add_tail(&t[1], &m);
	112
	113	mutex_lock(&at25->lock);
	114
	115	/* Read it all at once.
	116	*
	117	* REVISIT that's potentially a problem with large chips, if
	118	* other devices on the bus need to be accessed regularly or
	119	* this chip is clocked very slowly
	120	*/
	121	status = spi_sync(at25->spi, &m);
3936e4c8 AS	122	dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n",
3936e4c8 AS	123	count, offset, status);
b587b13a DB	124
b587b13a DB	125	mutex_unlock(&at25->lock);
01973a01	126	return status;
b587b13a DB	127	}
b587b13a DB	128
01973a01	129	static int at25_ee_write(void priv, unsigned int off, void val, size_t count)
b587b13a	130	{
01973a01 SK	131	struct at25_data *at25 = priv;
	132	const char *buf = val;
	133	int status = 0;
b587b13a DB	134	unsigned buf_size;
	135	u8 *bounce;
	136
5a99f570	137	if (unlikely(off >= at25->chip.byte_len))
14dd1ff0	138	return -EFBIG;
5a99f570 AL	139	if ((off + count) > at25->chip.byte_len)
5a99f570 AL	140	count = at25->chip.byte_len - off;
14dd1ff0	141	if (unlikely(!count))
01973a01	142	return -EINVAL;
14dd1ff0	143
b587b13a DB	144	/* Temp buffer starts with command and address */
	145	buf_size = at25->chip.page_size;
	146	if (buf_size > io_limit)
	147	buf_size = io_limit;
	148	bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
	149	if (!bounce)
	150	return -ENOMEM;
	151
	152	/* For write, rollover is within the page ... so we write at
	153	* most one page, then manually roll over to the next page.
	154	*/
b587b13a DB	155	mutex_lock(&at25->lock);
	156	do {
	157	unsigned long timeout, retries;
	158	unsigned segment;
	159	unsigned offset = (unsigned) off;
b4161f0b	160	u8 *cp = bounce;
f0d83679	161	int sr;
b4161f0b	162	u8 instr;
b587b13a DB	163
	164	*cp = AT25_WREN;
	165	status = spi_write(at25->spi, cp, 1);
	166	if (status < 0) {
3936e4c8	167	dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
b587b13a DB	168	break;
	169	}
	170
b4161f0b IS	171	instr = AT25_WRITE;
	172	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
	173	if (offset >= (1U << (at25->addrlen * 8)))
	174	instr \|= AT25_INSTR_BIT3;
	175	*cp++ = instr;
	176
b587b13a DB	177	/* 8/16/24-bit address is written MSB first */
	178	switch (at25->addrlen) {
	179	default: /* case 3 */
	180	*cp++ = offset >> 16;
0c2ccd8c	181	/* fall through */
b587b13a DB	182	case 2:
b587b13a DB	183	*cp++ = offset >> 8;
0c2ccd8c	184	/* fall through */
b587b13a DB	185	case 1:
	186	case 0: /* can't happen: for better codegen */
	187	*cp++ = offset >> 0;
	188	}
	189
	190	/* Write as much of a page as we can */
	191	segment = buf_size - (offset % buf_size);
	192	if (segment > count)
	193	segment = count;
	194	memcpy(cp, buf, segment);
	195	status = spi_write(at25->spi, bounce,
	196	segment + at25->addrlen + 1);
3936e4c8 AS	197	dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
3936e4c8 AS	198	segment, offset, status);
b587b13a DB	199	if (status < 0)
	200	break;
	201
	202	/* REVISIT this should detect (or prevent) failed writes
	203	* to readonly sections of the EEPROM...
	204	*/
	205
	206	/* Wait for non-busy status */
	207	timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
	208	retries = 0;
	209	do {
b587b13a DB	210
	211	sr = spi_w8r8(at25->spi, AT25_RDSR);
	212	if (sr < 0 \|\| (sr & AT25_SR_nRDY)) {
	213	dev_dbg(&at25->spi->dev,
	214	"rdsr --> %d (%02x)\n", sr, sr);
	215	/* at HZ=100, this is sloooow */
	216	msleep(1);
	217	continue;
	218	}
	219	if (!(sr & AT25_SR_nRDY))
	220	break;
	221	} while (retries++ < 3 \|\| time_before_eq(jiffies, timeout));
	222
f0d83679	223	if ((sr < 0) \|\| (sr & AT25_SR_nRDY)) {
b587b13a	224	dev_err(&at25->spi->dev,
3936e4c8	225	"write %u bytes offset %u, timeout after %u msecs\n",
b587b13a DB	226	segment, offset,
	227	jiffies_to_msecs(jiffies -
	228	(timeout - EE_TIMEOUT)));
	229	status = -ETIMEDOUT;
	230	break;
	231	}
	232
	233	off += segment;
	234	buf += segment;
	235	count -= segment;
b587b13a DB	236
	237	} while (count > 0);
	238
	239	mutex_unlock(&at25->lock);
	240
	241	kfree(bounce);
01973a01	242	return status;
b587b13a DB	243	}
b587b13a DB	244
b587b13a DB	245	/-------------------------------------------------------------------------/
b587b13a DB	246
f60e7074	247	static int at25_fw_to_chip(struct device dev, struct spi_eeprom chip)
d6ae0d57 DD	248	{
	249	u32 val;
	250
	251	memset(chip, 0, sizeof(*chip));
f60e7074	252	strncpy(chip->name, "at25", sizeof(chip->name));
d6ae0d57	253
f60e7074 MW	254	if (device_property_read_u32(dev, "size", &val) == 0 \|\|
f60e7074 MW	255	device_property_read_u32(dev, "at25,byte-len", &val) == 0) {
d6ae0d57 DD	256	chip->byte_len = val;
	257	} else {
	258	dev_err(dev, "Error: missing \"size\" property\n");
	259	return -ENODEV;
	260	}
	261
f60e7074 MW	262	if (device_property_read_u32(dev, "pagesize", &val) == 0 \|\|
f60e7074 MW	263	device_property_read_u32(dev, "at25,page-size", &val) == 0) {
d6ae0d57 DD	264	chip->page_size = (u16)val;
	265	} else {
	266	dev_err(dev, "Error: missing \"pagesize\" property\n");
	267	return -ENODEV;
	268	}
	269
f60e7074	270	if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) {
d6ae0d57 DD	271	chip->flags = (u16)val;
d6ae0d57 DD	272	} else {
f60e7074	273	if (device_property_read_u32(dev, "address-width", &val)) {
d6ae0d57 DD	274	dev_err(dev,
	275	"Error: missing \"address-width\" property\n");
	276	return -ENODEV;
	277	}
	278	switch (val) {
f8d3bc10 GU	279	case 9:
	280	chip->flags \|= EE_INSTR_BIT3_IS_ADDR;
	281	/* fall through */
d6ae0d57 DD	282	case 8:
	283	chip->flags \|= EE_ADDR1;
	284	break;
	285	case 16:
	286	chip->flags \|= EE_ADDR2;
	287	break;
	288	case 24:
	289	chip->flags \|= EE_ADDR3;
	290	break;
	291	default:
	292	dev_err(dev,
	293	"Error: bad \"address-width\" property: %u\n",
	294	val);
	295	return -ENODEV;
	296	}
f60e7074	297	if (device_property_present(dev, "read-only"))
d6ae0d57 DD	298	chip->flags \|= EE_READONLY;
	299	}
	300	return 0;
	301	}
	302
b587b13a DB	303	static int at25_probe(struct spi_device *spi)
	304	{
	305	struct at25_data *at25 = NULL;
002176db	306	struct spi_eeprom chip;
b587b13a DB	307	int err;
	308	int sr;
	309	int addrlen;
	310
	311	/* Chip description */
002176db	312	if (!spi->dev.platform_data) {
f60e7074 MW	313	err = at25_fw_to_chip(&spi->dev, &chip);
	314	if (err)
	315	return err;
002176db APS	316	} else
002176db APS	317	chip = (struct spi_eeprom )spi->dev.platform_data;
b587b13a DB	318
b587b13a DB	319	/* For now we only support 8/16/24 bit addressing */
002176db	320	if (chip.flags & EE_ADDR1)
b587b13a	321	addrlen = 1;
002176db	322	else if (chip.flags & EE_ADDR2)
b587b13a	323	addrlen = 2;
002176db	324	else if (chip.flags & EE_ADDR3)
b587b13a DB	325	addrlen = 3;
	326	else {
	327	dev_dbg(&spi->dev, "unsupported address type\n");
01fe7b43	328	return -EINVAL;
b587b13a DB	329	}
	330
	331	/* Ping the chip ... the status register is pretty portable,
	332	* unlike probing manufacturer IDs. We do expect that system
	333	* firmware didn't write it in the past few milliseconds!
	334	*/
	335	sr = spi_w8r8(spi, AT25_RDSR);
	336	if (sr < 0 \|\| sr & AT25_SR_nRDY) {
c6ca97d2	337	dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
01fe7b43	338	return -ENXIO;
b587b13a DB	339	}
b587b13a DB	340
01fe7b43 NB	341	at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL);
	342	if (!at25)
	343	return -ENOMEM;
b587b13a DB	344
b587b13a DB	345	mutex_init(&at25->lock);
002176db	346	at25->chip = chip;
96b2a45c	347	at25->spi = spi;
41ddcf67	348	spi_set_drvdata(spi, at25);
b587b13a DB	349	at25->addrlen = addrlen;
b587b13a DB	350
5a99f570 AL	351	at25->nvmem_config.name = dev_name(&spi->dev);
	352	at25->nvmem_config.dev = &spi->dev;
	353	at25->nvmem_config.read_only = chip.flags & EE_READONLY;
	354	at25->nvmem_config.root_only = true;
	355	at25->nvmem_config.owner = THIS_MODULE;
	356	at25->nvmem_config.compat = true;
	357	at25->nvmem_config.base_dev = &spi->dev;
01973a01 SK	358	at25->nvmem_config.reg_read = at25_ee_read;
	359	at25->nvmem_config.reg_write = at25_ee_write;
	360	at25->nvmem_config.priv = at25;
356cf06f	361	at25->nvmem_config.stride = 1;
01973a01 SK	362	at25->nvmem_config.word_size = 1;
01973a01 SK	363	at25->nvmem_config.size = chip.byte_len;
5a99f570	364
96d08fb4	365	at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
5a99f570 AL	366	if (IS_ERR(at25->nvmem))
	367	return PTR_ERR(at25->nvmem);
	368
	369	dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n",
3936e4c8	370	(chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024),
5a99f570	371	(chip.byte_len < 1024) ? "Byte" : "KByte",
b587b13a	372	at25->chip.name,
002176db	373	(chip.flags & EE_READONLY) ? " (readonly)" : "",
b587b13a DB	374	at25->chip.page_size);
b587b13a DB	375	return 0;
b587b13a DB	376	}
b587b13a DB	377
b587b13a DB	378	/-------------------------------------------------------------------------/
b587b13a DB	379
fbfdb6ed JL	380	static const struct of_device_id at25_of_match[] = {
	381	{ .compatible = "atmel,at25", },
	382	{ }
	383	};
	384	MODULE_DEVICE_TABLE(of, at25_of_match);
	385
b587b13a DB	386	static struct spi_driver at25_driver = {
	387	.driver = {
	388	.name = "at25",
fbfdb6ed	389	.of_match_table = at25_of_match,
b587b13a DB	390	},
b587b13a DB	391	.probe = at25_probe,
b587b13a DB	392	};
b587b13a DB	393
a3dc3c9e	394	module_spi_driver(at25_driver);
b587b13a DB	395
	396	MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
	397	MODULE_AUTHOR("David Brownell");
	398	MODULE_LICENSE("GPL");
e0626e38	399	MODULE_ALIAS("spi:at25");