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1 | /* SPDX-License-Identifier: GPL-2.0 |
2 | * | |
3 | * Copyright 2019-2020 HabanaLabs, Ltd. | |
4 | * All Rights Reserved. | |
5 | * | |
6 | */ | |
7 | ||
8 | #ifndef GAUDIP_H_ | |
9 | #define GAUDIP_H_ | |
10 | ||
11 | #include <uapi/misc/habanalabs.h> | |
12 | #include "habanalabs.h" | |
13 | #include "include/hl_boot_if.h" | |
14 | #include "include/gaudi/gaudi_packets.h" | |
15 | #include "include/gaudi/gaudi.h" | |
16 | #include "include/gaudi/gaudi_async_events.h" | |
17 | ||
18 | #define NUMBER_OF_EXT_HW_QUEUES 12 | |
19 | #define NUMBER_OF_CMPLT_QUEUES NUMBER_OF_EXT_HW_QUEUES | |
20 | #define NUMBER_OF_CPU_HW_QUEUES 1 | |
21 | #define NUMBER_OF_INT_HW_QUEUES 100 | |
22 | #define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \ | |
23 | NUMBER_OF_CPU_HW_QUEUES + \ | |
24 | NUMBER_OF_INT_HW_QUEUES) | |
25 | ||
26 | /* | |
27 | * Number of MSI interrupts IDS: | |
28 | * Each completion queue has 1 ID | |
29 | * The event queue has 1 ID | |
30 | */ | |
31 | #define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + \ | |
32 | NUMBER_OF_CPU_HW_QUEUES) | |
33 | ||
34 | #if (NUMBER_OF_INTERRUPTS > GAUDI_MSI_ENTRIES) | |
35 | #error "Number of MSI interrupts must be smaller or equal to GAUDI_MSI_ENTRIES" | |
36 | #endif | |
37 | ||
38 | #define QMAN_FENCE_TIMEOUT_USEC 10000 /* 10 ms */ | |
39 | ||
40 | #define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */ | |
41 | ||
42 | #define GAUDI_MAX_CLK_FREQ 2200000000ull /* 2200 MHz */ | |
43 | ||
44 | #define MAX_POWER_DEFAULT 200000 /* 200W */ | |
45 | ||
46 | #define GAUDI_CPU_TIMEOUT_USEC 15000000 /* 15s */ | |
47 | ||
48 | #define TPC_ENABLED_MASK 0xFF | |
49 | ||
50 | #define GAUDI_HBM_SIZE_32GB 0x800000000ull | |
51 | #define GAUDI_HBM_DEVICES 4 | |
52 | #define GAUDI_HBM_CHANNELS 8 | |
53 | #define GAUDI_HBM_CFG_BASE (mmHBM0_BASE - CFG_BASE) | |
54 | #define GAUDI_HBM_CFG_OFFSET (mmHBM1_BASE - mmHBM0_BASE) | |
55 | ||
56 | #define DMA_MAX_TRANSFER_SIZE U32_MAX | |
57 | ||
58 | #define GAUDI_DEFAULT_CARD_NAME "HL2000" | |
59 | ||
60 | #define PCI_DMA_NUMBER_OF_CHNLS 3 | |
61 | #define HBM_DMA_NUMBER_OF_CHNLS 5 | |
62 | #define DMA_NUMBER_OF_CHNLS (PCI_DMA_NUMBER_OF_CHNLS + \ | |
63 | HBM_DMA_NUMBER_OF_CHNLS) | |
64 | ||
65 | #define MME_NUMBER_OF_SLAVE_ENGINES 2 | |
66 | #define MME_NUMBER_OF_ENGINES (MME_NUMBER_OF_MASTER_ENGINES + \ | |
67 | MME_NUMBER_OF_SLAVE_ENGINES) | |
68 | #define MME_NUMBER_OF_QMANS (MME_NUMBER_OF_MASTER_ENGINES * \ | |
69 | QMAN_STREAMS) | |
70 | ||
71 | #define QMAN_STREAMS 4 | |
72 | ||
73 | #define DMA_QMAN_OFFSET (mmDMA1_QM_BASE - mmDMA0_QM_BASE) | |
74 | #define TPC_QMAN_OFFSET (mmTPC1_QM_BASE - mmTPC0_QM_BASE) | |
75 | #define MME_QMAN_OFFSET (mmMME1_QM_BASE - mmMME0_QM_BASE) | |
76 | #define NIC_MACRO_QMAN_OFFSET (mmNIC1_QM0_BASE - mmNIC0_QM0_BASE) | |
77 | ||
78 | #define TPC_CFG_OFFSET (mmTPC1_CFG_BASE - mmTPC0_CFG_BASE) | |
79 | ||
80 | #define DMA_CORE_OFFSET (mmDMA1_CORE_BASE - mmDMA0_CORE_BASE) | |
81 | ||
82 | #define SIF_RTR_CTRL_OFFSET (mmSIF_RTR_CTRL_1_BASE - mmSIF_RTR_CTRL_0_BASE) | |
83 | ||
84 | #define NIF_RTR_CTRL_OFFSET (mmNIF_RTR_CTRL_1_BASE - mmNIF_RTR_CTRL_0_BASE) | |
85 | ||
86 | #define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE) | |
87 | #define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE) | |
88 | ||
89 | #define NUM_OF_SOB_IN_BLOCK \ | |
90 | (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \ | |
91 | mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2) | |
92 | ||
93 | #define NUM_OF_MONITORS_IN_BLOCK \ | |
94 | (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 - \ | |
95 | mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2) | |
96 | ||
97 | ||
98 | /* DRAM Memory Map */ | |
99 | ||
100 | #define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */ | |
101 | #define MMU_PAGE_TABLES_SIZE 0x0BF00000 /* 191MB */ | |
102 | #define MMU_CACHE_MNG_SIZE 0x00100000 /* 1MB */ | |
103 | #define RESERVED 0x04000000 /* 64MB */ | |
104 | ||
105 | #define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE | |
106 | #define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE) | |
107 | #define MMU_CACHE_MNG_ADDR (MMU_PAGE_TABLES_ADDR + MMU_PAGE_TABLES_SIZE) | |
108 | ||
109 | #define DRAM_DRIVER_END_ADDR (MMU_CACHE_MNG_ADDR + MMU_CACHE_MNG_SIZE +\ | |
110 | RESERVED) | |
111 | ||
112 | #define DRAM_BASE_ADDR_USER 0x20000000 | |
113 | ||
114 | #if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER) | |
115 | #error "Driver must reserve no more than 512MB" | |
116 | #endif | |
117 | ||
118 | /* Internal QMANs PQ sizes */ | |
119 | ||
120 | #define MME_QMAN_LENGTH 64 | |
121 | #define MME_QMAN_SIZE_IN_BYTES (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) | |
122 | ||
123 | #define HBM_DMA_QMAN_LENGTH 64 | |
124 | #define HBM_DMA_QMAN_SIZE_IN_BYTES \ | |
125 | (HBM_DMA_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) | |
126 | ||
127 | #define TPC_QMAN_LENGTH 64 | |
128 | #define TPC_QMAN_SIZE_IN_BYTES (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) | |
129 | ||
130 | #define SRAM_USER_BASE_OFFSET GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START | |
131 | ||
132 | /* Virtual address space */ | |
133 | #define VA_HOST_SPACE_START 0x1000000000000ull /* 256TB */ | |
134 | #define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 1TB */ | |
135 | #define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \ | |
136 | VA_HOST_SPACE_START) /* 767TB */ | |
137 | ||
138 | #define HW_CAP_PLL 0x00000001 | |
139 | #define HW_CAP_HBM 0x00000002 | |
140 | #define HW_CAP_MMU 0x00000004 | |
141 | #define HW_CAP_MME 0x00000008 | |
142 | #define HW_CAP_CPU 0x00000010 | |
143 | #define HW_CAP_PCI_DMA 0x00000020 | |
144 | #define HW_CAP_MSI 0x00000040 | |
145 | #define HW_CAP_CPU_Q 0x00000080 | |
146 | #define HW_CAP_HBM_DMA 0x00000100 | |
147 | #define HW_CAP_CLK_GATE 0x00000200 | |
148 | #define HW_CAP_SRAM_SCRAMBLER 0x00000400 | |
149 | #define HW_CAP_HBM_SCRAMBLER 0x00000800 | |
150 | ||
151 | #define HW_CAP_TPC0 0x01000000 | |
152 | #define HW_CAP_TPC1 0x02000000 | |
153 | #define HW_CAP_TPC2 0x04000000 | |
154 | #define HW_CAP_TPC3 0x08000000 | |
155 | #define HW_CAP_TPC4 0x10000000 | |
156 | #define HW_CAP_TPC5 0x20000000 | |
157 | #define HW_CAP_TPC6 0x40000000 | |
158 | #define HW_CAP_TPC7 0x80000000 | |
159 | #define HW_CAP_TPC_MASK 0xFF000000 | |
160 | #define HW_CAP_TPC_SHIFT 24 | |
161 | ||
162 | #define GAUDI_CPU_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 39)) >> 39) | |
163 | #define GAUDI_PCI_TO_CPU_ADDR(addr) \ | |
164 | do { \ | |
165 | (addr) &= ~GENMASK_ULL(49, 39); \ | |
166 | (addr) |= BIT_ULL(39); \ | |
167 | } while (0) | |
168 | #define GAUDI_CPU_TO_PCI_ADDR(addr, extension) \ | |
169 | do { \ | |
170 | (addr) &= ~GENMASK_ULL(49, 39); \ | |
171 | (addr) |= (u64) (extension) << 39; \ | |
172 | } while (0) | |
173 | ||
174 | enum gaudi_dma_channels { | |
175 | GAUDI_PCI_DMA_1, | |
176 | GAUDI_PCI_DMA_2, | |
177 | GAUDI_PCI_DMA_3, | |
178 | GAUDI_HBM_DMA_1, | |
179 | GAUDI_HBM_DMA_2, | |
180 | GAUDI_HBM_DMA_3, | |
181 | GAUDI_HBM_DMA_4, | |
182 | GAUDI_HBM_DMA_5, | |
183 | GAUDI_DMA_MAX | |
184 | }; | |
185 | ||
186 | enum gaudi_tpc_mask { | |
187 | GAUDI_TPC_MASK_TPC0 = 0x01, | |
188 | GAUDI_TPC_MASK_TPC1 = 0x02, | |
189 | GAUDI_TPC_MASK_TPC2 = 0x04, | |
190 | GAUDI_TPC_MASK_TPC3 = 0x08, | |
191 | GAUDI_TPC_MASK_TPC4 = 0x10, | |
192 | GAUDI_TPC_MASK_TPC5 = 0x20, | |
193 | GAUDI_TPC_MASK_TPC6 = 0x40, | |
194 | GAUDI_TPC_MASK_TPC7 = 0x80, | |
195 | GAUDI_TPC_MASK_ALL = 0xFF | |
196 | }; | |
197 | ||
198 | /** | |
199 | * struct gaudi_internal_qman_info - Internal QMAN information. | |
200 | * @pq_kernel_addr: Kernel address of the PQ memory area in the host. | |
201 | * @pq_dma_addr: DMA address of the PQ memory area in the host. | |
202 | * @pq_size: Size of allocated host memory for PQ. | |
203 | */ | |
204 | struct gaudi_internal_qman_info { | |
205 | void *pq_kernel_addr; | |
206 | dma_addr_t pq_dma_addr; | |
207 | size_t pq_size; | |
208 | }; | |
209 | ||
210 | /** | |
211 | * struct gaudi_device - ASIC specific manage structure. | |
212 | * @armcp_info_get: get information on device from ArmCP | |
213 | * @hw_queues_lock: protects the H/W queues from concurrent access. | |
214 | * @clk_gate_mutex: protects code areas that require clock gating to be disabled | |
215 | * temporarily | |
216 | * @internal_qmans: Internal QMANs information. The array size is larger than | |
217 | * the actual number of internal queues because they are not in | |
218 | * consecutive order. | |
219 | * @hbm_bar_cur_addr: current address of HBM PCI bar. | |
220 | * @max_freq_value: current max clk frequency. | |
221 | * @events_stat: array that holds histogram of all received events. | |
222 | * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset | |
223 | * @hw_cap_initialized: This field contains a bit per H/W engine. When that | |
224 | * engine is initialized, that bit is set by the driver to | |
225 | * signal we can use this engine in later code paths. | |
226 | * Each bit is cleared upon reset of its corresponding H/W | |
227 | * engine. | |
228 | * @multi_msi_mode: whether we are working in multi MSI single MSI mode. | |
229 | * Multi MSI is possible only with IOMMU enabled. | |
230 | * @ext_queue_idx: helper index for external queues initialization. | |
231 | */ | |
232 | struct gaudi_device { | |
233 | int (*armcp_info_get)(struct hl_device *hdev); | |
234 | ||
235 | /* TODO: remove hw_queues_lock after moving to scheduler code */ | |
236 | spinlock_t hw_queues_lock; | |
237 | struct mutex clk_gate_mutex; | |
238 | ||
239 | struct gaudi_internal_qman_info internal_qmans[GAUDI_QUEUE_ID_SIZE]; | |
240 | ||
241 | u64 hbm_bar_cur_addr; | |
242 | u64 max_freq_value; | |
243 | ||
244 | u32 events_stat[GAUDI_EVENT_SIZE]; | |
245 | u32 events_stat_aggregate[GAUDI_EVENT_SIZE]; | |
246 | u32 hw_cap_initialized; | |
247 | u8 multi_msi_mode; | |
248 | u8 ext_queue_idx; | |
249 | }; | |
250 | ||
bcaf4152 OG |
251 | void gaudi_add_device_attr(struct hl_device *hdev, |
252 | struct attribute_group *dev_attr_grp); | |
253 | void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq); | |
254 | int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk); | |
255 | ||
ac0ae6a9 | 256 | #endif /* GAUDIP_H_ */ |