[mirror_ubuntu-artful-kernel.git] / drivers / misc / mei / pci-me.c

/*
 *
 * Intel Management Engine Interface (Intel MEI) Linux driver
 * Copyright (c) 2003-2012, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/aio.h>
#include <linux/pci.h>
#include <linux/poll.h>
#include <linux/ioctl.h>
#include <linux/cdev.h>
#include <linux/sched.h>
#include <linux/uuid.h>
#include <linux/compat.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>
#include <linux/miscdevice.h>

#include <linux/pm_runtime.h>

#include <linux/mei.h>

#include "mei_dev.h"
#include "client.h"
#include "hw-me-regs.h"
#include "hw-me.h"

/* mei_pci_tbl - PCI Device ID Table */
static const struct pci_device_id mei_me_pci_tbl[] = {
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82946GZ)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G35)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82Q965)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G965)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GM965)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GME965)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q35)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82G33)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q33)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82X38)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_3200)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_6)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_7)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_8)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_9)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_10)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_1)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_3)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_4)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_1)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_3)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_4)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_1)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_CPT_1)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PBG_1)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_1)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_3)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_H)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_W)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_LP)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_HR)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_WPT_LP)},

	/* required last entry */
	{0, }
};

MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);

/**
 * mei_quirk_probe - probe for devices that doesn't valid ME interface
 *
 * @pdev: PCI device structure
 * @ent: entry into pci_device_table
 *
 * returns true if ME Interface is valid, false otherwise
 */
static bool mei_me_quirk_probe(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{
	u32 reg;
	/* Cougar Point || Patsburg */
	if (ent->device == MEI_DEV_ID_CPT_1 ||
	    ent->device == MEI_DEV_ID_PBG_1) {
		pci_read_config_dword(pdev, PCI_CFG_HFS_2, &reg);
		/* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
		if ((reg & 0x600) == 0x200)
			goto no_mei;
	}

	/* Lynx Point */
	if (ent->device == MEI_DEV_ID_LPT_H  ||
	    ent->device == MEI_DEV_ID_LPT_W  ||
	    ent->device == MEI_DEV_ID_LPT_HR) {
		/* Read ME FW Status check for SPS Firmware */
		pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
		/* if bits [19:16] = 15, running SPS Firmware */
		if ((reg & 0xf0000) == 0xf0000)
			goto no_mei;
	}

	return true;

no_mei:
	dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
	return false;
}
/**
 * mei_probe - Device Initialization Routine
 *
 * @pdev: PCI device structure
 * @ent: entry in kcs_pci_tbl
 *
 * returns 0 on success, <0 on failure.
 */
static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct mei_device *dev;
	struct mei_me_hw *hw;
	int err;


	if (!mei_me_quirk_probe(pdev, ent)) {
		err = -ENODEV;
		goto end;
	}

	/* enable pci dev */
	err = pci_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "failed to enable pci device.\n");
		goto end;
	}
	/* set PCI host mastering  */
	pci_set_master(pdev);
	/* pci request regions for mei driver */
	err = pci_request_regions(pdev, KBUILD_MODNAME);
	if (err) {
		dev_err(&pdev->dev, "failed to get pci regions.\n");
		goto disable_device;
	}

	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
	    dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {

		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
		if (err)
			err = dma_set_coherent_mask(&pdev->dev,
						    DMA_BIT_MASK(32));
	}
	if (err) {
		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
		goto release_regions;
	}


	/* allocates and initializes the mei dev structure */
	dev = mei_me_dev_init(pdev);
	if (!dev) {
		err = -ENOMEM;
		goto release_regions;
	}
	hw = to_me_hw(dev);
	/* mapping  IO device memory */
	hw->mem_addr = pci_iomap(pdev, 0, 0);
	if (!hw->mem_addr) {
		dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
		err = -ENOMEM;
		goto free_device;
	}
	pci_enable_msi(pdev);

	 /* request and enable interrupt */
	if (pci_dev_msi_enabled(pdev))
		err = request_threaded_irq(pdev->irq,
			NULL,
			mei_me_irq_thread_handler,
			IRQF_ONESHOT, KBUILD_MODNAME, dev);
	else
		err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			IRQF_SHARED, KBUILD_MODNAME, dev);

	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
		       pdev->irq);
		goto disable_msi;
	}

	if (mei_start(dev)) {
		dev_err(&pdev->dev, "init hw failure.\n");
		err = -ENODEV;
		goto release_irq;
	}

	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);

	err = mei_register(dev);
	if (err)
		goto release_irq;

	pci_set_drvdata(pdev, dev);

	schedule_delayed_work(&dev->timer_work, HZ);

	if (mei_pg_is_enabled(dev))
		pm_runtime_put_noidle(&pdev->dev);

	dev_dbg(&pdev->dev, "initialization successful.\n");

	return 0;

release_irq:
	mei_cancel_work(dev);
	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
disable_msi:
	pci_disable_msi(pdev);
	pci_iounmap(pdev, hw->mem_addr);
free_device:
	kfree(dev);
release_regions:
	pci_release_regions(pdev);
disable_device:
	pci_disable_device(pdev);
end:
	dev_err(&pdev->dev, "initialization failed.\n");
	return err;
}

/**
 * mei_remove - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_remove is called by the PCI subsystem to alert the driver
 * that it should release a PCI device.
 */
static void mei_me_remove(struct pci_dev *pdev)
{
	struct mei_device *dev;
	struct mei_me_hw *hw;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return;

	if (mei_pg_is_enabled(dev))
		pm_runtime_get_noresume(&pdev->dev);

	hw = to_me_hw(dev);


	dev_dbg(&pdev->dev, "stop\n");
	mei_stop(dev);

	/* disable interrupts */
	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	if (hw->mem_addr)
		pci_iounmap(pdev, hw->mem_addr);

	mei_deregister(dev);

	kfree(dev);

	pci_release_regions(pdev);
	pci_disable_device(pdev);


}
#ifdef CONFIG_PM_SLEEP
static int mei_me_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev = pci_get_drvdata(pdev);

	if (!dev)
		return -ENODEV;

	dev_dbg(&pdev->dev, "suspend\n");

	mei_stop(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	return 0;
}

static int mei_me_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int err;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	pci_enable_msi(pdev);

	/* request and enable interrupt */
	if (pci_dev_msi_enabled(pdev))
		err = request_threaded_irq(pdev->irq,
			NULL,
			mei_me_irq_thread_handler,
			IRQF_ONESHOT, KBUILD_MODNAME, dev);
	else
		err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			IRQF_SHARED, KBUILD_MODNAME, dev);

	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
				pdev->irq);
		return err;
	}

	err = mei_restart(dev);
	if (err)
		return err;

	/* Start timer if stopped in suspend */
	schedule_delayed_work(&dev->timer_work, HZ);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

#ifdef CONFIG_PM_RUNTIME
static int mei_me_pm_runtime_idle(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;

	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;
	if (mei_write_is_idle(dev))
		pm_schedule_suspend(device, MEI_ME_RPM_TIMEOUT * 2);

	return -EBUSY;
}

static int mei_me_pm_runtime_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int ret;

	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	if (mei_write_is_idle(dev))
		ret = mei_me_pg_set_sync(dev);
	else
		ret = -EAGAIN;

	mutex_unlock(&dev->device_lock);

	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);

	return ret;
}

static int mei_me_pm_runtime_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int ret;

	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	ret = mei_me_pg_unset_sync(dev);

	mutex_unlock(&dev->device_lock);

	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);

	return ret;
}
#endif /* CONFIG_PM_RUNTIME */

#ifdef CONFIG_PM
static const struct dev_pm_ops mei_me_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
				mei_me_pci_resume)
	SET_RUNTIME_PM_OPS(
		mei_me_pm_runtime_suspend,
		mei_me_pm_runtime_resume,
		mei_me_pm_runtime_idle)
};

#define MEI_ME_PM_OPS	(&mei_me_pm_ops)
#else
#define MEI_ME_PM_OPS	NULL
#endif /* CONFIG_PM */
/*
 *  PCI driver structure
 */
static struct pci_driver mei_me_driver = {
	.name = KBUILD_MODNAME,
	.id_table = mei_me_pci_tbl,
	.probe = mei_me_probe,
	.remove = mei_me_remove,
	.shutdown = mei_me_remove,
	.driver.pm = MEI_ME_PM_OPS,
};

module_pci_driver(mei_me_driver);

MODULE_AUTHOR("Intel Corporation");
MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2703d4b2 TW	1	/*
	2	*
	3	* Intel Management Engine Interface (Intel MEI) Linux driver
	4	* Copyright (c) 2003-2012, Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	*/
2703d4b2 TW	16	#include <linux/module.h>
	17	#include <linux/moduleparam.h>
	18	#include <linux/kernel.h>
	19	#include <linux/device.h>
	20	#include <linux/fs.h>
	21	#include <linux/errno.h>
	22	#include <linux/types.h>
	23	#include <linux/fcntl.h>
	24	#include <linux/aio.h>
	25	#include <linux/pci.h>
	26	#include <linux/poll.h>
2703d4b2 TW	27	#include <linux/ioctl.h>
	28	#include <linux/cdev.h>
	29	#include <linux/sched.h>
	30	#include <linux/uuid.h>
	31	#include <linux/compat.h>
	32	#include <linux/jiffies.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/miscdevice.h>
	35
180ea05b TW	36	#include <linux/pm_runtime.h>
180ea05b TW	37
2703d4b2 TW	38	#include <linux/mei.h>
	39
	40	#include "mei_dev.h"
2703d4b2	41	#include "client.h"
6e4cd27a TW	42	#include "hw-me-regs.h"
6e4cd27a TW	43	#include "hw-me.h"
2703d4b2	44
2703d4b2	45	/* mei_pci_tbl - PCI Device ID Table */
a05f8f86	46	static const struct pci_device_id mei_me_pci_tbl[] = {
2703d4b2 TW	47	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82946GZ)},
	48	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G35)},
	49	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82Q965)},
	50	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G965)},
	51	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GM965)},
	52	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GME965)},
	53	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q35)},
	54	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82G33)},
	55	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q33)},
	56	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82X38)},
	57	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_3200)},
	58	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_6)},
	59	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_7)},
	60	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_8)},
	61	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_9)},
	62	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_10)},
	63	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_1)},
	64	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_2)},
	65	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_3)},
	66	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_4)},
	67	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_1)},
	68	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_2)},
	69	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_3)},
	70	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_4)},
	71	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_1)},
	72	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_2)},
	73	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_CPT_1)},
	74	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PBG_1)},
	75	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_1)},
	76	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_2)},
	77	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_3)},
76a96359	78	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_H)},
838b3a6d	79	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_W)},
2703d4b2	80	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_LP)},
76a96359 TW	81	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_HR)},
76a96359 TW	82	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_WPT_LP)},
2703d4b2 TW	83
	84	/* required last entry */
	85	{0, }
	86	};
	87
b68301e9	88	MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
2703d4b2	89
2703d4b2 TW	90	/**
2703d4b2 TW	91	* mei_quirk_probe - probe for devices that doesn't valid ME interface
393b148f	92	*
2703d4b2 TW	93	* @pdev: PCI device structure
	94	* @ent: entry into pci_device_table
	95	*
	96	* returns true if ME Interface is valid, false otherwise
	97	*/
b68301e9	98	static bool mei_me_quirk_probe(struct pci_dev *pdev,
2703d4b2 TW	99	const struct pci_device_id *ent)
	100	{
	101	u32 reg;
5e6533a6 TW	102	/* Cougar Point \|\| Patsburg */
	103	if (ent->device == MEI_DEV_ID_CPT_1 \|\|
	104	ent->device == MEI_DEV_ID_PBG_1) {
	105	pci_read_config_dword(pdev, PCI_CFG_HFS_2, &reg);
	106	/* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
	107	if ((reg & 0x600) == 0x200)
	108	goto no_mei;
2703d4b2	109	}
5e6533a6 TW	110
	111	/* Lynx Point */
	112	if (ent->device == MEI_DEV_ID_LPT_H \|\|
	113	ent->device == MEI_DEV_ID_LPT_W \|\|
	114	ent->device == MEI_DEV_ID_LPT_HR) {
	115	/* Read ME FW Status check for SPS Firmware */
	116	pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
	117	/* if bits [19:16] = 15, running SPS Firmware */
	118	if ((reg & 0xf0000) == 0xf0000)
	119	goto no_mei;
	120	}
	121
2703d4b2	122	return true;
5e6533a6 TW	123
	124	no_mei:
	125	dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
	126	return false;
2703d4b2 TW	127	}
	128	/**
	129	* mei_probe - Device Initialization Routine
	130	*
	131	* @pdev: PCI device structure
	132	* @ent: entry in kcs_pci_tbl
	133	*
	134	* returns 0 on success, <0 on failure.
	135	*/
b68301e9	136	static int mei_me_probe(struct pci_dev pdev, const struct pci_device_id ent)
2703d4b2 TW	137	{
2703d4b2 TW	138	struct mei_device *dev;
52c34561	139	struct mei_me_hw *hw;
2703d4b2 TW	140	int err;
2703d4b2 TW	141
2703d4b2	142
b68301e9	143	if (!mei_me_quirk_probe(pdev, ent)) {
2703d4b2 TW	144	err = -ENODEV;
	145	goto end;
	146	}
	147
2703d4b2 TW	148	/* enable pci dev */
	149	err = pci_enable_device(pdev);
	150	if (err) {
	151	dev_err(&pdev->dev, "failed to enable pci device.\n");
	152	goto end;
	153	}
	154	/* set PCI host mastering */
	155	pci_set_master(pdev);
	156	/* pci request regions for mei driver */
	157	err = pci_request_regions(pdev, KBUILD_MODNAME);
	158	if (err) {
	159	dev_err(&pdev->dev, "failed to get pci regions.\n");
	160	goto disable_device;
	161	}
3ecfb168 TW	162
	163	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) \|\|
	164	dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
	165
	166	err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
	167	if (err)
	168	err = dma_set_coherent_mask(&pdev->dev,
	169	DMA_BIT_MASK(32));
	170	}
	171	if (err) {
	172	dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
	173	goto release_regions;
	174	}
	175
	176
2703d4b2	177	/* allocates and initializes the mei dev structure */
52c34561	178	dev = mei_me_dev_init(pdev);
2703d4b2 TW	179	if (!dev) {
	180	err = -ENOMEM;
	181	goto release_regions;
	182	}
52c34561	183	hw = to_me_hw(dev);
2703d4b2	184	/* mapping IO device memory */
52c34561 TW	185	hw->mem_addr = pci_iomap(pdev, 0, 0);
52c34561 TW	186	if (!hw->mem_addr) {
2703d4b2 TW	187	dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
	188	err = -ENOMEM;
	189	goto free_device;
	190	}
	191	pci_enable_msi(pdev);
	192
	193	/* request and enable interrupt */
	194	if (pci_dev_msi_enabled(pdev))
	195	err = request_threaded_irq(pdev->irq,
	196	NULL,
06ecd645	197	mei_me_irq_thread_handler,
2703d4b2 TW	198	IRQF_ONESHOT, KBUILD_MODNAME, dev);
	199	else
	200	err = request_threaded_irq(pdev->irq,
06ecd645 TW	201	mei_me_irq_quick_handler,
06ecd645 TW	202	mei_me_irq_thread_handler,
2703d4b2 TW	203	IRQF_SHARED, KBUILD_MODNAME, dev);
	204
	205	if (err) {
	206	dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
	207	pdev->irq);
	208	goto disable_msi;
	209	}
	210
c4d589be	211	if (mei_start(dev)) {
2703d4b2 TW	212	dev_err(&pdev->dev, "init hw failure.\n");
	213	err = -ENODEV;
	214	goto release_irq;
	215	}
	216
180ea05b TW	217	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	218	pm_runtime_use_autosuspend(&pdev->dev);
	219
30e53bb8	220	err = mei_register(dev);
2703d4b2 TW	221	if (err)
	222	goto release_irq;
	223
2703d4b2 TW	224	pci_set_drvdata(pdev, dev);
2703d4b2 TW	225
2703d4b2 TW	226	schedule_delayed_work(&dev->timer_work, HZ);
2703d4b2 TW	227
180ea05b TW	228	if (mei_pg_is_enabled(dev))
	229	pm_runtime_put_noidle(&pdev->dev);
	230
c4e87b52	231	dev_dbg(&pdev->dev, "initialization successful.\n");
2703d4b2 TW	232
	233	return 0;
	234
	235	release_irq:
dc844b0d	236	mei_cancel_work(dev);
2703d4b2	237	mei_disable_interrupts(dev);
2703d4b2 TW	238	free_irq(pdev->irq, dev);
	239	disable_msi:
	240	pci_disable_msi(pdev);
52c34561	241	pci_iounmap(pdev, hw->mem_addr);
2703d4b2 TW	242	free_device:
	243	kfree(dev);
	244	release_regions:
	245	pci_release_regions(pdev);
	246	disable_device:
	247	pci_disable_device(pdev);
	248	end:
2703d4b2 TW	249	dev_err(&pdev->dev, "initialization failed.\n");
	250	return err;
	251	}
	252
	253	/**
	254	* mei_remove - Device Removal Routine
	255	*
	256	* @pdev: PCI device structure
	257	*
	258	* mei_remove is called by the PCI subsystem to alert the driver
	259	* that it should release a PCI device.
	260	*/
b68301e9	261	static void mei_me_remove(struct pci_dev *pdev)
2703d4b2 TW	262	{
2703d4b2 TW	263	struct mei_device *dev;
52c34561	264	struct mei_me_hw *hw;
2703d4b2	265
2703d4b2 TW	266	dev = pci_get_drvdata(pdev);
	267	if (!dev)
	268	return;
	269
180ea05b TW	270	if (mei_pg_is_enabled(dev))
	271	pm_runtime_get_noresume(&pdev->dev);
	272
52c34561 TW	273	hw = to_me_hw(dev);
52c34561 TW	274
2703d4b2	275
ed6f7ac1	276	dev_dbg(&pdev->dev, "stop\n");
7cb035d9	277	mei_stop(dev);
2703d4b2	278
2703d4b2 TW	279	/* disable interrupts */
	280	mei_disable_interrupts(dev);
	281
	282	free_irq(pdev->irq, dev);
	283	pci_disable_msi(pdev);
2703d4b2	284
52c34561 TW	285	if (hw->mem_addr)
52c34561 TW	286	pci_iounmap(pdev, hw->mem_addr);
2703d4b2	287
30e53bb8 TW	288	mei_deregister(dev);
30e53bb8 TW	289
2703d4b2 TW	290	kfree(dev);
	291
	292	pci_release_regions(pdev);
	293	pci_disable_device(pdev);
	294
2703d4b2 TW	295
2703d4b2 TW	296	}
16833257	297	#ifdef CONFIG_PM_SLEEP
b68301e9	298	static int mei_me_pci_suspend(struct device *device)
2703d4b2 TW	299	{
	300	struct pci_dev *pdev = to_pci_dev(device);
	301	struct mei_device *dev = pci_get_drvdata(pdev);
2703d4b2 TW	302
	303	if (!dev)
	304	return -ENODEV;
2703d4b2	305
ed6f7ac1	306	dev_dbg(&pdev->dev, "suspend\n");
2703d4b2	307
7cb035d9 TW	308	mei_stop(dev);
	309
	310	mei_disable_interrupts(dev);
2703d4b2 TW	311
	312	free_irq(pdev->irq, dev);
	313	pci_disable_msi(pdev);
	314
7cb035d9	315	return 0;
2703d4b2 TW	316	}
2703d4b2 TW	317
b68301e9	318	static int mei_me_pci_resume(struct device *device)
2703d4b2 TW	319	{
	320	struct pci_dev *pdev = to_pci_dev(device);
	321	struct mei_device *dev;
	322	int err;
	323
	324	dev = pci_get_drvdata(pdev);
	325	if (!dev)
	326	return -ENODEV;
	327
	328	pci_enable_msi(pdev);
	329
	330	/* request and enable interrupt */
	331	if (pci_dev_msi_enabled(pdev))
	332	err = request_threaded_irq(pdev->irq,
	333	NULL,
06ecd645	334	mei_me_irq_thread_handler,
2703d4b2 TW	335	IRQF_ONESHOT, KBUILD_MODNAME, dev);
	336	else
	337	err = request_threaded_irq(pdev->irq,
06ecd645 TW	338	mei_me_irq_quick_handler,
06ecd645 TW	339	mei_me_irq_thread_handler,
2703d4b2 TW	340	IRQF_SHARED, KBUILD_MODNAME, dev);
	341
	342	if (err) {
	343	dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
	344	pdev->irq);
	345	return err;
	346	}
	347
33ec0826 TW	348	err = mei_restart(dev);
	349	if (err)
	350	return err;
2703d4b2 TW	351
	352	/* Start timer if stopped in suspend */
	353	schedule_delayed_work(&dev->timer_work, HZ);
	354
33ec0826	355	return 0;
2703d4b2	356	}
180ea05b TW	357	#endif /* CONFIG_PM_SLEEP */
	358
	359	#ifdef CONFIG_PM_RUNTIME
	360	static int mei_me_pm_runtime_idle(struct device *device)
	361	{
	362	struct pci_dev *pdev = to_pci_dev(device);
	363	struct mei_device *dev;
	364
	365	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
	366
	367	dev = pci_get_drvdata(pdev);
	368	if (!dev)
	369	return -ENODEV;
	370	if (mei_write_is_idle(dev))
	371	pm_schedule_suspend(device, MEI_ME_RPM_TIMEOUT * 2);
	372
	373	return -EBUSY;
	374	}
	375
	376	static int mei_me_pm_runtime_suspend(struct device *device)
	377	{
	378	struct pci_dev *pdev = to_pci_dev(device);
	379	struct mei_device *dev;
	380	int ret;
	381
	382	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
	383
	384	dev = pci_get_drvdata(pdev);
	385	if (!dev)
	386	return -ENODEV;
	387
	388	mutex_lock(&dev->device_lock);
	389
	390	if (mei_write_is_idle(dev))
	391	ret = mei_me_pg_set_sync(dev);
	392	else
	393	ret = -EAGAIN;
	394
	395	mutex_unlock(&dev->device_lock);
	396
	397	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
	398
	399	return ret;
	400	}
	401
	402	static int mei_me_pm_runtime_resume(struct device *device)
	403	{
	404	struct pci_dev *pdev = to_pci_dev(device);
	405	struct mei_device *dev;
	406	int ret;
	407
	408	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
	409
	410	dev = pci_get_drvdata(pdev);
	411	if (!dev)
	412	return -ENODEV;
	413
	414	mutex_lock(&dev->device_lock);
	415
	416	ret = mei_me_pg_unset_sync(dev);
	417
	418	mutex_unlock(&dev->device_lock);
	419
	420	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
421
422	return ret;
423	}
424	#endif /* CONFIG_PM_RUNTIME */
425
426	#ifdef CONFIG_PM
427	static const struct dev_pm_ops mei_me_pm_ops = {
428	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
429	mei_me_pci_resume)
430	SET_RUNTIME_PM_OPS(
431	mei_me_pm_runtime_suspend,
432	mei_me_pm_runtime_resume,
433	mei_me_pm_runtime_idle)
434	};
16833257	435
b68301e9	436	#define MEI_ME_PM_OPS (&mei_me_pm_ops)
2703d4b2	437	#else
b68301e9	438	#define MEI_ME_PM_OPS NULL
180ea05b	439	#endif /* CONFIG_PM */
2703d4b2 TW	440	/*
	441	* PCI driver structure
	442	*/
b68301e9	443	static struct pci_driver mei_me_driver = {
2703d4b2	444	.name = KBUILD_MODNAME,
b68301e9 TW	445	.id_table = mei_me_pci_tbl,
	446	.probe = mei_me_probe,
	447	.remove = mei_me_remove,
	448	.shutdown = mei_me_remove,
	449	.driver.pm = MEI_ME_PM_OPS,
2703d4b2 TW	450	};
2703d4b2 TW	451
b68301e9	452	module_pci_driver(mei_me_driver);
2703d4b2 TW	453
	454	MODULE_AUTHOR("Intel Corporation");
	455	MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
	456	MODULE_LICENSE("GPL v2");