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Commit | Line | Data |
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2703d4b2 TW |
1 | /* |
2 | * | |
3 | * Intel Management Engine Interface (Intel MEI) Linux driver | |
4 | * Copyright (c) 2003-2012, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | */ | |
2703d4b2 TW |
16 | #include <linux/module.h> |
17 | #include <linux/moduleparam.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/fs.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/fcntl.h> | |
2703d4b2 TW |
24 | #include <linux/pci.h> |
25 | #include <linux/poll.h> | |
2703d4b2 TW |
26 | #include <linux/ioctl.h> |
27 | #include <linux/cdev.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/uuid.h> | |
30 | #include <linux/compat.h> | |
31 | #include <linux/jiffies.h> | |
32 | #include <linux/interrupt.h> | |
2703d4b2 | 33 | |
989561de | 34 | #include <linux/pm_domain.h> |
180ea05b TW |
35 | #include <linux/pm_runtime.h> |
36 | ||
2703d4b2 TW |
37 | #include <linux/mei.h> |
38 | ||
39 | #include "mei_dev.h" | |
2703d4b2 | 40 | #include "client.h" |
6e4cd27a TW |
41 | #include "hw-me-regs.h" |
42 | #include "hw-me.h" | |
2703d4b2 | 43 | |
2703d4b2 | 44 | /* mei_pci_tbl - PCI Device ID Table */ |
a05f8f86 | 45 | static const struct pci_device_id mei_me_pci_tbl[] = { |
8d929d48 AU |
46 | {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, mei_me_legacy_cfg)}, |
47 | {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, mei_me_legacy_cfg)}, | |
48 | {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, mei_me_legacy_cfg)}, | |
49 | {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, mei_me_legacy_cfg)}, | |
50 | {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, mei_me_legacy_cfg)}, | |
51 | {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, mei_me_legacy_cfg)}, | |
52 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, mei_me_legacy_cfg)}, | |
53 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, mei_me_legacy_cfg)}, | |
54 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, mei_me_legacy_cfg)}, | |
55 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, mei_me_legacy_cfg)}, | |
56 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, mei_me_legacy_cfg)}, | |
57 | ||
58 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, mei_me_legacy_cfg)}, | |
59 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, mei_me_legacy_cfg)}, | |
60 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, mei_me_legacy_cfg)}, | |
61 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, mei_me_legacy_cfg)}, | |
62 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, mei_me_legacy_cfg)}, | |
63 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, mei_me_legacy_cfg)}, | |
64 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, mei_me_legacy_cfg)}, | |
65 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, mei_me_legacy_cfg)}, | |
66 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, mei_me_legacy_cfg)}, | |
67 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, mei_me_ich_cfg)}, | |
68 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, mei_me_ich_cfg)}, | |
69 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, mei_me_ich_cfg)}, | |
70 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, mei_me_ich_cfg)}, | |
71 | ||
72 | {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)}, | |
73 | {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)}, | |
c919951d TW |
74 | {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)}, |
75 | {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)}, | |
8d929d48 AU |
76 | {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)}, |
77 | {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)}, | |
78 | {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)}, | |
edca5ea3 AU |
79 | {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_pch8_sps_cfg)}, |
80 | {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_pch8_sps_cfg)}, | |
81 | {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch8_cfg)}, | |
82 | {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_pch8_sps_cfg)}, | |
83 | {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch8_cfg)}, | |
84 | {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, mei_me_pch8_cfg)}, | |
2703d4b2 | 85 | |
1625c7ec TW |
86 | {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, mei_me_pch8_cfg)}, |
87 | {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, mei_me_pch8_cfg)}, | |
8c57cac1 TW |
88 | {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, mei_me_pch8_sps_cfg)}, |
89 | {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, mei_me_pch8_sps_cfg)}, | |
1625c7ec | 90 | |
dd16f6cd TW |
91 | {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, mei_me_pch8_cfg)}, |
92 | {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, mei_me_pch8_cfg)}, | |
93 | ||
2703d4b2 TW |
94 | /* required last entry */ |
95 | {0, } | |
96 | }; | |
97 | ||
b68301e9 | 98 | MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); |
2703d4b2 | 99 | |
bbd6d050 | 100 | #ifdef CONFIG_PM |
e13fa90c TW |
101 | static inline void mei_me_set_pm_domain(struct mei_device *dev); |
102 | static inline void mei_me_unset_pm_domain(struct mei_device *dev); | |
103 | #else | |
104 | static inline void mei_me_set_pm_domain(struct mei_device *dev) {} | |
105 | static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} | |
bbd6d050 | 106 | #endif /* CONFIG_PM */ |
e13fa90c | 107 | |
2703d4b2 | 108 | /** |
ce23139c | 109 | * mei_me_quirk_probe - probe for devices that doesn't valid ME interface |
393b148f | 110 | * |
2703d4b2 | 111 | * @pdev: PCI device structure |
c919951d | 112 | * @cfg: per generation config |
2703d4b2 | 113 | * |
a8605ea2 | 114 | * Return: true if ME Interface is valid, false otherwise |
2703d4b2 | 115 | */ |
b68301e9 | 116 | static bool mei_me_quirk_probe(struct pci_dev *pdev, |
c919951d | 117 | const struct mei_cfg *cfg) |
2703d4b2 | 118 | { |
c919951d TW |
119 | if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { |
120 | dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); | |
121 | return false; | |
5e6533a6 TW |
122 | } |
123 | ||
2703d4b2 TW |
124 | return true; |
125 | } | |
c919951d | 126 | |
2703d4b2 | 127 | /** |
ce23139c | 128 | * mei_me_probe - Device Initialization Routine |
2703d4b2 TW |
129 | * |
130 | * @pdev: PCI device structure | |
131 | * @ent: entry in kcs_pci_tbl | |
132 | * | |
a8605ea2 | 133 | * Return: 0 on success, <0 on failure. |
2703d4b2 | 134 | */ |
b68301e9 | 135 | static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
2703d4b2 | 136 | { |
8d929d48 | 137 | const struct mei_cfg *cfg = (struct mei_cfg *)(ent->driver_data); |
2703d4b2 | 138 | struct mei_device *dev; |
52c34561 | 139 | struct mei_me_hw *hw; |
1fa55b4e | 140 | unsigned int irqflags; |
2703d4b2 TW |
141 | int err; |
142 | ||
2703d4b2 | 143 | |
c919951d TW |
144 | if (!mei_me_quirk_probe(pdev, cfg)) |
145 | return -ENODEV; | |
2703d4b2 | 146 | |
2703d4b2 TW |
147 | /* enable pci dev */ |
148 | err = pci_enable_device(pdev); | |
149 | if (err) { | |
150 | dev_err(&pdev->dev, "failed to enable pci device.\n"); | |
151 | goto end; | |
152 | } | |
153 | /* set PCI host mastering */ | |
154 | pci_set_master(pdev); | |
155 | /* pci request regions for mei driver */ | |
156 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
157 | if (err) { | |
158 | dev_err(&pdev->dev, "failed to get pci regions.\n"); | |
159 | goto disable_device; | |
160 | } | |
3ecfb168 TW |
161 | |
162 | if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || | |
163 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
164 | ||
165 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
166 | if (err) | |
167 | err = dma_set_coherent_mask(&pdev->dev, | |
168 | DMA_BIT_MASK(32)); | |
169 | } | |
170 | if (err) { | |
171 | dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); | |
172 | goto release_regions; | |
173 | } | |
174 | ||
175 | ||
2703d4b2 | 176 | /* allocates and initializes the mei dev structure */ |
8d929d48 | 177 | dev = mei_me_dev_init(pdev, cfg); |
2703d4b2 TW |
178 | if (!dev) { |
179 | err = -ENOMEM; | |
180 | goto release_regions; | |
181 | } | |
52c34561 | 182 | hw = to_me_hw(dev); |
2703d4b2 | 183 | /* mapping IO device memory */ |
52c34561 TW |
184 | hw->mem_addr = pci_iomap(pdev, 0, 0); |
185 | if (!hw->mem_addr) { | |
2703d4b2 TW |
186 | dev_err(&pdev->dev, "mapping I/O device memory failure.\n"); |
187 | err = -ENOMEM; | |
188 | goto free_device; | |
189 | } | |
190 | pci_enable_msi(pdev); | |
191 | ||
192 | /* request and enable interrupt */ | |
1fa55b4e AU |
193 | irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; |
194 | ||
195 | err = request_threaded_irq(pdev->irq, | |
06ecd645 TW |
196 | mei_me_irq_quick_handler, |
197 | mei_me_irq_thread_handler, | |
1fa55b4e | 198 | irqflags, KBUILD_MODNAME, dev); |
2703d4b2 TW |
199 | if (err) { |
200 | dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", | |
201 | pdev->irq); | |
202 | goto disable_msi; | |
203 | } | |
204 | ||
c4d589be | 205 | if (mei_start(dev)) { |
2703d4b2 TW |
206 | dev_err(&pdev->dev, "init hw failure.\n"); |
207 | err = -ENODEV; | |
208 | goto release_irq; | |
209 | } | |
210 | ||
180ea05b TW |
211 | pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); |
212 | pm_runtime_use_autosuspend(&pdev->dev); | |
213 | ||
f3d8e878 | 214 | err = mei_register(dev, &pdev->dev); |
2703d4b2 | 215 | if (err) |
1f7e489a | 216 | goto stop; |
2703d4b2 | 217 | |
2703d4b2 TW |
218 | pci_set_drvdata(pdev, dev); |
219 | ||
2703d4b2 TW |
220 | schedule_delayed_work(&dev->timer_work, HZ); |
221 | ||
e13fa90c TW |
222 | /* |
223 | * For not wake-able HW runtime pm framework | |
224 | * can't be used on pci device level. | |
225 | * Use domain runtime pm callbacks instead. | |
226 | */ | |
227 | if (!pci_dev_run_wake(pdev)) | |
228 | mei_me_set_pm_domain(dev); | |
229 | ||
180ea05b TW |
230 | if (mei_pg_is_enabled(dev)) |
231 | pm_runtime_put_noidle(&pdev->dev); | |
232 | ||
c4e87b52 | 233 | dev_dbg(&pdev->dev, "initialization successful.\n"); |
2703d4b2 TW |
234 | |
235 | return 0; | |
236 | ||
1f7e489a AU |
237 | stop: |
238 | mei_stop(dev); | |
2703d4b2 | 239 | release_irq: |
dc844b0d | 240 | mei_cancel_work(dev); |
2703d4b2 | 241 | mei_disable_interrupts(dev); |
2703d4b2 TW |
242 | free_irq(pdev->irq, dev); |
243 | disable_msi: | |
244 | pci_disable_msi(pdev); | |
52c34561 | 245 | pci_iounmap(pdev, hw->mem_addr); |
2703d4b2 TW |
246 | free_device: |
247 | kfree(dev); | |
248 | release_regions: | |
249 | pci_release_regions(pdev); | |
250 | disable_device: | |
251 | pci_disable_device(pdev); | |
252 | end: | |
2703d4b2 TW |
253 | dev_err(&pdev->dev, "initialization failed.\n"); |
254 | return err; | |
255 | } | |
256 | ||
257 | /** | |
ce23139c | 258 | * mei_me_remove - Device Removal Routine |
2703d4b2 TW |
259 | * |
260 | * @pdev: PCI device structure | |
261 | * | |
262 | * mei_remove is called by the PCI subsystem to alert the driver | |
263 | * that it should release a PCI device. | |
264 | */ | |
b68301e9 | 265 | static void mei_me_remove(struct pci_dev *pdev) |
2703d4b2 TW |
266 | { |
267 | struct mei_device *dev; | |
52c34561 | 268 | struct mei_me_hw *hw; |
2703d4b2 | 269 | |
2703d4b2 TW |
270 | dev = pci_get_drvdata(pdev); |
271 | if (!dev) | |
272 | return; | |
273 | ||
180ea05b TW |
274 | if (mei_pg_is_enabled(dev)) |
275 | pm_runtime_get_noresume(&pdev->dev); | |
276 | ||
52c34561 TW |
277 | hw = to_me_hw(dev); |
278 | ||
2703d4b2 | 279 | |
ed6f7ac1 | 280 | dev_dbg(&pdev->dev, "stop\n"); |
7cb035d9 | 281 | mei_stop(dev); |
2703d4b2 | 282 | |
e13fa90c TW |
283 | if (!pci_dev_run_wake(pdev)) |
284 | mei_me_unset_pm_domain(dev); | |
285 | ||
2703d4b2 TW |
286 | /* disable interrupts */ |
287 | mei_disable_interrupts(dev); | |
288 | ||
289 | free_irq(pdev->irq, dev); | |
290 | pci_disable_msi(pdev); | |
2703d4b2 | 291 | |
52c34561 TW |
292 | if (hw->mem_addr) |
293 | pci_iounmap(pdev, hw->mem_addr); | |
2703d4b2 | 294 | |
30e53bb8 TW |
295 | mei_deregister(dev); |
296 | ||
2703d4b2 TW |
297 | kfree(dev); |
298 | ||
299 | pci_release_regions(pdev); | |
300 | pci_disable_device(pdev); | |
301 | ||
2703d4b2 TW |
302 | |
303 | } | |
16833257 | 304 | #ifdef CONFIG_PM_SLEEP |
b68301e9 | 305 | static int mei_me_pci_suspend(struct device *device) |
2703d4b2 TW |
306 | { |
307 | struct pci_dev *pdev = to_pci_dev(device); | |
308 | struct mei_device *dev = pci_get_drvdata(pdev); | |
2703d4b2 TW |
309 | |
310 | if (!dev) | |
311 | return -ENODEV; | |
2703d4b2 | 312 | |
ed6f7ac1 | 313 | dev_dbg(&pdev->dev, "suspend\n"); |
2703d4b2 | 314 | |
7cb035d9 TW |
315 | mei_stop(dev); |
316 | ||
317 | mei_disable_interrupts(dev); | |
2703d4b2 TW |
318 | |
319 | free_irq(pdev->irq, dev); | |
320 | pci_disable_msi(pdev); | |
321 | ||
7cb035d9 | 322 | return 0; |
2703d4b2 TW |
323 | } |
324 | ||
b68301e9 | 325 | static int mei_me_pci_resume(struct device *device) |
2703d4b2 TW |
326 | { |
327 | struct pci_dev *pdev = to_pci_dev(device); | |
328 | struct mei_device *dev; | |
1fa55b4e | 329 | unsigned int irqflags; |
2703d4b2 TW |
330 | int err; |
331 | ||
332 | dev = pci_get_drvdata(pdev); | |
333 | if (!dev) | |
334 | return -ENODEV; | |
335 | ||
336 | pci_enable_msi(pdev); | |
337 | ||
1fa55b4e AU |
338 | irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; |
339 | ||
2703d4b2 | 340 | /* request and enable interrupt */ |
1fa55b4e | 341 | err = request_threaded_irq(pdev->irq, |
06ecd645 TW |
342 | mei_me_irq_quick_handler, |
343 | mei_me_irq_thread_handler, | |
1fa55b4e | 344 | irqflags, KBUILD_MODNAME, dev); |
2703d4b2 TW |
345 | |
346 | if (err) { | |
347 | dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", | |
348 | pdev->irq); | |
349 | return err; | |
350 | } | |
351 | ||
33ec0826 TW |
352 | err = mei_restart(dev); |
353 | if (err) | |
354 | return err; | |
2703d4b2 TW |
355 | |
356 | /* Start timer if stopped in suspend */ | |
357 | schedule_delayed_work(&dev->timer_work, HZ); | |
358 | ||
33ec0826 | 359 | return 0; |
2703d4b2 | 360 | } |
180ea05b TW |
361 | #endif /* CONFIG_PM_SLEEP */ |
362 | ||
bbd6d050 | 363 | #ifdef CONFIG_PM |
180ea05b TW |
364 | static int mei_me_pm_runtime_idle(struct device *device) |
365 | { | |
366 | struct pci_dev *pdev = to_pci_dev(device); | |
367 | struct mei_device *dev; | |
368 | ||
369 | dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n"); | |
370 | ||
371 | dev = pci_get_drvdata(pdev); | |
372 | if (!dev) | |
373 | return -ENODEV; | |
374 | if (mei_write_is_idle(dev)) | |
d5d83f8a | 375 | pm_runtime_autosuspend(device); |
180ea05b TW |
376 | |
377 | return -EBUSY; | |
378 | } | |
379 | ||
380 | static int mei_me_pm_runtime_suspend(struct device *device) | |
381 | { | |
382 | struct pci_dev *pdev = to_pci_dev(device); | |
383 | struct mei_device *dev; | |
384 | int ret; | |
385 | ||
386 | dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n"); | |
387 | ||
388 | dev = pci_get_drvdata(pdev); | |
389 | if (!dev) | |
390 | return -ENODEV; | |
391 | ||
392 | mutex_lock(&dev->device_lock); | |
393 | ||
394 | if (mei_write_is_idle(dev)) | |
2d1995fc | 395 | ret = mei_me_pg_enter_sync(dev); |
180ea05b TW |
396 | else |
397 | ret = -EAGAIN; | |
398 | ||
399 | mutex_unlock(&dev->device_lock); | |
400 | ||
401 | dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret); | |
402 | ||
403 | return ret; | |
404 | } | |
405 | ||
406 | static int mei_me_pm_runtime_resume(struct device *device) | |
407 | { | |
408 | struct pci_dev *pdev = to_pci_dev(device); | |
409 | struct mei_device *dev; | |
410 | int ret; | |
411 | ||
412 | dev_dbg(&pdev->dev, "rpm: me: runtime resume\n"); | |
413 | ||
414 | dev = pci_get_drvdata(pdev); | |
415 | if (!dev) | |
416 | return -ENODEV; | |
417 | ||
418 | mutex_lock(&dev->device_lock); | |
419 | ||
2d1995fc | 420 | ret = mei_me_pg_exit_sync(dev); |
180ea05b TW |
421 | |
422 | mutex_unlock(&dev->device_lock); | |
423 | ||
424 | dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret); | |
425 | ||
426 | return ret; | |
427 | } | |
e13fa90c TW |
428 | |
429 | /** | |
7efceb55 | 430 | * mei_me_set_pm_domain - fill and set pm domain structure for device |
e13fa90c TW |
431 | * |
432 | * @dev: mei_device | |
433 | */ | |
434 | static inline void mei_me_set_pm_domain(struct mei_device *dev) | |
435 | { | |
d08b8fc0 | 436 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
e13fa90c TW |
437 | |
438 | if (pdev->dev.bus && pdev->dev.bus->pm) { | |
439 | dev->pg_domain.ops = *pdev->dev.bus->pm; | |
440 | ||
441 | dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; | |
442 | dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; | |
443 | dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; | |
444 | ||
989561de | 445 | dev_pm_domain_set(&pdev->dev, &dev->pg_domain); |
e13fa90c TW |
446 | } |
447 | } | |
448 | ||
449 | /** | |
7efceb55 | 450 | * mei_me_unset_pm_domain - clean pm domain structure for device |
e13fa90c TW |
451 | * |
452 | * @dev: mei_device | |
453 | */ | |
454 | static inline void mei_me_unset_pm_domain(struct mei_device *dev) | |
455 | { | |
456 | /* stop using pm callbacks if any */ | |
989561de | 457 | dev_pm_domain_set(dev->dev, NULL); |
e13fa90c | 458 | } |
180ea05b | 459 | |
180ea05b TW |
460 | static const struct dev_pm_ops mei_me_pm_ops = { |
461 | SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, | |
462 | mei_me_pci_resume) | |
463 | SET_RUNTIME_PM_OPS( | |
464 | mei_me_pm_runtime_suspend, | |
465 | mei_me_pm_runtime_resume, | |
466 | mei_me_pm_runtime_idle) | |
467 | }; | |
16833257 | 468 | |
b68301e9 | 469 | #define MEI_ME_PM_OPS (&mei_me_pm_ops) |
2703d4b2 | 470 | #else |
b68301e9 | 471 | #define MEI_ME_PM_OPS NULL |
180ea05b | 472 | #endif /* CONFIG_PM */ |
2703d4b2 TW |
473 | /* |
474 | * PCI driver structure | |
475 | */ | |
b68301e9 | 476 | static struct pci_driver mei_me_driver = { |
2703d4b2 | 477 | .name = KBUILD_MODNAME, |
b68301e9 TW |
478 | .id_table = mei_me_pci_tbl, |
479 | .probe = mei_me_probe, | |
480 | .remove = mei_me_remove, | |
481 | .shutdown = mei_me_remove, | |
482 | .driver.pm = MEI_ME_PM_OPS, | |
2703d4b2 TW |
483 | }; |
484 | ||
b68301e9 | 485 | module_pci_driver(mei_me_driver); |
2703d4b2 TW |
486 | |
487 | MODULE_AUTHOR("Intel Corporation"); | |
488 | MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); | |
489 | MODULE_LICENSE("GPL v2"); |