[mirror_ubuntu-artful-kernel.git] / drivers / misc / mei / pci-me.c

/*
 *
 * Intel Management Engine Interface (Intel MEI) Linux driver
 * Copyright (c) 2003-2012, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/aio.h>
#include <linux/pci.h>
#include <linux/poll.h>
#include <linux/ioctl.h>
#include <linux/cdev.h>
#include <linux/sched.h>
#include <linux/uuid.h>
#include <linux/compat.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>
#include <linux/miscdevice.h>

#include <linux/mei.h>

#include "mei_dev.h"
#include "client.h"
#include "hw-me-regs.h"
#include "hw-me.h"

/* mei_pci_tbl - PCI Device ID Table */
static DEFINE_PCI_DEVICE_TABLE(mei_me_pci_tbl) = {
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82946GZ)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G35)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82Q965)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G965)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GM965)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GME965)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q35)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82G33)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q33)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82X38)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_3200)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_6)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_7)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_8)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_9)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_10)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_1)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_3)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_4)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_1)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_3)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_4)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_1)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_CPT_1)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PBG_1)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_1)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_3)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_H)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_W)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_LP)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_HR)},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_WPT_LP)},

	/* required last entry */
	{0, }
};

MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);

/**
 * mei_quirk_probe - probe for devices that doesn't valid ME interface
 *
 * @pdev: PCI device structure
 * @ent: entry into pci_device_table
 *
 * returns true if ME Interface is valid, false otherwise
 */
static bool mei_me_quirk_probe(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{
	u32 reg;
	if (ent->device == MEI_DEV_ID_PBG_1) {
		pci_read_config_dword(pdev, 0x48, &reg);
		/* make sure that bit 9 is up and bit 10 is down */
		if ((reg & 0x600) == 0x200) {
			dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
			return false;
		}
	}
	return true;
}
/**
 * mei_probe - Device Initialization Routine
 *
 * @pdev: PCI device structure
 * @ent: entry in kcs_pci_tbl
 *
 * returns 0 on success, <0 on failure.
 */
static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct mei_device *dev;
	struct mei_me_hw *hw;
	int err;


	if (!mei_me_quirk_probe(pdev, ent)) {
		err = -ENODEV;
		goto end;
	}

	/* enable pci dev */
	err = pci_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "failed to enable pci device.\n");
		goto end;
	}
	/* set PCI host mastering  */
	pci_set_master(pdev);
	/* pci request regions for mei driver */
	err = pci_request_regions(pdev, KBUILD_MODNAME);
	if (err) {
		dev_err(&pdev->dev, "failed to get pci regions.\n");
		goto disable_device;
	}

	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
	    dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {

		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
		if (err)
			err = dma_set_coherent_mask(&pdev->dev,
						    DMA_BIT_MASK(32));
	}
	if (err) {
		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
		goto release_regions;
	}


	/* allocates and initializes the mei dev structure */
	dev = mei_me_dev_init(pdev);
	if (!dev) {
		err = -ENOMEM;
		goto release_regions;
	}
	hw = to_me_hw(dev);
	/* mapping  IO device memory */
	hw->mem_addr = pci_iomap(pdev, 0, 0);
	if (!hw->mem_addr) {
		dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
		err = -ENOMEM;
		goto free_device;
	}
	pci_enable_msi(pdev);

	 /* request and enable interrupt */
	if (pci_dev_msi_enabled(pdev))
		err = request_threaded_irq(pdev->irq,
			NULL,
			mei_me_irq_thread_handler,
			IRQF_ONESHOT, KBUILD_MODNAME, dev);
	else
		err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			IRQF_SHARED, KBUILD_MODNAME, dev);

	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
		       pdev->irq);
		goto disable_msi;
	}

	if (mei_start(dev)) {
		dev_err(&pdev->dev, "init hw failure.\n");
		err = -ENODEV;
		goto release_irq;
	}

	err = mei_register(dev);
	if (err)
		goto release_irq;

	pci_set_drvdata(pdev, dev);

	schedule_delayed_work(&dev->timer_work, HZ);

	dev_dbg(&pdev->dev, "initialization successful.\n");

	return 0;

release_irq:
	mei_cancel_work(dev);
	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
disable_msi:
	pci_disable_msi(pdev);
	pci_iounmap(pdev, hw->mem_addr);
free_device:
	kfree(dev);
release_regions:
	pci_release_regions(pdev);
disable_device:
	pci_disable_device(pdev);
end:
	dev_err(&pdev->dev, "initialization failed.\n");
	return err;
}

/**
 * mei_remove - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_remove is called by the PCI subsystem to alert the driver
 * that it should release a PCI device.
 */
static void mei_me_remove(struct pci_dev *pdev)
{
	struct mei_device *dev;
	struct mei_me_hw *hw;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return;

	hw = to_me_hw(dev);


	dev_dbg(&pdev->dev, "stop\n");
	mei_stop(dev);

	/* disable interrupts */
	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	if (hw->mem_addr)
		pci_iounmap(pdev, hw->mem_addr);

	mei_deregister(dev);

	kfree(dev);

	pci_release_regions(pdev);
	pci_disable_device(pdev);


}
#ifdef CONFIG_PM_SLEEP
static int mei_me_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev = pci_get_drvdata(pdev);

	if (!dev)
		return -ENODEV;

	dev_dbg(&pdev->dev, "suspend\n");

	mei_stop(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	return 0;
}

static int mei_me_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int err;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	pci_enable_msi(pdev);

	/* request and enable interrupt */
	if (pci_dev_msi_enabled(pdev))
		err = request_threaded_irq(pdev->irq,
			NULL,
			mei_me_irq_thread_handler,
			IRQF_ONESHOT, KBUILD_MODNAME, dev);
	else
		err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			IRQF_SHARED, KBUILD_MODNAME, dev);

	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
				pdev->irq);
		return err;
	}

	err = mei_restart(dev);
	if (err)
		return err;

	/* Start timer if stopped in suspend */
	schedule_delayed_work(&dev->timer_work, HZ);

	return 0;
}

static SIMPLE_DEV_PM_OPS(mei_me_pm_ops, mei_me_pci_suspend, mei_me_pci_resume);
#define MEI_ME_PM_OPS	(&mei_me_pm_ops)
#else
#define MEI_ME_PM_OPS	NULL
#endif /* CONFIG_PM_SLEEP */
/*
 *  PCI driver structure
 */
static struct pci_driver mei_me_driver = {
	.name = KBUILD_MODNAME,
	.id_table = mei_me_pci_tbl,
	.probe = mei_me_probe,
	.remove = mei_me_remove,
	.shutdown = mei_me_remove,
	.driver.pm = MEI_ME_PM_OPS,
};

module_pci_driver(mei_me_driver);

MODULE_AUTHOR("Intel Corporation");
MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2703d4b2 TW	1	/*
	2	*
	3	* Intel Management Engine Interface (Intel MEI) Linux driver
	4	* Copyright (c) 2003-2012, Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	*/
2703d4b2 TW	16	#include <linux/module.h>
	17	#include <linux/moduleparam.h>
	18	#include <linux/kernel.h>
	19	#include <linux/device.h>
	20	#include <linux/fs.h>
	21	#include <linux/errno.h>
	22	#include <linux/types.h>
	23	#include <linux/fcntl.h>
	24	#include <linux/aio.h>
	25	#include <linux/pci.h>
	26	#include <linux/poll.h>
2703d4b2 TW	27	#include <linux/ioctl.h>
	28	#include <linux/cdev.h>
	29	#include <linux/sched.h>
	30	#include <linux/uuid.h>
	31	#include <linux/compat.h>
	32	#include <linux/jiffies.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/miscdevice.h>
	35
	36	#include <linux/mei.h>
	37
	38	#include "mei_dev.h"
2703d4b2	39	#include "client.h"
6e4cd27a TW	40	#include "hw-me-regs.h"
6e4cd27a TW	41	#include "hw-me.h"
2703d4b2	42
2703d4b2	43	/* mei_pci_tbl - PCI Device ID Table */
b68301e9	44	static DEFINE_PCI_DEVICE_TABLE(mei_me_pci_tbl) = {
2703d4b2 TW	45	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82946GZ)},
	46	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G35)},
	47	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82Q965)},
	48	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G965)},
	49	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GM965)},
	50	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GME965)},
	51	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q35)},
	52	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82G33)},
	53	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q33)},
	54	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82X38)},
	55	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_3200)},
	56	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_6)},
	57	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_7)},
	58	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_8)},
	59	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_9)},
	60	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_10)},
	61	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_1)},
	62	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_2)},
	63	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_3)},
	64	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_4)},
	65	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_1)},
	66	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_2)},
	67	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_3)},
	68	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_4)},
	69	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_1)},
	70	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_2)},
	71	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_CPT_1)},
	72	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PBG_1)},
	73	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_1)},
	74	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_2)},
	75	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_3)},
76a96359	76	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_H)},
838b3a6d	77	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_W)},
2703d4b2	78	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_LP)},
76a96359 TW	79	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_HR)},
76a96359 TW	80	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_WPT_LP)},
2703d4b2 TW	81
	82	/* required last entry */
	83	{0, }
	84	};
	85
b68301e9	86	MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
2703d4b2	87
2703d4b2 TW	88	/**
2703d4b2 TW	89	* mei_quirk_probe - probe for devices that doesn't valid ME interface
393b148f	90	*
2703d4b2 TW	91	* @pdev: PCI device structure
	92	* @ent: entry into pci_device_table
	93	*
	94	* returns true if ME Interface is valid, false otherwise
	95	*/
b68301e9	96	static bool mei_me_quirk_probe(struct pci_dev *pdev,
2703d4b2 TW	97	const struct pci_device_id *ent)
	98	{
	99	u32 reg;
	100	if (ent->device == MEI_DEV_ID_PBG_1) {
	101	pci_read_config_dword(pdev, 0x48, &reg);
	102	/* make sure that bit 9 is up and bit 10 is down */
	103	if ((reg & 0x600) == 0x200) {
	104	dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
	105	return false;
	106	}
	107	}
	108	return true;
	109	}
	110	/**
	111	* mei_probe - Device Initialization Routine
	112	*
	113	* @pdev: PCI device structure
	114	* @ent: entry in kcs_pci_tbl
	115	*
	116	* returns 0 on success, <0 on failure.
	117	*/
b68301e9	118	static int mei_me_probe(struct pci_dev pdev, const struct pci_device_id ent)
2703d4b2 TW	119	{
2703d4b2 TW	120	struct mei_device *dev;
52c34561	121	struct mei_me_hw *hw;
2703d4b2 TW	122	int err;
2703d4b2 TW	123
2703d4b2	124
b68301e9	125	if (!mei_me_quirk_probe(pdev, ent)) {
2703d4b2 TW	126	err = -ENODEV;
	127	goto end;
	128	}
	129
2703d4b2 TW	130	/* enable pci dev */
	131	err = pci_enable_device(pdev);
	132	if (err) {
	133	dev_err(&pdev->dev, "failed to enable pci device.\n");
	134	goto end;
	135	}
	136	/* set PCI host mastering */
	137	pci_set_master(pdev);
	138	/* pci request regions for mei driver */
	139	err = pci_request_regions(pdev, KBUILD_MODNAME);
	140	if (err) {
	141	dev_err(&pdev->dev, "failed to get pci regions.\n");
	142	goto disable_device;
	143	}
3ecfb168 TW	144
	145	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) \|\|
	146	dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
	147
	148	err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
	149	if (err)
	150	err = dma_set_coherent_mask(&pdev->dev,
	151	DMA_BIT_MASK(32));
	152	}
	153	if (err) {
	154	dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
	155	goto release_regions;
	156	}
	157
	158
2703d4b2	159	/* allocates and initializes the mei dev structure */
52c34561	160	dev = mei_me_dev_init(pdev);
2703d4b2 TW	161	if (!dev) {
	162	err = -ENOMEM;
	163	goto release_regions;
	164	}
52c34561	165	hw = to_me_hw(dev);
2703d4b2	166	/* mapping IO device memory */
52c34561 TW	167	hw->mem_addr = pci_iomap(pdev, 0, 0);
52c34561 TW	168	if (!hw->mem_addr) {
2703d4b2 TW	169	dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
	170	err = -ENOMEM;
	171	goto free_device;
	172	}
	173	pci_enable_msi(pdev);
	174
	175	/* request and enable interrupt */
	176	if (pci_dev_msi_enabled(pdev))
	177	err = request_threaded_irq(pdev->irq,
	178	NULL,
06ecd645	179	mei_me_irq_thread_handler,
2703d4b2 TW	180	IRQF_ONESHOT, KBUILD_MODNAME, dev);
	181	else
	182	err = request_threaded_irq(pdev->irq,
06ecd645 TW	183	mei_me_irq_quick_handler,
06ecd645 TW	184	mei_me_irq_thread_handler,
2703d4b2 TW	185	IRQF_SHARED, KBUILD_MODNAME, dev);
	186
	187	if (err) {
	188	dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
	189	pdev->irq);
	190	goto disable_msi;
	191	}
	192
c4d589be	193	if (mei_start(dev)) {
2703d4b2 TW	194	dev_err(&pdev->dev, "init hw failure.\n");
	195	err = -ENODEV;
	196	goto release_irq;
	197	}
	198
30e53bb8	199	err = mei_register(dev);
2703d4b2 TW	200	if (err)
	201	goto release_irq;
	202
2703d4b2 TW	203	pci_set_drvdata(pdev, dev);
2703d4b2 TW	204
2703d4b2 TW	205	schedule_delayed_work(&dev->timer_work, HZ);
2703d4b2 TW	206
c4e87b52	207	dev_dbg(&pdev->dev, "initialization successful.\n");
2703d4b2 TW	208
	209	return 0;
	210
	211	release_irq:
dc844b0d	212	mei_cancel_work(dev);
2703d4b2	213	mei_disable_interrupts(dev);
2703d4b2 TW	214	free_irq(pdev->irq, dev);
	215	disable_msi:
	216	pci_disable_msi(pdev);
52c34561	217	pci_iounmap(pdev, hw->mem_addr);
2703d4b2 TW	218	free_device:
	219	kfree(dev);
	220	release_regions:
	221	pci_release_regions(pdev);
	222	disable_device:
	223	pci_disable_device(pdev);
	224	end:
2703d4b2 TW	225	dev_err(&pdev->dev, "initialization failed.\n");
	226	return err;
	227	}
	228
	229	/**
	230	* mei_remove - Device Removal Routine
	231	*
	232	* @pdev: PCI device structure
	233	*
	234	* mei_remove is called by the PCI subsystem to alert the driver
	235	* that it should release a PCI device.
	236	*/
b68301e9	237	static void mei_me_remove(struct pci_dev *pdev)
2703d4b2 TW	238	{
2703d4b2 TW	239	struct mei_device *dev;
52c34561	240	struct mei_me_hw *hw;
2703d4b2	241
2703d4b2 TW	242	dev = pci_get_drvdata(pdev);
	243	if (!dev)
	244	return;
	245
52c34561 TW	246	hw = to_me_hw(dev);
52c34561 TW	247
2703d4b2	248
ed6f7ac1	249	dev_dbg(&pdev->dev, "stop\n");
7cb035d9	250	mei_stop(dev);
2703d4b2	251
2703d4b2 TW	252	/* disable interrupts */
	253	mei_disable_interrupts(dev);
	254
	255	free_irq(pdev->irq, dev);
	256	pci_disable_msi(pdev);
2703d4b2	257
52c34561 TW	258	if (hw->mem_addr)
52c34561 TW	259	pci_iounmap(pdev, hw->mem_addr);
2703d4b2	260
30e53bb8 TW	261	mei_deregister(dev);
30e53bb8 TW	262
2703d4b2 TW	263	kfree(dev);
	264
	265	pci_release_regions(pdev);
	266	pci_disable_device(pdev);
	267
2703d4b2 TW	268
2703d4b2 TW	269	}
16833257	270	#ifdef CONFIG_PM_SLEEP
b68301e9	271	static int mei_me_pci_suspend(struct device *device)
2703d4b2 TW	272	{
	273	struct pci_dev *pdev = to_pci_dev(device);
	274	struct mei_device *dev = pci_get_drvdata(pdev);
2703d4b2 TW	275
	276	if (!dev)
	277	return -ENODEV;
2703d4b2	278
ed6f7ac1	279	dev_dbg(&pdev->dev, "suspend\n");
2703d4b2	280
7cb035d9 TW	281	mei_stop(dev);
	282
	283	mei_disable_interrupts(dev);
2703d4b2 TW	284
	285	free_irq(pdev->irq, dev);
	286	pci_disable_msi(pdev);
	287
7cb035d9	288	return 0;
2703d4b2 TW	289	}
2703d4b2 TW	290
b68301e9	291	static int mei_me_pci_resume(struct device *device)
2703d4b2 TW	292	{
	293	struct pci_dev *pdev = to_pci_dev(device);
	294	struct mei_device *dev;
	295	int err;
	296
	297	dev = pci_get_drvdata(pdev);
	298	if (!dev)
	299	return -ENODEV;
	300
	301	pci_enable_msi(pdev);
	302
	303	/* request and enable interrupt */
	304	if (pci_dev_msi_enabled(pdev))
	305	err = request_threaded_irq(pdev->irq,
	306	NULL,
06ecd645	307	mei_me_irq_thread_handler,
2703d4b2 TW	308	IRQF_ONESHOT, KBUILD_MODNAME, dev);
	309	else
	310	err = request_threaded_irq(pdev->irq,
06ecd645 TW	311	mei_me_irq_quick_handler,
06ecd645 TW	312	mei_me_irq_thread_handler,
2703d4b2 TW	313	IRQF_SHARED, KBUILD_MODNAME, dev);
	314
	315	if (err) {
	316	dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
	317	pdev->irq);
	318	return err;
	319	}
	320
33ec0826 TW	321	err = mei_restart(dev);
	322	if (err)
	323	return err;
2703d4b2 TW	324
	325	/* Start timer if stopped in suspend */
	326	schedule_delayed_work(&dev->timer_work, HZ);
	327
33ec0826	328	return 0;
2703d4b2	329	}
16833257	330
b68301e9 TW	331	static SIMPLE_DEV_PM_OPS(mei_me_pm_ops, mei_me_pci_suspend, mei_me_pci_resume);
b68301e9 TW	332	#define MEI_ME_PM_OPS (&mei_me_pm_ops)
2703d4b2	333	#else
b68301e9	334	#define MEI_ME_PM_OPS NULL
16833257	335	#endif /* CONFIG_PM_SLEEP */
2703d4b2 TW	336	/*
	337	* PCI driver structure
	338	*/
b68301e9	339	static struct pci_driver mei_me_driver = {
2703d4b2	340	.name = KBUILD_MODNAME,
b68301e9 TW	341	.id_table = mei_me_pci_tbl,
	342	.probe = mei_me_probe,
	343	.remove = mei_me_remove,
	344	.shutdown = mei_me_remove,
	345	.driver.pm = MEI_ME_PM_OPS,
2703d4b2 TW	346	};
2703d4b2 TW	347
b68301e9	348	module_pci_driver(mei_me_driver);
2703d4b2 TW	349
	350	MODULE_AUTHOR("Intel Corporation");
	351	MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
	352	MODULE_LICENSE("GPL v2");