[mirror_ubuntu-artful-kernel.git] / drivers / misc / mei / pci-me.c

/*
 *
 * Intel Management Engine Interface (Intel MEI) Linux driver
 * Copyright (c) 2003-2012, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/pci.h>
#include <linux/poll.h>
#include <linux/ioctl.h>
#include <linux/cdev.h>
#include <linux/sched.h>
#include <linux/uuid.h>
#include <linux/compat.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>

#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

#include <linux/mei.h>

#include "mei_dev.h"
#include "client.h"
#include "hw-me-regs.h"
#include "hw-me.h"

/* mei_pci_tbl - PCI Device ID Table */
static const struct pci_device_id mei_me_pci_tbl[] = {
	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, mei_me_legacy_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, mei_me_ich_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, mei_me_ich_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, mei_me_ich_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, mei_me_ich_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, mei_me_pch8_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, mei_me_pch8_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, mei_me_pch8_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, mei_me_pch8_cfg)},

	/* required last entry */
	{0, }
};

MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);

#ifdef CONFIG_PM
static inline void mei_me_set_pm_domain(struct mei_device *dev);
static inline void mei_me_unset_pm_domain(struct mei_device *dev);
#else
static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
#endif /* CONFIG_PM */

/**
 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 *
 * @pdev: PCI device structure
 * @cfg: per generation config
 *
 * Return: true if ME Interface is valid, false otherwise
 */
static bool mei_me_quirk_probe(struct pci_dev *pdev,
				const struct mei_cfg *cfg)
{
	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
		dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
		return false;
	}

	return true;
}

/**
 * mei_me_probe - Device Initialization Routine
 *
 * @pdev: PCI device structure
 * @ent: entry in kcs_pci_tbl
 *
 * Return: 0 on success, <0 on failure.
 */
static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct mei_cfg *cfg = (struct mei_cfg *)(ent->driver_data);
	struct mei_device *dev;
	struct mei_me_hw *hw;
	unsigned int irqflags;
	int err;


	if (!mei_me_quirk_probe(pdev, cfg))
		return -ENODEV;

	/* enable pci dev */
	err = pcim_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "failed to enable pci device.\n");
		goto end;
	}
	/* set PCI host mastering  */
	pci_set_master(pdev);
	/* pci request regions and mapping IO device memory for mei driver */
	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
	if (err) {
		dev_err(&pdev->dev, "failed to get pci regions.\n");
		goto end;
	}

	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
	    dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {

		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
		if (err)
			err = dma_set_coherent_mask(&pdev->dev,
						    DMA_BIT_MASK(32));
	}
	if (err) {
		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
		goto end;
	}

	/* allocates and initializes the mei dev structure */
	dev = mei_me_dev_init(pdev, cfg);
	if (!dev) {
		err = -ENOMEM;
		goto end;
	}
	hw = to_me_hw(dev);
	hw->mem_addr = pcim_iomap_table(pdev)[0];

	pci_enable_msi(pdev);

	 /* request and enable interrupt */
	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);
	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
		       pdev->irq);
		goto end;
	}

	if (mei_start(dev)) {
		dev_err(&pdev->dev, "init hw failure.\n");
		err = -ENODEV;
		goto release_irq;
	}

	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);

	err = mei_register(dev, &pdev->dev);
	if (err)
		goto stop;

	pci_set_drvdata(pdev, dev);

	/*
	 * MEI requires to resume from runtime suspend mode
	 * in order to perform link reset flow upon system suspend.
	 */
	pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;

	/*
	* For not wake-able HW runtime pm framework
	* can't be used on pci device level.
	* Use domain runtime pm callbacks instead.
	*/
	if (!pci_dev_run_wake(pdev))
		mei_me_set_pm_domain(dev);

	if (mei_pg_is_enabled(dev))
		pm_runtime_put_noidle(&pdev->dev);

	dev_dbg(&pdev->dev, "initialization successful.\n");

	return 0;

stop:
	mei_stop(dev);
release_irq:
	mei_cancel_work(dev);
	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
end:
	dev_err(&pdev->dev, "initialization failed.\n");
	return err;
}

/**
 * mei_me_shutdown - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_me_shutdown is called from the reboot notifier
 * it's a simplified version of remove so we go down
 * faster.
 */
static void mei_me_shutdown(struct pci_dev *pdev)
{
	struct mei_device *dev;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return;

	dev_dbg(&pdev->dev, "shutdown\n");
	mei_stop(dev);

	if (!pci_dev_run_wake(pdev))
		mei_me_unset_pm_domain(dev);

	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
}

/**
 * mei_me_remove - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_me_remove is called by the PCI subsystem to alert the driver
 * that it should release a PCI device.
 */
static void mei_me_remove(struct pci_dev *pdev)
{
	struct mei_device *dev;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return;

	if (mei_pg_is_enabled(dev))
		pm_runtime_get_noresume(&pdev->dev);

	dev_dbg(&pdev->dev, "stop\n");
	mei_stop(dev);

	if (!pci_dev_run_wake(pdev))
		mei_me_unset_pm_domain(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);

	mei_deregister(dev);
}

#ifdef CONFIG_PM_SLEEP
static int mei_me_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev = pci_get_drvdata(pdev);

	if (!dev)
		return -ENODEV;

	dev_dbg(&pdev->dev, "suspend\n");

	mei_stop(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	return 0;
}

static int mei_me_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	unsigned int irqflags;
	int err;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	pci_enable_msi(pdev);

	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	/* request and enable interrupt */
	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);

	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
				pdev->irq);
		return err;
	}

	err = mei_restart(dev);
	if (err)
		return err;

	/* Start timer if stopped in suspend */
	schedule_delayed_work(&dev->timer_work, HZ);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

#ifdef CONFIG_PM
static int mei_me_pm_runtime_idle(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;

	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;
	if (mei_write_is_idle(dev))
		pm_runtime_autosuspend(device);

	return -EBUSY;
}

static int mei_me_pm_runtime_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int ret;

	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	if (mei_write_is_idle(dev))
		ret = mei_me_pg_enter_sync(dev);
	else
		ret = -EAGAIN;

	mutex_unlock(&dev->device_lock);

	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);

	if (ret && ret != -EAGAIN)
		schedule_work(&dev->reset_work);

	return ret;
}

static int mei_me_pm_runtime_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int ret;

	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	ret = mei_me_pg_exit_sync(dev);

	mutex_unlock(&dev->device_lock);

	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);

	if (ret)
		schedule_work(&dev->reset_work);

	return ret;
}

/**
 * mei_me_set_pm_domain - fill and set pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_set_pm_domain(struct mei_device *dev)
{
	struct pci_dev *pdev  = to_pci_dev(dev->dev);

	if (pdev->dev.bus && pdev->dev.bus->pm) {
		dev->pg_domain.ops = *pdev->dev.bus->pm;

		dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
		dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
		dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;

		dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
	}
}

/**
 * mei_me_unset_pm_domain - clean pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_unset_pm_domain(struct mei_device *dev)
{
	/* stop using pm callbacks if any */
	dev_pm_domain_set(dev->dev, NULL);
}

static const struct dev_pm_ops mei_me_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
				mei_me_pci_resume)
	SET_RUNTIME_PM_OPS(
		mei_me_pm_runtime_suspend,
		mei_me_pm_runtime_resume,
		mei_me_pm_runtime_idle)
};

#define MEI_ME_PM_OPS	(&mei_me_pm_ops)
#else
#define MEI_ME_PM_OPS	NULL
#endif /* CONFIG_PM */
/*
 *  PCI driver structure
 */
static struct pci_driver mei_me_driver = {
	.name = KBUILD_MODNAME,
	.id_table = mei_me_pci_tbl,
	.probe = mei_me_probe,
	.remove = mei_me_remove,
	.shutdown = mei_me_shutdown,
	.driver.pm = MEI_ME_PM_OPS,
};

module_pci_driver(mei_me_driver);

MODULE_AUTHOR("Intel Corporation");
MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2703d4b2 TW	1	/*
	2	*
	3	* Intel Management Engine Interface (Intel MEI) Linux driver
	4	* Copyright (c) 2003-2012, Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	*/
2703d4b2 TW	16	#include <linux/module.h>
	17	#include <linux/moduleparam.h>
	18	#include <linux/kernel.h>
	19	#include <linux/device.h>
	20	#include <linux/fs.h>
	21	#include <linux/errno.h>
	22	#include <linux/types.h>
	23	#include <linux/fcntl.h>
2703d4b2 TW	24	#include <linux/pci.h>
2703d4b2 TW	25	#include <linux/poll.h>
2703d4b2 TW	26	#include <linux/ioctl.h>
	27	#include <linux/cdev.h>
	28	#include <linux/sched.h>
	29	#include <linux/uuid.h>
	30	#include <linux/compat.h>
	31	#include <linux/jiffies.h>
	32	#include <linux/interrupt.h>
2703d4b2	33
989561de	34	#include <linux/pm_domain.h>
180ea05b TW	35	#include <linux/pm_runtime.h>
180ea05b TW	36
2703d4b2 TW	37	#include <linux/mei.h>
	38
	39	#include "mei_dev.h"
2703d4b2	40	#include "client.h"
6e4cd27a TW	41	#include "hw-me-regs.h"
6e4cd27a TW	42	#include "hw-me.h"
2703d4b2	43
2703d4b2	44	/* mei_pci_tbl - PCI Device ID Table */
a05f8f86	45	static const struct pci_device_id mei_me_pci_tbl[] = {
8d929d48 AU	46	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, mei_me_legacy_cfg)},
	47	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, mei_me_legacy_cfg)},
	48	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, mei_me_legacy_cfg)},
	49	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, mei_me_legacy_cfg)},
	50	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, mei_me_legacy_cfg)},
	51	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, mei_me_legacy_cfg)},
	52	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, mei_me_legacy_cfg)},
	53	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, mei_me_legacy_cfg)},
	54	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, mei_me_legacy_cfg)},
	55	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, mei_me_legacy_cfg)},
	56	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, mei_me_legacy_cfg)},
	57
	58	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, mei_me_legacy_cfg)},
	59	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, mei_me_legacy_cfg)},
	60	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, mei_me_legacy_cfg)},
	61	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, mei_me_legacy_cfg)},
	62	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, mei_me_legacy_cfg)},
	63	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, mei_me_legacy_cfg)},
	64	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, mei_me_legacy_cfg)},
	65	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, mei_me_legacy_cfg)},
	66	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, mei_me_legacy_cfg)},
	67	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, mei_me_ich_cfg)},
	68	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, mei_me_ich_cfg)},
	69	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, mei_me_ich_cfg)},
	70	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, mei_me_ich_cfg)},
	71
	72	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)},
	73	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)},
c919951d TW	74	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)},
c919951d TW	75	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)},
8d929d48 AU	76	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)},
	77	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)},
	78	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)},
edca5ea3 AU	79	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_pch8_sps_cfg)},
	80	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_pch8_sps_cfg)},
	81	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch8_cfg)},
	82	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_pch8_sps_cfg)},
	83	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch8_cfg)},
	84	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, mei_me_pch8_cfg)},
2703d4b2	85
1625c7ec TW	86	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, mei_me_pch8_cfg)},
1625c7ec TW	87	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, mei_me_pch8_cfg)},
8c57cac1 TW	88	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, mei_me_pch8_sps_cfg)},
8c57cac1 TW	89	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, mei_me_pch8_sps_cfg)},
9ff2007b	90	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, mei_me_pch8_cfg)},
1625c7ec	91
dd16f6cd TW	92	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, mei_me_pch8_cfg)},
	93	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, mei_me_pch8_cfg)},
	94
ac182e8a AU	95	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, mei_me_pch8_cfg)},
	96	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, mei_me_pch8_cfg)},
	97
2703d4b2 TW	98	/* required last entry */
	99	{0, }
	100	};
	101
b68301e9	102	MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
2703d4b2	103
bbd6d050	104	#ifdef CONFIG_PM
e13fa90c TW	105	static inline void mei_me_set_pm_domain(struct mei_device *dev);
	106	static inline void mei_me_unset_pm_domain(struct mei_device *dev);
	107	#else
	108	static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
	109	static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
bbd6d050	110	#endif /* CONFIG_PM */
e13fa90c	111
2703d4b2	112	/**
ce23139c	113	* mei_me_quirk_probe - probe for devices that doesn't valid ME interface
393b148f	114	*
2703d4b2	115	* @pdev: PCI device structure
c919951d	116	* @cfg: per generation config
2703d4b2	117	*
a8605ea2	118	* Return: true if ME Interface is valid, false otherwise
2703d4b2	119	*/
b68301e9	120	static bool mei_me_quirk_probe(struct pci_dev *pdev,
c919951d	121	const struct mei_cfg *cfg)
2703d4b2	122	{
c919951d TW	123	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
	124	dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
	125	return false;
5e6533a6 TW	126	}
5e6533a6 TW	127
2703d4b2 TW	128	return true;
2703d4b2 TW	129	}
c919951d	130
2703d4b2	131	/**
ce23139c	132	* mei_me_probe - Device Initialization Routine
2703d4b2 TW	133	*
	134	* @pdev: PCI device structure
	135	* @ent: entry in kcs_pci_tbl
	136	*
a8605ea2	137	* Return: 0 on success, <0 on failure.
2703d4b2	138	*/
b68301e9	139	static int mei_me_probe(struct pci_dev pdev, const struct pci_device_id ent)
2703d4b2	140	{
8d929d48	141	const struct mei_cfg cfg = (struct mei_cfg )(ent->driver_data);
2703d4b2	142	struct mei_device *dev;
52c34561	143	struct mei_me_hw *hw;
1fa55b4e	144	unsigned int irqflags;
2703d4b2 TW	145	int err;
2703d4b2 TW	146
2703d4b2	147
c919951d TW	148	if (!mei_me_quirk_probe(pdev, cfg))
c919951d TW	149	return -ENODEV;
2703d4b2	150
2703d4b2	151	/* enable pci dev */
f8a09605	152	err = pcim_enable_device(pdev);
2703d4b2 TW	153	if (err) {
	154	dev_err(&pdev->dev, "failed to enable pci device.\n");
	155	goto end;
	156	}
	157	/* set PCI host mastering */
	158	pci_set_master(pdev);
f8a09605 TW	159	/* pci request regions and mapping IO device memory for mei driver */
f8a09605 TW	160	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
2703d4b2 TW	161	if (err) {
2703d4b2 TW	162	dev_err(&pdev->dev, "failed to get pci regions.\n");
f8a09605	163	goto end;
2703d4b2	164	}
3ecfb168 TW	165
	166	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) \|\|
	167	dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
	168
	169	err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
	170	if (err)
	171	err = dma_set_coherent_mask(&pdev->dev,
	172	DMA_BIT_MASK(32));
	173	}
	174	if (err) {
	175	dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
f8a09605	176	goto end;
3ecfb168 TW	177	}
3ecfb168 TW	178
2703d4b2	179	/* allocates and initializes the mei dev structure */
8d929d48	180	dev = mei_me_dev_init(pdev, cfg);
2703d4b2 TW	181	if (!dev) {
2703d4b2 TW	182	err = -ENOMEM;
f8a09605	183	goto end;
2703d4b2	184	}
52c34561	185	hw = to_me_hw(dev);
f8a09605 TW	186	hw->mem_addr = pcim_iomap_table(pdev)[0];
f8a09605 TW	187
2703d4b2 TW	188	pci_enable_msi(pdev);
	189
	190	/* request and enable interrupt */
1fa55b4e AU	191	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
	192
	193	err = request_threaded_irq(pdev->irq,
06ecd645 TW	194	mei_me_irq_quick_handler,
06ecd645 TW	195	mei_me_irq_thread_handler,
1fa55b4e	196	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	197	if (err) {
	198	dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
	199	pdev->irq);
f8a09605	200	goto end;
2703d4b2 TW	201	}
2703d4b2 TW	202
c4d589be	203	if (mei_start(dev)) {
2703d4b2 TW	204	dev_err(&pdev->dev, "init hw failure.\n");
	205	err = -ENODEV;
	206	goto release_irq;
	207	}
	208
180ea05b TW	209	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	210	pm_runtime_use_autosuspend(&pdev->dev);
	211
f3d8e878	212	err = mei_register(dev, &pdev->dev);
2703d4b2	213	if (err)
1f7e489a	214	goto stop;
2703d4b2	215
2703d4b2 TW	216	pci_set_drvdata(pdev, dev);
2703d4b2 TW	217
557909e1 AU	218	/*
	219	* MEI requires to resume from runtime suspend mode
	220	* in order to perform link reset flow upon system suspend.
	221	*/
	222	pdev->dev_flags \|= PCI_DEV_FLAGS_NEEDS_RESUME;
	223
e13fa90c TW	224	/*
	225	* For not wake-able HW runtime pm framework
	226	* can't be used on pci device level.
	227	* Use domain runtime pm callbacks instead.
	228	*/
	229	if (!pci_dev_run_wake(pdev))
	230	mei_me_set_pm_domain(dev);
	231
180ea05b TW	232	if (mei_pg_is_enabled(dev))
	233	pm_runtime_put_noidle(&pdev->dev);
	234
c4e87b52	235	dev_dbg(&pdev->dev, "initialization successful.\n");
2703d4b2 TW	236
	237	return 0;
	238
1f7e489a AU	239	stop:
1f7e489a AU	240	mei_stop(dev);
2703d4b2	241	release_irq:
dc844b0d	242	mei_cancel_work(dev);
2703d4b2	243	mei_disable_interrupts(dev);
2703d4b2	244	free_irq(pdev->irq, dev);
2703d4b2	245	end:
2703d4b2 TW	246	dev_err(&pdev->dev, "initialization failed.\n");
	247	return err;
	248	}
	249
5c4c0106 TW	250	/**
	251	* mei_me_shutdown - Device Removal Routine
	252	*
	253	* @pdev: PCI device structure
	254	*
	255	* mei_me_shutdown is called from the reboot notifier
	256	* it's a simplified version of remove so we go down
	257	* faster.
	258	*/
	259	static void mei_me_shutdown(struct pci_dev *pdev)
	260	{
	261	struct mei_device *dev;
	262
	263	dev = pci_get_drvdata(pdev);
	264	if (!dev)
	265	return;
	266
	267	dev_dbg(&pdev->dev, "shutdown\n");
	268	mei_stop(dev);
	269
	270	if (!pci_dev_run_wake(pdev))
	271	mei_me_unset_pm_domain(dev);
	272
	273	mei_disable_interrupts(dev);
	274	free_irq(pdev->irq, dev);
	275	}
	276
2703d4b2	277	/**
ce23139c	278	* mei_me_remove - Device Removal Routine
2703d4b2 TW	279	*
	280	* @pdev: PCI device structure
	281	*
5c4c0106	282	* mei_me_remove is called by the PCI subsystem to alert the driver
2703d4b2 TW	283	* that it should release a PCI device.
2703d4b2 TW	284	*/
b68301e9	285	static void mei_me_remove(struct pci_dev *pdev)
2703d4b2 TW	286	{
	287	struct mei_device *dev;
	288
2703d4b2 TW	289	dev = pci_get_drvdata(pdev);
	290	if (!dev)
	291	return;
	292
180ea05b TW	293	if (mei_pg_is_enabled(dev))
	294	pm_runtime_get_noresume(&pdev->dev);
	295
ed6f7ac1	296	dev_dbg(&pdev->dev, "stop\n");
7cb035d9	297	mei_stop(dev);
2703d4b2	298
e13fa90c TW	299	if (!pci_dev_run_wake(pdev))
	300	mei_me_unset_pm_domain(dev);
	301
2703d4b2 TW	302	mei_disable_interrupts(dev);
	303
	304	free_irq(pdev->irq, dev);
2703d4b2	305
30e53bb8	306	mei_deregister(dev);
2703d4b2	307	}
f8a09605	308
16833257	309	#ifdef CONFIG_PM_SLEEP
b68301e9	310	static int mei_me_pci_suspend(struct device *device)
2703d4b2 TW	311	{
	312	struct pci_dev *pdev = to_pci_dev(device);
	313	struct mei_device *dev = pci_get_drvdata(pdev);
2703d4b2 TW	314
	315	if (!dev)
	316	return -ENODEV;
2703d4b2	317
ed6f7ac1	318	dev_dbg(&pdev->dev, "suspend\n");
2703d4b2	319
7cb035d9 TW	320	mei_stop(dev);
	321
	322	mei_disable_interrupts(dev);
2703d4b2 TW	323
	324	free_irq(pdev->irq, dev);
	325	pci_disable_msi(pdev);
	326
7cb035d9	327	return 0;
2703d4b2 TW	328	}
2703d4b2 TW	329
b68301e9	330	static int mei_me_pci_resume(struct device *device)
2703d4b2 TW	331	{
	332	struct pci_dev *pdev = to_pci_dev(device);
	333	struct mei_device *dev;
1fa55b4e	334	unsigned int irqflags;
2703d4b2 TW	335	int err;
	336
	337	dev = pci_get_drvdata(pdev);
	338	if (!dev)
	339	return -ENODEV;
	340
	341	pci_enable_msi(pdev);
	342
1fa55b4e AU	343	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
1fa55b4e AU	344
2703d4b2	345	/* request and enable interrupt */
1fa55b4e	346	err = request_threaded_irq(pdev->irq,
06ecd645 TW	347	mei_me_irq_quick_handler,
06ecd645 TW	348	mei_me_irq_thread_handler,
1fa55b4e	349	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	350
	351	if (err) {
	352	dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
	353	pdev->irq);
	354	return err;
	355	}
	356
33ec0826 TW	357	err = mei_restart(dev);
	358	if (err)
	359	return err;
2703d4b2 TW	360
	361	/* Start timer if stopped in suspend */
	362	schedule_delayed_work(&dev->timer_work, HZ);
	363
33ec0826	364	return 0;
2703d4b2	365	}
180ea05b TW	366	#endif /* CONFIG_PM_SLEEP */
180ea05b TW	367
bbd6d050	368	#ifdef CONFIG_PM
180ea05b TW	369	static int mei_me_pm_runtime_idle(struct device *device)
	370	{
	371	struct pci_dev *pdev = to_pci_dev(device);
	372	struct mei_device *dev;
	373
	374	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
	375
	376	dev = pci_get_drvdata(pdev);
	377	if (!dev)
	378	return -ENODEV;
	379	if (mei_write_is_idle(dev))
d5d83f8a	380	pm_runtime_autosuspend(device);
180ea05b TW	381
	382	return -EBUSY;
	383	}
	384
	385	static int mei_me_pm_runtime_suspend(struct device *device)
	386	{
	387	struct pci_dev *pdev = to_pci_dev(device);
	388	struct mei_device *dev;
	389	int ret;
	390
	391	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
	392
	393	dev = pci_get_drvdata(pdev);
	394	if (!dev)
	395	return -ENODEV;
	396
	397	mutex_lock(&dev->device_lock);
	398
	399	if (mei_write_is_idle(dev))
2d1995fc	400	ret = mei_me_pg_enter_sync(dev);
180ea05b TW	401	else
	402	ret = -EAGAIN;
	403
	404	mutex_unlock(&dev->device_lock);
	405
	406	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
	407
77537ad2 AU	408	if (ret && ret != -EAGAIN)
	409	schedule_work(&dev->reset_work);
	410
180ea05b TW	411	return ret;
	412	}
	413
	414	static int mei_me_pm_runtime_resume(struct device *device)
	415	{
	416	struct pci_dev *pdev = to_pci_dev(device);
	417	struct mei_device *dev;
	418	int ret;
	419
	420	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
	421
	422	dev = pci_get_drvdata(pdev);
	423	if (!dev)
	424	return -ENODEV;
	425
	426	mutex_lock(&dev->device_lock);
	427
2d1995fc	428	ret = mei_me_pg_exit_sync(dev);
180ea05b TW	429
	430	mutex_unlock(&dev->device_lock);
	431
	432	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
	433
77537ad2 AU	434	if (ret)
	435	schedule_work(&dev->reset_work);
	436
180ea05b TW	437	return ret;
180ea05b TW	438	}
e13fa90c TW	439
e13fa90c TW	440	/**
7efceb55	441	* mei_me_set_pm_domain - fill and set pm domain structure for device
e13fa90c TW	442	*
	443	* @dev: mei_device
	444	*/
	445	static inline void mei_me_set_pm_domain(struct mei_device *dev)
	446	{
d08b8fc0	447	struct pci_dev *pdev = to_pci_dev(dev->dev);
e13fa90c TW	448
	449	if (pdev->dev.bus && pdev->dev.bus->pm) {
	450	dev->pg_domain.ops = *pdev->dev.bus->pm;
	451
	452	dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
	453	dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
	454	dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
	455
989561de	456	dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
e13fa90c TW	457	}
	458	}
	459
	460	/**
7efceb55	461	* mei_me_unset_pm_domain - clean pm domain structure for device
e13fa90c TW	462	*
	463	* @dev: mei_device
	464	*/
	465	static inline void mei_me_unset_pm_domain(struct mei_device *dev)
	466	{
	467	/* stop using pm callbacks if any */
989561de	468	dev_pm_domain_set(dev->dev, NULL);
e13fa90c	469	}
180ea05b	470
180ea05b TW	471	static const struct dev_pm_ops mei_me_pm_ops = {
	472	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
	473	mei_me_pci_resume)
	474	SET_RUNTIME_PM_OPS(
	475	mei_me_pm_runtime_suspend,
	476	mei_me_pm_runtime_resume,
	477	mei_me_pm_runtime_idle)
	478	};
16833257	479
b68301e9	480	#define MEI_ME_PM_OPS (&mei_me_pm_ops)
2703d4b2	481	#else
b68301e9	482	#define MEI_ME_PM_OPS NULL
180ea05b	483	#endif /* CONFIG_PM */
2703d4b2 TW	484	/*
	485	* PCI driver structure
	486	*/
b68301e9	487	static struct pci_driver mei_me_driver = {
2703d4b2	488	.name = KBUILD_MODNAME,
b68301e9 TW	489	.id_table = mei_me_pci_tbl,
	490	.probe = mei_me_probe,
	491	.remove = mei_me_remove,
5c4c0106	492	.shutdown = mei_me_shutdown,
b68301e9	493	.driver.pm = MEI_ME_PM_OPS,
2703d4b2 TW	494	};
2703d4b2 TW	495
b68301e9	496	module_pci_driver(mei_me_driver);
2703d4b2 TW	497
	498	MODULE_AUTHOR("Intel Corporation");
	499	MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
	500	MODULE_LICENSE("GPL v2");