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2703d4b2 TW |
1 | /* |
2 | * | |
3 | * Intel Management Engine Interface (Intel MEI) Linux driver | |
4 | * Copyright (c) 2003-2012, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/fs.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/fcntl.h> | |
27 | #include <linux/aio.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/poll.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/ioctl.h> | |
32 | #include <linux/cdev.h> | |
33 | #include <linux/sched.h> | |
34 | #include <linux/uuid.h> | |
35 | #include <linux/compat.h> | |
36 | #include <linux/jiffies.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/miscdevice.h> | |
39 | ||
40 | #include <linux/mei.h> | |
41 | ||
42 | #include "mei_dev.h" | |
43 | #include "hw-me.h" | |
44 | #include "client.h" | |
45 | ||
46 | /* AMT device is a singleton on the platform */ | |
47 | static struct pci_dev *mei_pdev; | |
48 | ||
49 | /* mei_pci_tbl - PCI Device ID Table */ | |
50 | static DEFINE_PCI_DEVICE_TABLE(mei_pci_tbl) = { | |
51 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82946GZ)}, | |
52 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G35)}, | |
53 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82Q965)}, | |
54 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G965)}, | |
55 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GM965)}, | |
56 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GME965)}, | |
57 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q35)}, | |
58 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82G33)}, | |
59 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q33)}, | |
60 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82X38)}, | |
61 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_3200)}, | |
62 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_6)}, | |
63 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_7)}, | |
64 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_8)}, | |
65 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_9)}, | |
66 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_10)}, | |
67 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_1)}, | |
68 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_2)}, | |
69 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_3)}, | |
70 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_4)}, | |
71 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_1)}, | |
72 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_2)}, | |
73 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_3)}, | |
74 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_4)}, | |
75 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_1)}, | |
76 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_2)}, | |
77 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_CPT_1)}, | |
78 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PBG_1)}, | |
79 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_1)}, | |
80 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_2)}, | |
81 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_3)}, | |
82 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT)}, | |
83 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_LP)}, | |
84 | ||
85 | /* required last entry */ | |
86 | {0, } | |
87 | }; | |
88 | ||
89 | MODULE_DEVICE_TABLE(pci, mei_pci_tbl); | |
90 | ||
91 | static DEFINE_MUTEX(mei_mutex); | |
92 | ||
2703d4b2 TW |
93 | /** |
94 | * mei_quirk_probe - probe for devices that doesn't valid ME interface | |
95 | * @pdev: PCI device structure | |
96 | * @ent: entry into pci_device_table | |
97 | * | |
98 | * returns true if ME Interface is valid, false otherwise | |
99 | */ | |
100 | static bool mei_quirk_probe(struct pci_dev *pdev, | |
101 | const struct pci_device_id *ent) | |
102 | { | |
103 | u32 reg; | |
104 | if (ent->device == MEI_DEV_ID_PBG_1) { | |
105 | pci_read_config_dword(pdev, 0x48, ®); | |
106 | /* make sure that bit 9 is up and bit 10 is down */ | |
107 | if ((reg & 0x600) == 0x200) { | |
108 | dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); | |
109 | return false; | |
110 | } | |
111 | } | |
112 | return true; | |
113 | } | |
114 | /** | |
115 | * mei_probe - Device Initialization Routine | |
116 | * | |
117 | * @pdev: PCI device structure | |
118 | * @ent: entry in kcs_pci_tbl | |
119 | * | |
120 | * returns 0 on success, <0 on failure. | |
121 | */ | |
52c34561 | 122 | static int mei_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
2703d4b2 TW |
123 | { |
124 | struct mei_device *dev; | |
52c34561 | 125 | struct mei_me_hw *hw; |
2703d4b2 TW |
126 | int err; |
127 | ||
128 | mutex_lock(&mei_mutex); | |
129 | ||
130 | if (!mei_quirk_probe(pdev, ent)) { | |
131 | err = -ENODEV; | |
132 | goto end; | |
133 | } | |
134 | ||
135 | if (mei_pdev) { | |
136 | err = -EEXIST; | |
137 | goto end; | |
138 | } | |
139 | /* enable pci dev */ | |
140 | err = pci_enable_device(pdev); | |
141 | if (err) { | |
142 | dev_err(&pdev->dev, "failed to enable pci device.\n"); | |
143 | goto end; | |
144 | } | |
145 | /* set PCI host mastering */ | |
146 | pci_set_master(pdev); | |
147 | /* pci request regions for mei driver */ | |
148 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
149 | if (err) { | |
150 | dev_err(&pdev->dev, "failed to get pci regions.\n"); | |
151 | goto disable_device; | |
152 | } | |
153 | /* allocates and initializes the mei dev structure */ | |
52c34561 | 154 | dev = mei_me_dev_init(pdev); |
2703d4b2 TW |
155 | if (!dev) { |
156 | err = -ENOMEM; | |
157 | goto release_regions; | |
158 | } | |
52c34561 | 159 | hw = to_me_hw(dev); |
2703d4b2 | 160 | /* mapping IO device memory */ |
52c34561 TW |
161 | hw->mem_addr = pci_iomap(pdev, 0, 0); |
162 | if (!hw->mem_addr) { | |
2703d4b2 TW |
163 | dev_err(&pdev->dev, "mapping I/O device memory failure.\n"); |
164 | err = -ENOMEM; | |
165 | goto free_device; | |
166 | } | |
167 | pci_enable_msi(pdev); | |
168 | ||
169 | /* request and enable interrupt */ | |
170 | if (pci_dev_msi_enabled(pdev)) | |
171 | err = request_threaded_irq(pdev->irq, | |
172 | NULL, | |
06ecd645 | 173 | mei_me_irq_thread_handler, |
2703d4b2 TW |
174 | IRQF_ONESHOT, KBUILD_MODNAME, dev); |
175 | else | |
176 | err = request_threaded_irq(pdev->irq, | |
06ecd645 TW |
177 | mei_me_irq_quick_handler, |
178 | mei_me_irq_thread_handler, | |
2703d4b2 TW |
179 | IRQF_SHARED, KBUILD_MODNAME, dev); |
180 | ||
181 | if (err) { | |
182 | dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", | |
183 | pdev->irq); | |
184 | goto disable_msi; | |
185 | } | |
186 | ||
187 | if (mei_hw_init(dev)) { | |
188 | dev_err(&pdev->dev, "init hw failure.\n"); | |
189 | err = -ENODEV; | |
190 | goto release_irq; | |
191 | } | |
192 | ||
193 | err = mei_register(&pdev->dev); | |
194 | if (err) | |
195 | goto release_irq; | |
196 | ||
197 | mei_pdev = pdev; | |
198 | pci_set_drvdata(pdev, dev); | |
199 | ||
200 | ||
201 | schedule_delayed_work(&dev->timer_work, HZ); | |
202 | ||
203 | mutex_unlock(&mei_mutex); | |
204 | ||
205 | pr_debug("initialization successful.\n"); | |
206 | ||
207 | return 0; | |
208 | ||
209 | release_irq: | |
210 | mei_disable_interrupts(dev); | |
211 | flush_scheduled_work(); | |
212 | free_irq(pdev->irq, dev); | |
213 | disable_msi: | |
214 | pci_disable_msi(pdev); | |
52c34561 | 215 | pci_iounmap(pdev, hw->mem_addr); |
2703d4b2 TW |
216 | free_device: |
217 | kfree(dev); | |
218 | release_regions: | |
219 | pci_release_regions(pdev); | |
220 | disable_device: | |
221 | pci_disable_device(pdev); | |
222 | end: | |
223 | mutex_unlock(&mei_mutex); | |
224 | dev_err(&pdev->dev, "initialization failed.\n"); | |
225 | return err; | |
226 | } | |
227 | ||
228 | /** | |
229 | * mei_remove - Device Removal Routine | |
230 | * | |
231 | * @pdev: PCI device structure | |
232 | * | |
233 | * mei_remove is called by the PCI subsystem to alert the driver | |
234 | * that it should release a PCI device. | |
235 | */ | |
236 | static void mei_remove(struct pci_dev *pdev) | |
237 | { | |
238 | struct mei_device *dev; | |
52c34561 | 239 | struct mei_me_hw *hw; |
2703d4b2 TW |
240 | |
241 | if (mei_pdev != pdev) | |
242 | return; | |
243 | ||
244 | dev = pci_get_drvdata(pdev); | |
245 | if (!dev) | |
246 | return; | |
247 | ||
52c34561 TW |
248 | hw = to_me_hw(dev); |
249 | ||
2703d4b2 | 250 | |
7cb035d9 TW |
251 | dev_err(&pdev->dev, "stop\n"); |
252 | mei_stop(dev); | |
2703d4b2 TW |
253 | |
254 | mei_pdev = NULL; | |
2703d4b2 | 255 | |
2703d4b2 TW |
256 | /* disable interrupts */ |
257 | mei_disable_interrupts(dev); | |
258 | ||
259 | free_irq(pdev->irq, dev); | |
260 | pci_disable_msi(pdev); | |
261 | pci_set_drvdata(pdev, NULL); | |
262 | ||
52c34561 TW |
263 | if (hw->mem_addr) |
264 | pci_iounmap(pdev, hw->mem_addr); | |
2703d4b2 TW |
265 | |
266 | kfree(dev); | |
267 | ||
268 | pci_release_regions(pdev); | |
269 | pci_disable_device(pdev); | |
270 | ||
271 | mei_deregister(); | |
272 | ||
273 | } | |
274 | #ifdef CONFIG_PM | |
275 | static int mei_pci_suspend(struct device *device) | |
276 | { | |
277 | struct pci_dev *pdev = to_pci_dev(device); | |
278 | struct mei_device *dev = pci_get_drvdata(pdev); | |
2703d4b2 TW |
279 | |
280 | if (!dev) | |
281 | return -ENODEV; | |
2703d4b2 | 282 | |
7cb035d9 | 283 | dev_err(&pdev->dev, "suspend\n"); |
2703d4b2 | 284 | |
7cb035d9 TW |
285 | mei_stop(dev); |
286 | ||
287 | mei_disable_interrupts(dev); | |
2703d4b2 TW |
288 | |
289 | free_irq(pdev->irq, dev); | |
290 | pci_disable_msi(pdev); | |
291 | ||
7cb035d9 | 292 | return 0; |
2703d4b2 TW |
293 | } |
294 | ||
295 | static int mei_pci_resume(struct device *device) | |
296 | { | |
297 | struct pci_dev *pdev = to_pci_dev(device); | |
298 | struct mei_device *dev; | |
299 | int err; | |
300 | ||
301 | dev = pci_get_drvdata(pdev); | |
302 | if (!dev) | |
303 | return -ENODEV; | |
304 | ||
305 | pci_enable_msi(pdev); | |
306 | ||
307 | /* request and enable interrupt */ | |
308 | if (pci_dev_msi_enabled(pdev)) | |
309 | err = request_threaded_irq(pdev->irq, | |
310 | NULL, | |
06ecd645 | 311 | mei_me_irq_thread_handler, |
2703d4b2 TW |
312 | IRQF_ONESHOT, KBUILD_MODNAME, dev); |
313 | else | |
314 | err = request_threaded_irq(pdev->irq, | |
06ecd645 TW |
315 | mei_me_irq_quick_handler, |
316 | mei_me_irq_thread_handler, | |
2703d4b2 TW |
317 | IRQF_SHARED, KBUILD_MODNAME, dev); |
318 | ||
319 | if (err) { | |
320 | dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", | |
321 | pdev->irq); | |
322 | return err; | |
323 | } | |
324 | ||
325 | mutex_lock(&dev->device_lock); | |
326 | dev->dev_state = MEI_DEV_POWER_UP; | |
327 | mei_reset(dev, 1); | |
328 | mutex_unlock(&dev->device_lock); | |
329 | ||
330 | /* Start timer if stopped in suspend */ | |
331 | schedule_delayed_work(&dev->timer_work, HZ); | |
332 | ||
333 | return err; | |
334 | } | |
335 | static SIMPLE_DEV_PM_OPS(mei_pm_ops, mei_pci_suspend, mei_pci_resume); | |
336 | #define MEI_PM_OPS (&mei_pm_ops) | |
337 | #else | |
338 | #define MEI_PM_OPS NULL | |
339 | #endif /* CONFIG_PM */ | |
340 | /* | |
341 | * PCI driver structure | |
342 | */ | |
343 | static struct pci_driver mei_driver = { | |
344 | .name = KBUILD_MODNAME, | |
345 | .id_table = mei_pci_tbl, | |
346 | .probe = mei_probe, | |
347 | .remove = mei_remove, | |
348 | .shutdown = mei_remove, | |
349 | .driver.pm = MEI_PM_OPS, | |
350 | }; | |
351 | ||
352 | module_pci_driver(mei_driver); | |
353 | ||
354 | MODULE_AUTHOR("Intel Corporation"); | |
355 | MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); | |
356 | MODULE_LICENSE("GPL v2"); |