[mirror_ubuntu-artful-kernel.git] / drivers / misc / mei / pci-me.c

/*
 *
 * Intel Management Engine Interface (Intel MEI) Linux driver
 * Copyright (c) 2003-2012, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/pci.h>
#include <linux/poll.h>
#include <linux/ioctl.h>
#include <linux/cdev.h>
#include <linux/sched.h>
#include <linux/uuid.h>
#include <linux/compat.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>

#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

#include <linux/mei.h>

#include "mei_dev.h"
#include "client.h"
#include "hw-me-regs.h"
#include "hw-me.h"

/* mei_pci_tbl - PCI Device ID Table */
static const struct pci_device_id mei_me_pci_tbl[] = {
	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, mei_me_legacy_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, mei_me_ich_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, mei_me_ich_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, mei_me_ich_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, mei_me_ich_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, mei_me_pch8_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, mei_me_pch8_sps_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, mei_me_pch8_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, mei_me_pch8_cfg)},

	/* required last entry */
	{0, }
};

MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);

#ifdef CONFIG_PM
static inline void mei_me_set_pm_domain(struct mei_device *dev);
static inline void mei_me_unset_pm_domain(struct mei_device *dev);
#else
static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
#endif /* CONFIG_PM */

/**
 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 *
 * @pdev: PCI device structure
 * @cfg: per generation config
 *
 * Return: true if ME Interface is valid, false otherwise
 */
static bool mei_me_quirk_probe(struct pci_dev *pdev,
				const struct mei_cfg *cfg)
{
	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
		dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
		return false;
	}

	return true;
}

/**
 * mei_me_probe - Device Initialization Routine
 *
 * @pdev: PCI device structure
 * @ent: entry in kcs_pci_tbl
 *
 * Return: 0 on success, <0 on failure.
 */
static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct mei_cfg *cfg = (struct mei_cfg *)(ent->driver_data);
	struct mei_device *dev;
	struct mei_me_hw *hw;
	unsigned int irqflags;
	int err;


	if (!mei_me_quirk_probe(pdev, cfg))
		return -ENODEV;

	/* enable pci dev */
	err = pci_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "failed to enable pci device.\n");
		goto end;
	}
	/* set PCI host mastering  */
	pci_set_master(pdev);
	/* pci request regions for mei driver */
	err = pci_request_regions(pdev, KBUILD_MODNAME);
	if (err) {
		dev_err(&pdev->dev, "failed to get pci regions.\n");
		goto disable_device;
	}

	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
	    dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {

		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
		if (err)
			err = dma_set_coherent_mask(&pdev->dev,
						    DMA_BIT_MASK(32));
	}
	if (err) {
		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
		goto release_regions;
	}


	/* allocates and initializes the mei dev structure */
	dev = mei_me_dev_init(pdev, cfg);
	if (!dev) {
		err = -ENOMEM;
		goto release_regions;
	}
	hw = to_me_hw(dev);
	/* mapping  IO device memory */
	hw->mem_addr = pci_iomap(pdev, 0, 0);
	if (!hw->mem_addr) {
		dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
		err = -ENOMEM;
		goto free_device;
	}
	pci_enable_msi(pdev);

	 /* request and enable interrupt */
	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);
	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
		       pdev->irq);
		goto disable_msi;
	}

	if (mei_start(dev)) {
		dev_err(&pdev->dev, "init hw failure.\n");
		err = -ENODEV;
		goto release_irq;
	}

	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);

	err = mei_register(dev, &pdev->dev);
	if (err)
		goto stop;

	pci_set_drvdata(pdev, dev);

	/*
	* For not wake-able HW runtime pm framework
	* can't be used on pci device level.
	* Use domain runtime pm callbacks instead.
	*/
	if (!pci_dev_run_wake(pdev))
		mei_me_set_pm_domain(dev);

	if (mei_pg_is_enabled(dev))
		pm_runtime_put_noidle(&pdev->dev);

	dev_dbg(&pdev->dev, "initialization successful.\n");

	return 0;

stop:
	mei_stop(dev);
release_irq:
	mei_cancel_work(dev);
	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
disable_msi:
	pci_disable_msi(pdev);
	pci_iounmap(pdev, hw->mem_addr);
free_device:
	kfree(dev);
release_regions:
	pci_release_regions(pdev);
disable_device:
	pci_disable_device(pdev);
end:
	dev_err(&pdev->dev, "initialization failed.\n");
	return err;
}

/**
 * mei_me_remove - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_remove is called by the PCI subsystem to alert the driver
 * that it should release a PCI device.
 */
static void mei_me_remove(struct pci_dev *pdev)
{
	struct mei_device *dev;
	struct mei_me_hw *hw;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return;

	if (mei_pg_is_enabled(dev))
		pm_runtime_get_noresume(&pdev->dev);

	hw = to_me_hw(dev);


	dev_dbg(&pdev->dev, "stop\n");
	mei_stop(dev);

	if (!pci_dev_run_wake(pdev))
		mei_me_unset_pm_domain(dev);

	/* disable interrupts */
	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	if (hw->mem_addr)
		pci_iounmap(pdev, hw->mem_addr);

	mei_deregister(dev);

	kfree(dev);

	pci_release_regions(pdev);
	pci_disable_device(pdev);


}
#ifdef CONFIG_PM_SLEEP
static int mei_me_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev = pci_get_drvdata(pdev);

	if (!dev)
		return -ENODEV;

	dev_dbg(&pdev->dev, "suspend\n");

	mei_stop(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	return 0;
}

static int mei_me_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	unsigned int irqflags;
	int err;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	pci_enable_msi(pdev);

	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	/* request and enable interrupt */
	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);

	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
				pdev->irq);
		return err;
	}

	err = mei_restart(dev);
	if (err)
		return err;

	/* Start timer if stopped in suspend */
	schedule_delayed_work(&dev->timer_work, HZ);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

#ifdef CONFIG_PM
static int mei_me_pm_runtime_idle(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;

	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;
	if (mei_write_is_idle(dev))
		pm_runtime_autosuspend(device);

	return -EBUSY;
}

static int mei_me_pm_runtime_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int ret;

	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	if (mei_write_is_idle(dev))
		ret = mei_me_pg_enter_sync(dev);
	else
		ret = -EAGAIN;

	mutex_unlock(&dev->device_lock);

	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);

	if (ret && ret != -EAGAIN)
		schedule_work(&dev->reset_work);

	return ret;
}

static int mei_me_pm_runtime_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int ret;

	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	ret = mei_me_pg_exit_sync(dev);

	mutex_unlock(&dev->device_lock);

	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);

	if (ret)
		schedule_work(&dev->reset_work);

	return ret;
}

/**
 * mei_me_set_pm_domain - fill and set pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_set_pm_domain(struct mei_device *dev)
{
	struct pci_dev *pdev  = to_pci_dev(dev->dev);

	if (pdev->dev.bus && pdev->dev.bus->pm) {
		dev->pg_domain.ops = *pdev->dev.bus->pm;

		dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
		dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
		dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;

		dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
	}
}

/**
 * mei_me_unset_pm_domain - clean pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_unset_pm_domain(struct mei_device *dev)
{
	/* stop using pm callbacks if any */
	dev_pm_domain_set(dev->dev, NULL);
}

static const struct dev_pm_ops mei_me_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
				mei_me_pci_resume)
	SET_RUNTIME_PM_OPS(
		mei_me_pm_runtime_suspend,
		mei_me_pm_runtime_resume,
		mei_me_pm_runtime_idle)
};

#define MEI_ME_PM_OPS	(&mei_me_pm_ops)
#else
#define MEI_ME_PM_OPS	NULL
#endif /* CONFIG_PM */
/*
 *  PCI driver structure
 */
static struct pci_driver mei_me_driver = {
	.name = KBUILD_MODNAME,
	.id_table = mei_me_pci_tbl,
	.probe = mei_me_probe,
	.remove = mei_me_remove,
	.shutdown = mei_me_remove,
	.driver.pm = MEI_ME_PM_OPS,
};

module_pci_driver(mei_me_driver);

MODULE_AUTHOR("Intel Corporation");
MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2703d4b2 TW	1	/*
	2	*
	3	* Intel Management Engine Interface (Intel MEI) Linux driver
	4	* Copyright (c) 2003-2012, Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	*/
2703d4b2 TW	16	#include <linux/module.h>
	17	#include <linux/moduleparam.h>
	18	#include <linux/kernel.h>
	19	#include <linux/device.h>
	20	#include <linux/fs.h>
	21	#include <linux/errno.h>
	22	#include <linux/types.h>
	23	#include <linux/fcntl.h>
2703d4b2 TW	24	#include <linux/pci.h>
2703d4b2 TW	25	#include <linux/poll.h>
2703d4b2 TW	26	#include <linux/ioctl.h>
	27	#include <linux/cdev.h>
	28	#include <linux/sched.h>
	29	#include <linux/uuid.h>
	30	#include <linux/compat.h>
	31	#include <linux/jiffies.h>
	32	#include <linux/interrupt.h>
2703d4b2	33
989561de	34	#include <linux/pm_domain.h>
180ea05b TW	35	#include <linux/pm_runtime.h>
180ea05b TW	36
2703d4b2 TW	37	#include <linux/mei.h>
	38
	39	#include "mei_dev.h"
2703d4b2	40	#include "client.h"
6e4cd27a TW	41	#include "hw-me-regs.h"
6e4cd27a TW	42	#include "hw-me.h"
2703d4b2	43
2703d4b2	44	/* mei_pci_tbl - PCI Device ID Table */
a05f8f86	45	static const struct pci_device_id mei_me_pci_tbl[] = {
8d929d48 AU	46	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, mei_me_legacy_cfg)},
	47	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, mei_me_legacy_cfg)},
	48	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, mei_me_legacy_cfg)},
	49	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, mei_me_legacy_cfg)},
	50	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, mei_me_legacy_cfg)},
	51	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, mei_me_legacy_cfg)},
	52	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, mei_me_legacy_cfg)},
	53	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, mei_me_legacy_cfg)},
	54	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, mei_me_legacy_cfg)},
	55	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, mei_me_legacy_cfg)},
	56	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, mei_me_legacy_cfg)},
	57
	58	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, mei_me_legacy_cfg)},
	59	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, mei_me_legacy_cfg)},
	60	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, mei_me_legacy_cfg)},
	61	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, mei_me_legacy_cfg)},
	62	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, mei_me_legacy_cfg)},
	63	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, mei_me_legacy_cfg)},
	64	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, mei_me_legacy_cfg)},
	65	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, mei_me_legacy_cfg)},
	66	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, mei_me_legacy_cfg)},
	67	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, mei_me_ich_cfg)},
	68	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, mei_me_ich_cfg)},
	69	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, mei_me_ich_cfg)},
	70	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, mei_me_ich_cfg)},
	71
	72	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)},
	73	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)},
c919951d TW	74	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)},
c919951d TW	75	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)},
8d929d48 AU	76	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)},
	77	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)},
	78	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)},
edca5ea3 AU	79	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_pch8_sps_cfg)},
	80	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_pch8_sps_cfg)},
	81	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch8_cfg)},
	82	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_pch8_sps_cfg)},
	83	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch8_cfg)},
	84	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, mei_me_pch8_cfg)},
2703d4b2	85
1625c7ec TW	86	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, mei_me_pch8_cfg)},
1625c7ec TW	87	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, mei_me_pch8_cfg)},
8c57cac1 TW	88	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, mei_me_pch8_sps_cfg)},
8c57cac1 TW	89	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, mei_me_pch8_sps_cfg)},
1625c7ec	90
dd16f6cd TW	91	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, mei_me_pch8_cfg)},
	92	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, mei_me_pch8_cfg)},
	93
ac182e8a AU	94	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, mei_me_pch8_cfg)},
	95	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, mei_me_pch8_cfg)},
	96
2703d4b2 TW	97	/* required last entry */
	98	{0, }
	99	};
	100
b68301e9	101	MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
2703d4b2	102
bbd6d050	103	#ifdef CONFIG_PM
e13fa90c TW	104	static inline void mei_me_set_pm_domain(struct mei_device *dev);
	105	static inline void mei_me_unset_pm_domain(struct mei_device *dev);
	106	#else
	107	static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
	108	static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
bbd6d050	109	#endif /* CONFIG_PM */
e13fa90c	110
2703d4b2	111	/**
ce23139c	112	* mei_me_quirk_probe - probe for devices that doesn't valid ME interface
393b148f	113	*
2703d4b2	114	* @pdev: PCI device structure
c919951d	115	* @cfg: per generation config
2703d4b2	116	*
a8605ea2	117	* Return: true if ME Interface is valid, false otherwise
2703d4b2	118	*/
b68301e9	119	static bool mei_me_quirk_probe(struct pci_dev *pdev,
c919951d	120	const struct mei_cfg *cfg)
2703d4b2	121	{
c919951d TW	122	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
	123	dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
	124	return false;
5e6533a6 TW	125	}
5e6533a6 TW	126
2703d4b2 TW	127	return true;
2703d4b2 TW	128	}
c919951d	129
2703d4b2	130	/**
ce23139c	131	* mei_me_probe - Device Initialization Routine
2703d4b2 TW	132	*
	133	* @pdev: PCI device structure
	134	* @ent: entry in kcs_pci_tbl
	135	*
a8605ea2	136	* Return: 0 on success, <0 on failure.
2703d4b2	137	*/
b68301e9	138	static int mei_me_probe(struct pci_dev pdev, const struct pci_device_id ent)
2703d4b2	139	{
8d929d48	140	const struct mei_cfg cfg = (struct mei_cfg )(ent->driver_data);
2703d4b2	141	struct mei_device *dev;
52c34561	142	struct mei_me_hw *hw;
1fa55b4e	143	unsigned int irqflags;
2703d4b2 TW	144	int err;
2703d4b2 TW	145
2703d4b2	146
c919951d TW	147	if (!mei_me_quirk_probe(pdev, cfg))
c919951d TW	148	return -ENODEV;
2703d4b2	149
2703d4b2 TW	150	/* enable pci dev */
	151	err = pci_enable_device(pdev);
	152	if (err) {
	153	dev_err(&pdev->dev, "failed to enable pci device.\n");
	154	goto end;
	155	}
	156	/* set PCI host mastering */
	157	pci_set_master(pdev);
	158	/* pci request regions for mei driver */
	159	err = pci_request_regions(pdev, KBUILD_MODNAME);
	160	if (err) {
	161	dev_err(&pdev->dev, "failed to get pci regions.\n");
	162	goto disable_device;
	163	}
3ecfb168 TW	164
	165	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) \|\|
	166	dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
	167
	168	err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
	169	if (err)
	170	err = dma_set_coherent_mask(&pdev->dev,
	171	DMA_BIT_MASK(32));
	172	}
	173	if (err) {
	174	dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
	175	goto release_regions;
	176	}
	177
	178
2703d4b2	179	/* allocates and initializes the mei dev structure */
8d929d48	180	dev = mei_me_dev_init(pdev, cfg);
2703d4b2 TW	181	if (!dev) {
	182	err = -ENOMEM;
	183	goto release_regions;
	184	}
52c34561	185	hw = to_me_hw(dev);
2703d4b2	186	/* mapping IO device memory */
52c34561 TW	187	hw->mem_addr = pci_iomap(pdev, 0, 0);
52c34561 TW	188	if (!hw->mem_addr) {
2703d4b2 TW	189	dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
	190	err = -ENOMEM;
	191	goto free_device;
	192	}
	193	pci_enable_msi(pdev);
	194
	195	/* request and enable interrupt */
1fa55b4e AU	196	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
	197
	198	err = request_threaded_irq(pdev->irq,
06ecd645 TW	199	mei_me_irq_quick_handler,
06ecd645 TW	200	mei_me_irq_thread_handler,
1fa55b4e	201	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	202	if (err) {
	203	dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
	204	pdev->irq);
	205	goto disable_msi;
	206	}
	207
c4d589be	208	if (mei_start(dev)) {
2703d4b2 TW	209	dev_err(&pdev->dev, "init hw failure.\n");
	210	err = -ENODEV;
	211	goto release_irq;
	212	}
	213
180ea05b TW	214	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	215	pm_runtime_use_autosuspend(&pdev->dev);
	216
f3d8e878	217	err = mei_register(dev, &pdev->dev);
2703d4b2	218	if (err)
1f7e489a	219	goto stop;
2703d4b2	220
2703d4b2 TW	221	pci_set_drvdata(pdev, dev);
2703d4b2 TW	222
e13fa90c TW	223	/*
	224	* For not wake-able HW runtime pm framework
	225	* can't be used on pci device level.
	226	* Use domain runtime pm callbacks instead.
	227	*/
	228	if (!pci_dev_run_wake(pdev))
	229	mei_me_set_pm_domain(dev);
	230
180ea05b TW	231	if (mei_pg_is_enabled(dev))
	232	pm_runtime_put_noidle(&pdev->dev);
	233
c4e87b52	234	dev_dbg(&pdev->dev, "initialization successful.\n");
2703d4b2 TW	235
	236	return 0;
	237
1f7e489a AU	238	stop:
1f7e489a AU	239	mei_stop(dev);
2703d4b2	240	release_irq:
dc844b0d	241	mei_cancel_work(dev);
2703d4b2	242	mei_disable_interrupts(dev);
2703d4b2 TW	243	free_irq(pdev->irq, dev);
	244	disable_msi:
	245	pci_disable_msi(pdev);
52c34561	246	pci_iounmap(pdev, hw->mem_addr);
2703d4b2 TW	247	free_device:
	248	kfree(dev);
	249	release_regions:
	250	pci_release_regions(pdev);
	251	disable_device:
	252	pci_disable_device(pdev);
	253	end:
2703d4b2 TW	254	dev_err(&pdev->dev, "initialization failed.\n");
	255	return err;
	256	}
	257
	258	/**
ce23139c	259	* mei_me_remove - Device Removal Routine
2703d4b2 TW	260	*
	261	* @pdev: PCI device structure
	262	*
	263	* mei_remove is called by the PCI subsystem to alert the driver
	264	* that it should release a PCI device.
	265	*/
b68301e9	266	static void mei_me_remove(struct pci_dev *pdev)
2703d4b2 TW	267	{
2703d4b2 TW	268	struct mei_device *dev;
52c34561	269	struct mei_me_hw *hw;
2703d4b2	270
2703d4b2 TW	271	dev = pci_get_drvdata(pdev);
	272	if (!dev)
	273	return;
	274
180ea05b TW	275	if (mei_pg_is_enabled(dev))
	276	pm_runtime_get_noresume(&pdev->dev);
	277
52c34561 TW	278	hw = to_me_hw(dev);
52c34561 TW	279
2703d4b2	280
ed6f7ac1	281	dev_dbg(&pdev->dev, "stop\n");
7cb035d9	282	mei_stop(dev);
2703d4b2	283
e13fa90c TW	284	if (!pci_dev_run_wake(pdev))
	285	mei_me_unset_pm_domain(dev);
	286
2703d4b2 TW	287	/* disable interrupts */
	288	mei_disable_interrupts(dev);
	289
	290	free_irq(pdev->irq, dev);
	291	pci_disable_msi(pdev);
2703d4b2	292
52c34561 TW	293	if (hw->mem_addr)
52c34561 TW	294	pci_iounmap(pdev, hw->mem_addr);
2703d4b2	295
30e53bb8 TW	296	mei_deregister(dev);
30e53bb8 TW	297
2703d4b2 TW	298	kfree(dev);
	299
	300	pci_release_regions(pdev);
	301	pci_disable_device(pdev);
	302
2703d4b2 TW	303
2703d4b2 TW	304	}
16833257	305	#ifdef CONFIG_PM_SLEEP
b68301e9	306	static int mei_me_pci_suspend(struct device *device)
2703d4b2 TW	307	{
	308	struct pci_dev *pdev = to_pci_dev(device);
	309	struct mei_device *dev = pci_get_drvdata(pdev);
2703d4b2 TW	310
	311	if (!dev)
	312	return -ENODEV;
2703d4b2	313
ed6f7ac1	314	dev_dbg(&pdev->dev, "suspend\n");
2703d4b2	315
7cb035d9 TW	316	mei_stop(dev);
	317
	318	mei_disable_interrupts(dev);
2703d4b2 TW	319
	320	free_irq(pdev->irq, dev);
	321	pci_disable_msi(pdev);
	322
7cb035d9	323	return 0;
2703d4b2 TW	324	}
2703d4b2 TW	325
b68301e9	326	static int mei_me_pci_resume(struct device *device)
2703d4b2 TW	327	{
	328	struct pci_dev *pdev = to_pci_dev(device);
	329	struct mei_device *dev;
1fa55b4e	330	unsigned int irqflags;
2703d4b2 TW	331	int err;
	332
	333	dev = pci_get_drvdata(pdev);
	334	if (!dev)
	335	return -ENODEV;
	336
	337	pci_enable_msi(pdev);
	338
1fa55b4e AU	339	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
1fa55b4e AU	340
2703d4b2	341	/* request and enable interrupt */
1fa55b4e	342	err = request_threaded_irq(pdev->irq,
06ecd645 TW	343	mei_me_irq_quick_handler,
06ecd645 TW	344	mei_me_irq_thread_handler,
1fa55b4e	345	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	346
	347	if (err) {
	348	dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
	349	pdev->irq);
	350	return err;
	351	}
	352
33ec0826 TW	353	err = mei_restart(dev);
	354	if (err)
	355	return err;
2703d4b2 TW	356
	357	/* Start timer if stopped in suspend */
	358	schedule_delayed_work(&dev->timer_work, HZ);
	359
33ec0826	360	return 0;
2703d4b2	361	}
180ea05b TW	362	#endif /* CONFIG_PM_SLEEP */
180ea05b TW	363
bbd6d050	364	#ifdef CONFIG_PM
180ea05b TW	365	static int mei_me_pm_runtime_idle(struct device *device)
	366	{
	367	struct pci_dev *pdev = to_pci_dev(device);
	368	struct mei_device *dev;
	369
	370	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
	371
	372	dev = pci_get_drvdata(pdev);
	373	if (!dev)
	374	return -ENODEV;
	375	if (mei_write_is_idle(dev))
d5d83f8a	376	pm_runtime_autosuspend(device);
180ea05b TW	377
	378	return -EBUSY;
	379	}
	380
	381	static int mei_me_pm_runtime_suspend(struct device *device)
	382	{
	383	struct pci_dev *pdev = to_pci_dev(device);
	384	struct mei_device *dev;
	385	int ret;
	386
	387	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
	388
	389	dev = pci_get_drvdata(pdev);
	390	if (!dev)
	391	return -ENODEV;
	392
	393	mutex_lock(&dev->device_lock);
	394
	395	if (mei_write_is_idle(dev))
2d1995fc	396	ret = mei_me_pg_enter_sync(dev);
180ea05b TW	397	else
	398	ret = -EAGAIN;
	399
	400	mutex_unlock(&dev->device_lock);
	401
	402	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
	403
77537ad2 AU	404	if (ret && ret != -EAGAIN)
	405	schedule_work(&dev->reset_work);
	406
180ea05b TW	407	return ret;
	408	}
	409
	410	static int mei_me_pm_runtime_resume(struct device *device)
	411	{
	412	struct pci_dev *pdev = to_pci_dev(device);
	413	struct mei_device *dev;
	414	int ret;
	415
	416	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
	417
	418	dev = pci_get_drvdata(pdev);
	419	if (!dev)
	420	return -ENODEV;
	421
	422	mutex_lock(&dev->device_lock);
	423
2d1995fc	424	ret = mei_me_pg_exit_sync(dev);
180ea05b TW	425
	426	mutex_unlock(&dev->device_lock);
	427
	428	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
	429
77537ad2 AU	430	if (ret)
	431	schedule_work(&dev->reset_work);
	432
180ea05b TW	433	return ret;
180ea05b TW	434	}
e13fa90c TW	435
e13fa90c TW	436	/**
7efceb55	437	* mei_me_set_pm_domain - fill and set pm domain structure for device
e13fa90c TW	438	*
	439	* @dev: mei_device
	440	*/
	441	static inline void mei_me_set_pm_domain(struct mei_device *dev)
	442	{
d08b8fc0	443	struct pci_dev *pdev = to_pci_dev(dev->dev);
e13fa90c TW	444
	445	if (pdev->dev.bus && pdev->dev.bus->pm) {
	446	dev->pg_domain.ops = *pdev->dev.bus->pm;
	447
	448	dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
	449	dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
	450	dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
	451
989561de	452	dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
e13fa90c TW	453	}
	454	}
	455
	456	/**
7efceb55	457	* mei_me_unset_pm_domain - clean pm domain structure for device
e13fa90c TW	458	*
	459	* @dev: mei_device
	460	*/
	461	static inline void mei_me_unset_pm_domain(struct mei_device *dev)
	462	{
	463	/* stop using pm callbacks if any */
989561de	464	dev_pm_domain_set(dev->dev, NULL);
e13fa90c	465	}
180ea05b	466
180ea05b TW	467	static const struct dev_pm_ops mei_me_pm_ops = {
	468	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
	469	mei_me_pci_resume)
	470	SET_RUNTIME_PM_OPS(
	471	mei_me_pm_runtime_suspend,
	472	mei_me_pm_runtime_resume,
	473	mei_me_pm_runtime_idle)
	474	};
16833257	475
b68301e9	476	#define MEI_ME_PM_OPS (&mei_me_pm_ops)
2703d4b2	477	#else
b68301e9	478	#define MEI_ME_PM_OPS NULL
180ea05b	479	#endif /* CONFIG_PM */
2703d4b2 TW	480	/*
	481	* PCI driver structure
	482	*/
b68301e9	483	static struct pci_driver mei_me_driver = {
2703d4b2	484	.name = KBUILD_MODNAME,
b68301e9 TW	485	.id_table = mei_me_pci_tbl,
	486	.probe = mei_me_probe,
	487	.remove = mei_me_remove,
	488	.shutdown = mei_me_remove,
	489	.driver.pm = MEI_ME_PM_OPS,
2703d4b2 TW	490	};
2703d4b2 TW	491
b68301e9	492	module_pci_driver(mei_me_driver);
2703d4b2 TW	493
	494	MODULE_AUTHOR("Intel Corporation");
	495	MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
	496	MODULE_LICENSE("GPL v2");