[mirror_ubuntu-jammy-kernel.git] / drivers / misc / pci_endpoint_test.c

/**
 * Host side test driver to test endpoint functionality
 *
 * Copyright (C) 2017 Texas Instruments
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 of
 * the License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/crc32.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/miscdevice.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/random.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>

#include <linux/pci_regs.h>

#include <uapi/linux/pcitest.h>

#define DRV_MODULE_NAME			"pci-endpoint-test"

#define PCI_ENDPOINT_TEST_MAGIC		0x0

#define PCI_ENDPOINT_TEST_COMMAND	0x4
#define COMMAND_RAISE_LEGACY_IRQ	BIT(0)
#define COMMAND_RAISE_MSI_IRQ		BIT(1)
#define MSI_NUMBER_SHIFT		2
/* 6 bits for MSI number */
#define COMMAND_READ                    BIT(8)
#define COMMAND_WRITE                   BIT(9)
#define COMMAND_COPY                    BIT(10)

#define PCI_ENDPOINT_TEST_STATUS	0x8
#define STATUS_READ_SUCCESS             BIT(0)
#define STATUS_READ_FAIL                BIT(1)
#define STATUS_WRITE_SUCCESS            BIT(2)
#define STATUS_WRITE_FAIL               BIT(3)
#define STATUS_COPY_SUCCESS             BIT(4)
#define STATUS_COPY_FAIL                BIT(5)
#define STATUS_IRQ_RAISED               BIT(6)
#define STATUS_SRC_ADDR_INVALID         BIT(7)
#define STATUS_DST_ADDR_INVALID         BIT(8)

#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR	0xc
#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR	0x10

#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR	0x14
#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR	0x18

#define PCI_ENDPOINT_TEST_SIZE		0x1c
#define PCI_ENDPOINT_TEST_CHECKSUM	0x20

static DEFINE_IDA(pci_endpoint_test_ida);

#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
					    miscdev)
enum pci_barno {
	BAR_0,
	BAR_1,
	BAR_2,
	BAR_3,
	BAR_4,
	BAR_5,
};

struct pci_endpoint_test {
	struct pci_dev	*pdev;
	void __iomem	*base;
	void __iomem	*bar[6];
	struct completion irq_raised;
	int		last_irq;
	/* mutex to protect the ioctls */
	struct mutex	mutex;
	struct miscdevice miscdev;
	enum pci_barno test_reg_bar;
};

struct pci_endpoint_test_data {
	enum pci_barno test_reg_bar;
};

static int bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };

static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
					  u32 offset)
{
	return readl(test->base + offset);
}

static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
					    u32 offset, u32 value)
{
	writel(value, test->base + offset);
}

static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
					      int bar, int offset)
{
	return readl(test->bar[bar] + offset);
}

static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
						int bar, u32 offset, u32 value)
{
	writel(value, test->bar[bar] + offset);
}

static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
{
	struct pci_endpoint_test *test = dev_id;
	u32 reg;

	reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
	if (reg & STATUS_IRQ_RAISED) {
		test->last_irq = irq;
		complete(&test->irq_raised);
		reg &= ~STATUS_IRQ_RAISED;
	}
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
				 reg);

	return IRQ_HANDLED;
}

static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
				  enum pci_barno barno)
{
	int j;
	u32 val;
	int size;

	if (!test->bar[barno])
		return false;

	size = bar_size[barno];

	if (barno == test->test_reg_bar)
		size = 0x4;

	for (j = 0; j < size; j += 4)
		pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);

	for (j = 0; j < size; j += 4) {
		val = pci_endpoint_test_bar_readl(test, barno, j);
		if (val != 0xA0A0A0A0)
			return false;
	}

	return true;
}

static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
{
	u32 val;

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
				 COMMAND_RAISE_LEGACY_IRQ);
	val = wait_for_completion_timeout(&test->irq_raised,
					  msecs_to_jiffies(1000));
	if (!val)
		return false;

	return true;
}

static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
				      u8 msi_num)
{
	u32 val;
	struct pci_dev *pdev = test->pdev;

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
				 msi_num << MSI_NUMBER_SHIFT |
				 COMMAND_RAISE_MSI_IRQ);
	val = wait_for_completion_timeout(&test->irq_raised,
					  msecs_to_jiffies(1000));
	if (!val)
		return false;

	if (test->last_irq - pdev->irq == msi_num - 1)
		return true;

	return false;
}

static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
{
	bool ret = false;
	void *src_addr;
	void *dst_addr;
	dma_addr_t src_phys_addr;
	dma_addr_t dst_phys_addr;
	struct pci_dev *pdev = test->pdev;
	struct device *dev = &pdev->dev;
	u32 src_crc32;
	u32 dst_crc32;

	src_addr = dma_alloc_coherent(dev, size, &src_phys_addr, GFP_KERNEL);
	if (!src_addr) {
		dev_err(dev, "failed to allocate source buffer\n");
		ret = false;
		goto err;
	}

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
				 lower_32_bits(src_phys_addr));

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
				 upper_32_bits(src_phys_addr));

	get_random_bytes(src_addr, size);
	src_crc32 = crc32_le(~0, src_addr, size);

	dst_addr = dma_alloc_coherent(dev, size, &dst_phys_addr, GFP_KERNEL);
	if (!dst_addr) {
		dev_err(dev, "failed to allocate destination address\n");
		ret = false;
		goto err_src_addr;
	}

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
				 lower_32_bits(dst_phys_addr));
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
				 upper_32_bits(dst_phys_addr));

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
				 size);

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
				 1 << MSI_NUMBER_SHIFT | COMMAND_COPY);

	wait_for_completion(&test->irq_raised);

	dst_crc32 = crc32_le(~0, dst_addr, size);
	if (dst_crc32 == src_crc32)
		ret = true;

	dma_free_coherent(dev, size, dst_addr, dst_phys_addr);

err_src_addr:
	dma_free_coherent(dev, size, src_addr, src_phys_addr);

err:
	return ret;
}

static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
{
	bool ret = false;
	u32 reg;
	void *addr;
	dma_addr_t phys_addr;
	struct pci_dev *pdev = test->pdev;
	struct device *dev = &pdev->dev;
	u32 crc32;

	addr = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
	if (!addr) {
		dev_err(dev, "failed to allocate address\n");
		ret = false;
		goto err;
	}

	get_random_bytes(addr, size);

	crc32 = crc32_le(~0, addr, size);
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
				 crc32);

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
				 lower_32_bits(phys_addr));
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
				 upper_32_bits(phys_addr));

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
				 1 << MSI_NUMBER_SHIFT | COMMAND_READ);

	wait_for_completion(&test->irq_raised);

	reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
	if (reg & STATUS_READ_SUCCESS)
		ret = true;

	dma_free_coherent(dev, size, addr, phys_addr);

err:
	return ret;
}

static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
{
	bool ret = false;
	void *addr;
	dma_addr_t phys_addr;
	struct pci_dev *pdev = test->pdev;
	struct device *dev = &pdev->dev;
	u32 crc32;

	addr = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
	if (!addr) {
		dev_err(dev, "failed to allocate destination address\n");
		ret = false;
		goto err;
	}

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
				 lower_32_bits(phys_addr));
	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
				 upper_32_bits(phys_addr));

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);

	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
				 1 << MSI_NUMBER_SHIFT | COMMAND_WRITE);

	wait_for_completion(&test->irq_raised);

	crc32 = crc32_le(~0, addr, size);
	if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
		ret = true;

	dma_free_coherent(dev, size, addr, phys_addr);
err:
	return ret;
}

static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
				    unsigned long arg)
{
	int ret = -EINVAL;
	enum pci_barno bar;
	struct pci_endpoint_test *test = to_endpoint_test(file->private_data);

	mutex_lock(&test->mutex);
	switch (cmd) {
	case PCITEST_BAR:
		bar = arg;
		if (bar < 0 || bar > 5)
			goto ret;
		ret = pci_endpoint_test_bar(test, bar);
		break;
	case PCITEST_LEGACY_IRQ:
		ret = pci_endpoint_test_legacy_irq(test);
		break;
	case PCITEST_MSI:
		ret = pci_endpoint_test_msi_irq(test, arg);
		break;
	case PCITEST_WRITE:
		ret = pci_endpoint_test_write(test, arg);
		break;
	case PCITEST_READ:
		ret = pci_endpoint_test_read(test, arg);
		break;
	case PCITEST_COPY:
		ret = pci_endpoint_test_copy(test, arg);
		break;
	}

ret:
	mutex_unlock(&test->mutex);
	return ret;
}

static const struct file_operations pci_endpoint_test_fops = {
	.owner = THIS_MODULE,
	.unlocked_ioctl = pci_endpoint_test_ioctl,
};

static int pci_endpoint_test_probe(struct pci_dev *pdev,
				   const struct pci_device_id *ent)
{
	int i;
	int err;
	int irq;
	int id;
	char name[20];
	enum pci_barno bar;
	void __iomem *base;
	struct device *dev = &pdev->dev;
	struct pci_endpoint_test *test;
	struct pci_endpoint_test_data *data;
	enum pci_barno test_reg_bar = BAR_0;
	struct miscdevice *misc_device;

	if (pci_is_bridge(pdev))
		return -ENODEV;

	test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
	if (!test)
		return -ENOMEM;

	test->test_reg_bar = 0;
	test->pdev = pdev;

	data = (struct pci_endpoint_test_data *)ent->driver_data;
	if (data)
		test_reg_bar = data->test_reg_bar;

	init_completion(&test->irq_raised);
	mutex_init(&test->mutex);

	err = pci_enable_device(pdev);
	if (err) {
		dev_err(dev, "Cannot enable PCI device\n");
		return err;
	}

	err = pci_request_regions(pdev, DRV_MODULE_NAME);
	if (err) {
		dev_err(dev, "Cannot obtain PCI resources\n");
		goto err_disable_pdev;
	}

	pci_set_master(pdev);

	irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
	if (irq < 0)
		dev_err(dev, "failed to get MSI interrupts\n");

	err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
			       IRQF_SHARED, DRV_MODULE_NAME, test);
	if (err) {
		dev_err(dev, "failed to request IRQ %d\n", pdev->irq);
		goto err_disable_msi;
	}

	for (i = 1; i < irq; i++) {
		err = devm_request_irq(dev, pdev->irq + i,
				       pci_endpoint_test_irqhandler,
				       IRQF_SHARED, DRV_MODULE_NAME, test);
		if (err)
			dev_err(dev, "failed to request IRQ %d for MSI %d\n",
				pdev->irq + i, i + 1);
	}

	for (bar = BAR_0; bar <= BAR_5; bar++) {
		base = pci_ioremap_bar(pdev, bar);
		if (!base) {
			dev_err(dev, "failed to read BAR%d\n", bar);
			WARN_ON(bar == test_reg_bar);
		}
		test->bar[bar] = base;
	}

	test->base = test->bar[test_reg_bar];
	if (!test->base) {
		dev_err(dev, "Cannot perform PCI test without BAR%d\n",
			test_reg_bar);
		goto err_iounmap;
	}

	pci_set_drvdata(pdev, test);

	id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
	if (id < 0) {
		dev_err(dev, "unable to get id\n");
		goto err_iounmap;
	}

	snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
	misc_device = &test->miscdev;
	misc_device->minor = MISC_DYNAMIC_MINOR;
	misc_device->name = name;
	misc_device->fops = &pci_endpoint_test_fops,

	err = misc_register(misc_device);
	if (err) {
		dev_err(dev, "failed to register device\n");
		goto err_ida_remove;
	}

	return 0;

err_ida_remove:
	ida_simple_remove(&pci_endpoint_test_ida, id);

err_iounmap:
	for (bar = BAR_0; bar <= BAR_5; bar++) {
		if (test->bar[bar])
			pci_iounmap(pdev, test->bar[bar]);
	}

err_disable_msi:
	pci_disable_msi(pdev);
	pci_release_regions(pdev);

err_disable_pdev:
	pci_disable_device(pdev);

	return err;
}

static void pci_endpoint_test_remove(struct pci_dev *pdev)
{
	int id;
	enum pci_barno bar;
	struct pci_endpoint_test *test = pci_get_drvdata(pdev);
	struct miscdevice *misc_device = &test->miscdev;

	if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
		return;

	misc_deregister(&test->miscdev);
	ida_simple_remove(&pci_endpoint_test_ida, id);
	for (bar = BAR_0; bar <= BAR_5; bar++) {
		if (test->bar[bar])
			pci_iounmap(pdev, test->bar[bar]);
	}
	pci_disable_msi(pdev);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
}

static const struct pci_device_id pci_endpoint_test_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
	{ }
};
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);

static struct pci_driver pci_endpoint_test_driver = {
	.name		= DRV_MODULE_NAME,
	.id_table	= pci_endpoint_test_tbl,
	.probe		= pci_endpoint_test_probe,
	.remove		= pci_endpoint_test_remove,
};
module_pci_driver(pci_endpoint_test_driver);

MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2c156ac7 KVA	1	/**
	2	* Host side test driver to test endpoint functionality
	3	*
	4	* Copyright (C) 2017 Texas Instruments
	5	* Author: Kishon Vijay Abraham I <kishon@ti.com>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 of
	9	* the License as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/crc32.h>
	21	#include <linux/delay.h>
	22	#include <linux/fs.h>
	23	#include <linux/io.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/irq.h>
	26	#include <linux/miscdevice.h>
	27	#include <linux/module.h>
	28	#include <linux/mutex.h>
	29	#include <linux/random.h>
	30	#include <linux/slab.h>
	31	#include <linux/pci.h>
	32	#include <linux/pci_ids.h>
	33
	34	#include <linux/pci_regs.h>
	35
	36	#include <uapi/linux/pcitest.h>
	37
	38	#define DRV_MODULE_NAME "pci-endpoint-test"
	39
	40	#define PCI_ENDPOINT_TEST_MAGIC 0x0
	41
	42	#define PCI_ENDPOINT_TEST_COMMAND 0x4
	43	#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
	44	#define COMMAND_RAISE_MSI_IRQ BIT(1)
	45	#define MSI_NUMBER_SHIFT 2
	46	/* 6 bits for MSI number */
	47	#define COMMAND_READ BIT(8)
	48	#define COMMAND_WRITE BIT(9)
	49	#define COMMAND_COPY BIT(10)
	50
	51	#define PCI_ENDPOINT_TEST_STATUS 0x8
	52	#define STATUS_READ_SUCCESS BIT(0)
	53	#define STATUS_READ_FAIL BIT(1)
	54	#define STATUS_WRITE_SUCCESS BIT(2)
	55	#define STATUS_WRITE_FAIL BIT(3)
	56	#define STATUS_COPY_SUCCESS BIT(4)
	57	#define STATUS_COPY_FAIL BIT(5)
	58	#define STATUS_IRQ_RAISED BIT(6)
	59	#define STATUS_SRC_ADDR_INVALID BIT(7)
	60	#define STATUS_DST_ADDR_INVALID BIT(8)
	61
	62	#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc
	63	#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
	64
65	#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
66	#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
67
68	#define PCI_ENDPOINT_TEST_SIZE 0x1c
69	#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
70
71	static DEFINE_IDA(pci_endpoint_test_ida);
72
73	#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
74	miscdev)
75	enum pci_barno {
76	BAR_0,
77	BAR_1,
78	BAR_2,
79	BAR_3,
80	BAR_4,
81	BAR_5,
82	};
83
84	struct pci_endpoint_test {
85	struct pci_dev *pdev;
86	void __iomem *base;
87	void __iomem *bar[6];
88	struct completion irq_raised;
89	int last_irq;
90	/* mutex to protect the ioctls */
91	struct mutex mutex;
92	struct miscdevice miscdev;
834b9051	93	enum pci_barno test_reg_bar;
2c156ac7 KVA	94	};
2c156ac7 KVA	95
834b9051 KVA	96	struct pci_endpoint_test_data {
	97	enum pci_barno test_reg_bar;
	98	};
	99
	100	static int bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
2c156ac7 KVA	101
	102	static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
	103	u32 offset)
	104	{
	105	return readl(test->base + offset);
	106	}
	107
	108	static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
	109	u32 offset, u32 value)
	110	{
	111	writel(value, test->base + offset);
	112	}
	113
	114	static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
	115	int bar, int offset)
	116	{
	117	return readl(test->bar[bar] + offset);
	118	}
	119
	120	static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
	121	int bar, u32 offset, u32 value)
	122	{
	123	writel(value, test->bar[bar] + offset);
	124	}
	125
	126	static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
	127	{
	128	struct pci_endpoint_test *test = dev_id;
	129	u32 reg;
	130
	131	reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
	132	if (reg & STATUS_IRQ_RAISED) {
	133	test->last_irq = irq;
	134	complete(&test->irq_raised);
	135	reg &= ~STATUS_IRQ_RAISED;
	136	}
	137	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
	138	reg);
	139
	140	return IRQ_HANDLED;
	141	}
	142
	143	static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
	144	enum pci_barno barno)
	145	{
	146	int j;
	147	u32 val;
	148	int size;
	149
	150	if (!test->bar[barno])
	151	return false;
	152
	153	size = bar_size[barno];
	154
834b9051 KVA	155	if (barno == test->test_reg_bar)
	156	size = 0x4;
	157
2c156ac7 KVA	158	for (j = 0; j < size; j += 4)
	159	pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
	160
	161	for (j = 0; j < size; j += 4) {
	162	val = pci_endpoint_test_bar_readl(test, barno, j);
	163	if (val != 0xA0A0A0A0)
	164	return false;
	165	}
	166
	167	return true;
	168	}
	169
	170	static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
	171	{
	172	u32 val;
	173
	174	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
	175	COMMAND_RAISE_LEGACY_IRQ);
	176	val = wait_for_completion_timeout(&test->irq_raised,
	177	msecs_to_jiffies(1000));
	178	if (!val)
	179	return false;
	180
	181	return true;
	182	}
	183
	184	static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
	185	u8 msi_num)
	186	{
	187	u32 val;
	188	struct pci_dev *pdev = test->pdev;
	189
	190	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
	191	msi_num << MSI_NUMBER_SHIFT \|
	192	COMMAND_RAISE_MSI_IRQ);
	193	val = wait_for_completion_timeout(&test->irq_raised,
	194	msecs_to_jiffies(1000));
	195	if (!val)
	196	return false;
	197
	198	if (test->last_irq - pdev->irq == msi_num - 1)
	199	return true;
	200
	201	return false;
	202	}
	203
	204	static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
	205	{
	206	bool ret = false;
	207	void *src_addr;
	208	void *dst_addr;
	209	dma_addr_t src_phys_addr;
	210	dma_addr_t dst_phys_addr;
	211	struct pci_dev *pdev = test->pdev;
	212	struct device *dev = &pdev->dev;
	213	u32 src_crc32;
	214	u32 dst_crc32;
	215
	216	src_addr = dma_alloc_coherent(dev, size, &src_phys_addr, GFP_KERNEL);
	217	if (!src_addr) {
	218	dev_err(dev, "failed to allocate source buffer\n");
	219	ret = false;
	220	goto err;
	221	}
222
223	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
224	lower_32_bits(src_phys_addr));
225
226	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
227	upper_32_bits(src_phys_addr));
228
229	get_random_bytes(src_addr, size);
230	src_crc32 = crc32_le(~0, src_addr, size);
231
232	dst_addr = dma_alloc_coherent(dev, size, &dst_phys_addr, GFP_KERNEL);
233	if (!dst_addr) {
234	dev_err(dev, "failed to allocate destination address\n");
235	ret = false;
236	goto err_src_addr;
237	}
238
239	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
240	lower_32_bits(dst_phys_addr));
241	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
242	upper_32_bits(dst_phys_addr));
243
244	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
245	size);
246
247	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
248	1 << MSI_NUMBER_SHIFT \| COMMAND_COPY);
249
250	wait_for_completion(&test->irq_raised);
251
252	dst_crc32 = crc32_le(~0, dst_addr, size);
253	if (dst_crc32 == src_crc32)
254	ret = true;
255
256	dma_free_coherent(dev, size, dst_addr, dst_phys_addr);
257
258	err_src_addr:
259	dma_free_coherent(dev, size, src_addr, src_phys_addr);
260
261	err:
262	return ret;
263	}
264
265	static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
266	{
267	bool ret = false;
268	u32 reg;
269	void *addr;
270	dma_addr_t phys_addr;
271	struct pci_dev *pdev = test->pdev;
272	struct device *dev = &pdev->dev;
273	u32 crc32;
274
275	addr = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
276	if (!addr) {
277	dev_err(dev, "failed to allocate address\n");
278	ret = false;
279	goto err;
280	}
281
282	get_random_bytes(addr, size);
283
284	crc32 = crc32_le(~0, addr, size);
285	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
286	crc32);
287
288	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
289	lower_32_bits(phys_addr));
290	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
291	upper_32_bits(phys_addr));
292
293	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
294
295	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
296	1 << MSI_NUMBER_SHIFT \| COMMAND_READ);
297
298	wait_for_completion(&test->irq_raised);
299
300	reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
301	if (reg & STATUS_READ_SUCCESS)
302	ret = true;
303
304	dma_free_coherent(dev, size, addr, phys_addr);
305
306	err:
307	return ret;
308	}
309
310	static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
311	{
312	bool ret = false;
313	void *addr;
314	dma_addr_t phys_addr;
315	struct pci_dev *pdev = test->pdev;
316	struct device *dev = &pdev->dev;
317	u32 crc32;
318
319	addr = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
320	if (!addr) {
321	dev_err(dev, "failed to allocate destination address\n");
322	ret = false;
323	goto err;
324	}
325
326	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
327	lower_32_bits(phys_addr));
328	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
329	upper_32_bits(phys_addr));
330
331	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
332
333	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
334	1 << MSI_NUMBER_SHIFT \| COMMAND_WRITE);
335
336	wait_for_completion(&test->irq_raised);
337
338	crc32 = crc32_le(~0, addr, size);
339	if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
340	ret = true;
341
342	dma_free_coherent(dev, size, addr, phys_addr);
343	err:
344	return ret;
345	}
346
347	static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
348	unsigned long arg)
349	{
350	int ret = -EINVAL;
351	enum pci_barno bar;
352	struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
353
354	mutex_lock(&test->mutex);
355	switch (cmd) {
356	case PCITEST_BAR:
357	bar = arg;
358	if (bar < 0 \|\| bar > 5)
359	goto ret;
360	ret = pci_endpoint_test_bar(test, bar);
361	break;
362	case PCITEST_LEGACY_IRQ:
363	ret = pci_endpoint_test_legacy_irq(test);
364	break;
365	case PCITEST_MSI:
366	ret = pci_endpoint_test_msi_irq(test, arg);
367	break;
368	case PCITEST_WRITE:
369	ret = pci_endpoint_test_write(test, arg);
370	break;
371	case PCITEST_READ:
372	ret = pci_endpoint_test_read(test, arg);
373	break;
374	case PCITEST_COPY:
375	ret = pci_endpoint_test_copy(test, arg);
376	break;
377	}
378
379	ret:
380	mutex_unlock(&test->mutex);
381	return ret;
382	}
383
384	static const struct file_operations pci_endpoint_test_fops = {
385	.owner = THIS_MODULE,
386	.unlocked_ioctl = pci_endpoint_test_ioctl,
387	};
388
389	static int pci_endpoint_test_probe(struct pci_dev *pdev,
390	const struct pci_device_id *ent)
391	{
392	int i;
393	int err;
394	int irq;
395	int id;
396	char name[20];
397	enum pci_barno bar;
398	void __iomem *base;
399	struct device *dev = &pdev->dev;
400	struct pci_endpoint_test *test;
834b9051 KVA	401	struct pci_endpoint_test_data *data;
834b9051 KVA	402	enum pci_barno test_reg_bar = BAR_0;
2c156ac7 KVA	403	struct miscdevice *misc_device;
	404
	405	if (pci_is_bridge(pdev))
	406	return -ENODEV;
	407
	408	test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
	409	if (!test)
	410	return -ENOMEM;
	411
834b9051	412	test->test_reg_bar = 0;
2c156ac7	413	test->pdev = pdev;
834b9051 KVA	414
	415	data = (struct pci_endpoint_test_data *)ent->driver_data;
	416	if (data)
	417	test_reg_bar = data->test_reg_bar;
	418
2c156ac7 KVA	419	init_completion(&test->irq_raised);
	420	mutex_init(&test->mutex);
	421
	422	err = pci_enable_device(pdev);
	423	if (err) {
	424	dev_err(dev, "Cannot enable PCI device\n");
	425	return err;
	426	}
	427
	428	err = pci_request_regions(pdev, DRV_MODULE_NAME);
	429	if (err) {
	430	dev_err(dev, "Cannot obtain PCI resources\n");
	431	goto err_disable_pdev;
	432	}
	433
	434	pci_set_master(pdev);
	435
	436	irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
	437	if (irq < 0)
	438	dev_err(dev, "failed to get MSI interrupts\n");
	439
	440	err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
	441	IRQF_SHARED, DRV_MODULE_NAME, test);
	442	if (err) {
	443	dev_err(dev, "failed to request IRQ %d\n", pdev->irq);
	444	goto err_disable_msi;
	445	}
	446
	447	for (i = 1; i < irq; i++) {
	448	err = devm_request_irq(dev, pdev->irq + i,
	449	pci_endpoint_test_irqhandler,
	450	IRQF_SHARED, DRV_MODULE_NAME, test);
	451	if (err)
	452	dev_err(dev, "failed to request IRQ %d for MSI %d\n",
	453	pdev->irq + i, i + 1);
	454	}
	455
	456	for (bar = BAR_0; bar <= BAR_5; bar++) {
	457	base = pci_ioremap_bar(pdev, bar);
	458	if (!base) {
	459	dev_err(dev, "failed to read BAR%d\n", bar);
834b9051	460	WARN_ON(bar == test_reg_bar);
2c156ac7 KVA	461	}
	462	test->bar[bar] = base;
	463	}
	464
834b9051	465	test->base = test->bar[test_reg_bar];
2c156ac7	466	if (!test->base) {
834b9051 KVA	467	dev_err(dev, "Cannot perform PCI test without BAR%d\n",
834b9051 KVA	468	test_reg_bar);
2c156ac7 KVA	469	goto err_iounmap;
	470	}
	471
	472	pci_set_drvdata(pdev, test);
	473
	474	id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
	475	if (id < 0) {
	476	dev_err(dev, "unable to get id\n");
	477	goto err_iounmap;
	478	}
	479
	480	snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
	481	misc_device = &test->miscdev;
	482	misc_device->minor = MISC_DYNAMIC_MINOR;
	483	misc_device->name = name;
	484	misc_device->fops = &pci_endpoint_test_fops,
	485
	486	err = misc_register(misc_device);
	487	if (err) {
	488	dev_err(dev, "failed to register device\n");
	489	goto err_ida_remove;
	490	}
	491
	492	return 0;
	493
	494	err_ida_remove:
	495	ida_simple_remove(&pci_endpoint_test_ida, id);
	496
	497	err_iounmap:
	498	for (bar = BAR_0; bar <= BAR_5; bar++) {
	499	if (test->bar[bar])
	500	pci_iounmap(pdev, test->bar[bar]);
	501	}
	502
	503	err_disable_msi:
	504	pci_disable_msi(pdev);
	505	pci_release_regions(pdev);
	506
	507	err_disable_pdev:
	508	pci_disable_device(pdev);
	509
	510	return err;
	511	}
	512
	513	static void pci_endpoint_test_remove(struct pci_dev *pdev)
	514	{
	515	int id;
	516	enum pci_barno bar;
	517	struct pci_endpoint_test *test = pci_get_drvdata(pdev);
	518	struct miscdevice *misc_device = &test->miscdev;
	519
	520	if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
	521	return;
	522
	523	misc_deregister(&test->miscdev);
	524	ida_simple_remove(&pci_endpoint_test_ida, id);
	525	for (bar = BAR_0; bar <= BAR_5; bar++) {
	526	if (test->bar[bar])
	527	pci_iounmap(pdev, test->bar[bar]);
	528	}
	529	pci_disable_msi(pdev);
	530	pci_release_regions(pdev);
	531	pci_disable_device(pdev);
	532	}
533
534	static const struct pci_device_id pci_endpoint_test_tbl[] = {
535	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
536	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
537	{ }
538	};
539	MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
540
541	static struct pci_driver pci_endpoint_test_driver = {
542	.name = DRV_MODULE_NAME,
543	.id_table = pci_endpoint_test_tbl,
544	.probe = pci_endpoint_test_probe,
545	.remove = pci_endpoint_test_remove,
546	};
547	module_pci_driver(pci_endpoint_test_driver);
548
549	MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
550	MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
551	MODULE_LICENSE("GPL v2");