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65dbf343 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver |
65dbf343 AV |
3 | * |
4 | * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved | |
5 | * | |
6 | * Copyright (C) 2006 Malcolm Noyes | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
99eeb8df | 14 | This is the AT91 MCI driver that has been tested with both MMC cards |
65dbf343 AV |
15 | and SD-cards. Boards that support write protect are now supported. |
16 | The CCAT91SBC001 board does not support SD cards. | |
17 | ||
18 | The three entry points are at91_mci_request, at91_mci_set_ios | |
19 | and at91_mci_get_ro. | |
20 | ||
21 | SET IOS | |
22 | This configures the device to put it into the correct mode and clock speed | |
23 | required. | |
24 | ||
25 | MCI REQUEST | |
26 | MCI request processes the commands sent in the mmc_request structure. This | |
27 | can consist of a processing command and a stop command in the case of | |
28 | multiple block transfers. | |
29 | ||
30 | There are three main types of request, commands, reads and writes. | |
31 | ||
32 | Commands are straight forward. The command is submitted to the controller and | |
33 | the request function returns. When the controller generates an interrupt to indicate | |
34 | the command is finished, the response to the command are read and the mmc_request_done | |
35 | function called to end the request. | |
36 | ||
37 | Reads and writes work in a similar manner to normal commands but involve the PDC (DMA) | |
38 | controller to manage the transfers. | |
39 | ||
40 | A read is done from the controller directly to the scatterlist passed in from the request. | |
99eeb8df AV |
41 | Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte |
42 | swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug. | |
65dbf343 AV |
43 | |
44 | The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY | |
45 | ||
46 | A write is slightly different in that the bytes to write are read from the scatterlist | |
47 | into a dma memory buffer (this is in case the source buffer should be read only). The | |
48 | entire write buffer is then done from this single dma memory buffer. | |
49 | ||
50 | The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY | |
51 | ||
52 | GET RO | |
53 | Gets the status of the write protect pin, if available. | |
54 | */ | |
55 | ||
65dbf343 AV |
56 | #include <linux/module.h> |
57 | #include <linux/moduleparam.h> | |
58 | #include <linux/init.h> | |
59 | #include <linux/ioport.h> | |
60 | #include <linux/platform_device.h> | |
61 | #include <linux/interrupt.h> | |
62 | #include <linux/blkdev.h> | |
63 | #include <linux/delay.h> | |
64 | #include <linux/err.h> | |
65 | #include <linux/dma-mapping.h> | |
66 | #include <linux/clk.h> | |
93a3ddc2 | 67 | #include <linux/atmel_pdc.h> |
65dbf343 AV |
68 | |
69 | #include <linux/mmc/host.h> | |
65dbf343 AV |
70 | |
71 | #include <asm/io.h> | |
72 | #include <asm/irq.h> | |
6e996ee8 DB |
73 | #include <asm/gpio.h> |
74 | ||
65dbf343 AV |
75 | #include <asm/mach/mmc.h> |
76 | #include <asm/arch/board.h> | |
99eeb8df | 77 | #include <asm/arch/cpu.h> |
55d8baee | 78 | #include <asm/arch/at91_mci.h> |
65dbf343 AV |
79 | |
80 | #define DRIVER_NAME "at91_mci" | |
81 | ||
df05a303 AV |
82 | #define FL_SENT_COMMAND (1 << 0) |
83 | #define FL_SENT_STOP (1 << 1) | |
65dbf343 | 84 | |
df05a303 AV |
85 | #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ |
86 | | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ | |
37b758e8 | 87 | | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) |
65dbf343 | 88 | |
e0b19b83 AV |
89 | #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg)) |
90 | #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg)) | |
65dbf343 | 91 | |
65dbf343 AV |
92 | |
93 | /* | |
94 | * Low level type for this driver | |
95 | */ | |
96 | struct at91mci_host | |
97 | { | |
98 | struct mmc_host *mmc; | |
99 | struct mmc_command *cmd; | |
100 | struct mmc_request *request; | |
101 | ||
e0b19b83 | 102 | void __iomem *baseaddr; |
17ea0595 | 103 | int irq; |
e0b19b83 | 104 | |
65dbf343 AV |
105 | struct at91_mmc_data *board; |
106 | int present; | |
107 | ||
3dd3b039 AV |
108 | struct clk *mci_clk; |
109 | ||
65dbf343 AV |
110 | /* |
111 | * Flag indicating when the command has been sent. This is used to | |
112 | * work out whether or not to send the stop | |
113 | */ | |
114 | unsigned int flags; | |
115 | /* flag for current bus settings */ | |
116 | u32 bus_mode; | |
117 | ||
118 | /* DMA buffer used for transmitting */ | |
119 | unsigned int* buffer; | |
120 | dma_addr_t physical_address; | |
121 | unsigned int total_length; | |
122 | ||
123 | /* Latest in the scatterlist that has been enabled for transfer, but not freed */ | |
124 | int in_use_index; | |
125 | ||
126 | /* Latest in the scatterlist that has been enabled for transfer */ | |
127 | int transfer_index; | |
e181dce8 MP |
128 | |
129 | /* Timer for timeouts */ | |
130 | struct timer_list timer; | |
65dbf343 AV |
131 | }; |
132 | ||
c5a89c6c MP |
133 | /* |
134 | * Reset the controller and restore most of the state | |
135 | */ | |
136 | static void at91_reset_host(struct at91mci_host *host) | |
137 | { | |
138 | unsigned long flags; | |
139 | u32 mr; | |
140 | u32 sdcr; | |
141 | u32 dtor; | |
142 | u32 imr; | |
143 | ||
144 | local_irq_save(flags); | |
145 | imr = at91_mci_read(host, AT91_MCI_IMR); | |
146 | ||
147 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); | |
148 | ||
149 | /* save current state */ | |
150 | mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; | |
151 | sdcr = at91_mci_read(host, AT91_MCI_SDCR); | |
152 | dtor = at91_mci_read(host, AT91_MCI_DTOR); | |
153 | ||
154 | /* reset the controller */ | |
155 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); | |
156 | ||
157 | /* restore state */ | |
158 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); | |
159 | at91_mci_write(host, AT91_MCI_MR, mr); | |
160 | at91_mci_write(host, AT91_MCI_SDCR, sdcr); | |
161 | at91_mci_write(host, AT91_MCI_DTOR, dtor); | |
162 | at91_mci_write(host, AT91_MCI_IER, imr); | |
163 | ||
164 | /* make sure sdio interrupts will fire */ | |
165 | at91_mci_read(host, AT91_MCI_SR); | |
166 | ||
167 | local_irq_restore(flags); | |
168 | } | |
169 | ||
e181dce8 MP |
170 | static void at91_timeout_timer(unsigned long data) |
171 | { | |
172 | struct at91mci_host *host; | |
173 | ||
174 | host = (struct at91mci_host *)data; | |
175 | ||
176 | if (host->request) { | |
177 | dev_err(host->mmc->parent, "Timeout waiting end of packet\n"); | |
178 | ||
179 | if (host->cmd && host->cmd->data) { | |
180 | host->cmd->data->error = -ETIMEDOUT; | |
181 | } else { | |
182 | if (host->cmd) | |
183 | host->cmd->error = -ETIMEDOUT; | |
184 | else | |
185 | host->request->cmd->error = -ETIMEDOUT; | |
186 | } | |
187 | ||
c5a89c6c | 188 | at91_reset_host(host); |
e181dce8 MP |
189 | mmc_request_done(host->mmc, host->request); |
190 | } | |
191 | } | |
192 | ||
65dbf343 AV |
193 | /* |
194 | * Copy from sg to a dma block - used for transfers | |
195 | */ | |
e8d04d3d | 196 | static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data) |
65dbf343 AV |
197 | { |
198 | unsigned int len, i, size; | |
199 | unsigned *dmabuf = host->buffer; | |
200 | ||
201 | size = host->total_length; | |
202 | len = data->sg_len; | |
203 | ||
204 | /* | |
205 | * Just loop through all entries. Size might not | |
206 | * be the entire list though so make sure that | |
207 | * we do not transfer too much. | |
208 | */ | |
209 | for (i = 0; i < len; i++) { | |
210 | struct scatterlist *sg; | |
211 | int amount; | |
65dbf343 AV |
212 | unsigned int *sgbuffer; |
213 | ||
214 | sg = &data->sg[i]; | |
215 | ||
45711f1a | 216 | sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
65dbf343 AV |
217 | amount = min(size, sg->length); |
218 | size -= amount; | |
65dbf343 | 219 | |
99eeb8df AV |
220 | if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ |
221 | int index; | |
222 | ||
223 | for (index = 0; index < (amount / 4); index++) | |
224 | *dmabuf++ = swab32(sgbuffer[index]); | |
225 | } | |
226 | else | |
227 | memcpy(dmabuf, sgbuffer, amount); | |
65dbf343 AV |
228 | |
229 | kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ); | |
230 | ||
231 | if (size == 0) | |
232 | break; | |
233 | } | |
234 | ||
235 | /* | |
236 | * Check that we didn't get a request to transfer | |
237 | * more data than can fit into the SG list. | |
238 | */ | |
239 | BUG_ON(size != 0); | |
240 | } | |
241 | ||
242 | /* | |
243 | * Prepare a dma read | |
244 | */ | |
e8d04d3d | 245 | static void at91_mci_pre_dma_read(struct at91mci_host *host) |
65dbf343 AV |
246 | { |
247 | int i; | |
248 | struct scatterlist *sg; | |
249 | struct mmc_command *cmd; | |
250 | struct mmc_data *data; | |
251 | ||
b44fb7a0 | 252 | pr_debug("pre dma read\n"); |
65dbf343 AV |
253 | |
254 | cmd = host->cmd; | |
255 | if (!cmd) { | |
b44fb7a0 | 256 | pr_debug("no command\n"); |
65dbf343 AV |
257 | return; |
258 | } | |
259 | ||
260 | data = cmd->data; | |
261 | if (!data) { | |
b44fb7a0 | 262 | pr_debug("no data\n"); |
65dbf343 AV |
263 | return; |
264 | } | |
265 | ||
266 | for (i = 0; i < 2; i++) { | |
267 | /* nothing left to transfer */ | |
268 | if (host->transfer_index >= data->sg_len) { | |
b44fb7a0 | 269 | pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index); |
65dbf343 AV |
270 | break; |
271 | } | |
272 | ||
273 | /* Check to see if this needs filling */ | |
274 | if (i == 0) { | |
93a3ddc2 | 275 | if (at91_mci_read(host, ATMEL_PDC_RCR) != 0) { |
b44fb7a0 | 276 | pr_debug("Transfer active in current\n"); |
65dbf343 AV |
277 | continue; |
278 | } | |
279 | } | |
280 | else { | |
93a3ddc2 | 281 | if (at91_mci_read(host, ATMEL_PDC_RNCR) != 0) { |
b44fb7a0 | 282 | pr_debug("Transfer active in next\n"); |
65dbf343 AV |
283 | continue; |
284 | } | |
285 | } | |
286 | ||
287 | /* Setup the next transfer */ | |
b44fb7a0 | 288 | pr_debug("Using transfer index %d\n", host->transfer_index); |
65dbf343 AV |
289 | |
290 | sg = &data->sg[host->transfer_index++]; | |
b44fb7a0 | 291 | pr_debug("sg = %p\n", sg); |
65dbf343 | 292 | |
45711f1a | 293 | sg->dma_address = dma_map_page(NULL, sg_page(sg), sg->offset, sg->length, DMA_FROM_DEVICE); |
65dbf343 | 294 | |
b44fb7a0 | 295 | pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length); |
65dbf343 AV |
296 | |
297 | if (i == 0) { | |
93a3ddc2 | 298 | at91_mci_write(host, ATMEL_PDC_RPR, sg->dma_address); |
80f92546 | 299 | at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? sg->length : sg->length / 4); |
65dbf343 AV |
300 | } |
301 | else { | |
93a3ddc2 | 302 | at91_mci_write(host, ATMEL_PDC_RNPR, sg->dma_address); |
80f92546 | 303 | at91_mci_write(host, ATMEL_PDC_RNCR, (data->blksz & 0x3) ? sg->length : sg->length / 4); |
65dbf343 AV |
304 | } |
305 | } | |
306 | ||
b44fb7a0 | 307 | pr_debug("pre dma read done\n"); |
65dbf343 AV |
308 | } |
309 | ||
310 | /* | |
311 | * Handle after a dma read | |
312 | */ | |
e8d04d3d | 313 | static void at91_mci_post_dma_read(struct at91mci_host *host) |
65dbf343 AV |
314 | { |
315 | struct mmc_command *cmd; | |
316 | struct mmc_data *data; | |
317 | ||
b44fb7a0 | 318 | pr_debug("post dma read\n"); |
65dbf343 AV |
319 | |
320 | cmd = host->cmd; | |
321 | if (!cmd) { | |
b44fb7a0 | 322 | pr_debug("no command\n"); |
65dbf343 AV |
323 | return; |
324 | } | |
325 | ||
326 | data = cmd->data; | |
327 | if (!data) { | |
b44fb7a0 | 328 | pr_debug("no data\n"); |
65dbf343 AV |
329 | return; |
330 | } | |
331 | ||
332 | while (host->in_use_index < host->transfer_index) { | |
65dbf343 AV |
333 | struct scatterlist *sg; |
334 | ||
b44fb7a0 | 335 | pr_debug("finishing index %d\n", host->in_use_index); |
65dbf343 AV |
336 | |
337 | sg = &data->sg[host->in_use_index++]; | |
338 | ||
b44fb7a0 | 339 | pr_debug("Unmapping page %08X\n", sg->dma_address); |
65dbf343 AV |
340 | |
341 | dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE); | |
342 | ||
99eeb8df | 343 | if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ |
ed99c541 | 344 | unsigned int *buffer; |
99eeb8df | 345 | int index; |
65dbf343 | 346 | |
ed99c541 | 347 | /* Swap the contents of the buffer */ |
45711f1a | 348 | buffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
ed99c541 NF |
349 | pr_debug("buffer = %p, length = %d\n", buffer, sg->length); |
350 | ||
99eeb8df AV |
351 | for (index = 0; index < (sg->length / 4); index++) |
352 | buffer[index] = swab32(buffer[index]); | |
ed99c541 NF |
353 | |
354 | kunmap_atomic(buffer, KM_BIO_SRC_IRQ); | |
65dbf343 | 355 | } |
99eeb8df | 356 | |
45711f1a | 357 | flush_dcache_page(sg_page(sg)); |
4ac24a87 NF |
358 | |
359 | data->bytes_xfered += sg->length; | |
65dbf343 AV |
360 | } |
361 | ||
362 | /* Is there another transfer to trigger? */ | |
363 | if (host->transfer_index < data->sg_len) | |
e8d04d3d | 364 | at91_mci_pre_dma_read(host); |
65dbf343 | 365 | else { |
ed99c541 | 366 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX); |
e0b19b83 | 367 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF); |
65dbf343 AV |
368 | } |
369 | ||
b44fb7a0 | 370 | pr_debug("post dma read done\n"); |
65dbf343 AV |
371 | } |
372 | ||
373 | /* | |
374 | * Handle transmitted data | |
375 | */ | |
376 | static void at91_mci_handle_transmitted(struct at91mci_host *host) | |
377 | { | |
378 | struct mmc_command *cmd; | |
379 | struct mmc_data *data; | |
380 | ||
b44fb7a0 | 381 | pr_debug("Handling the transmit\n"); |
65dbf343 AV |
382 | |
383 | /* Disable the transfer */ | |
93a3ddc2 | 384 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
65dbf343 AV |
385 | |
386 | /* Now wait for cmd ready */ | |
e0b19b83 | 387 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE); |
65dbf343 AV |
388 | |
389 | cmd = host->cmd; | |
390 | if (!cmd) return; | |
391 | ||
392 | data = cmd->data; | |
393 | if (!data) return; | |
394 | ||
be0192aa | 395 | if (cmd->data->blocks > 1) { |
ed99c541 NF |
396 | pr_debug("multiple write : wait for BLKE...\n"); |
397 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE); | |
398 | } else | |
399 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
4ac24a87 NF |
400 | } |
401 | ||
402 | /* | |
403 | * Update bytes tranfered count during a write operation | |
404 | */ | |
405 | static void at91_mci_update_bytes_xfered(struct at91mci_host *host) | |
406 | { | |
407 | struct mmc_data *data; | |
ed99c541 | 408 | |
4ac24a87 NF |
409 | /* always deal with the effective request (and not the current cmd) */ |
410 | ||
411 | if (host->request->cmd && host->request->cmd->error != 0) | |
412 | return; | |
413 | ||
414 | if (host->request->data) { | |
415 | data = host->request->data; | |
416 | if (data->flags & MMC_DATA_WRITE) { | |
417 | /* card is in IDLE mode now */ | |
418 | pr_debug("-> bytes_xfered %d, total_length = %d\n", | |
419 | data->bytes_xfered, host->total_length); | |
420 | data->bytes_xfered = host->total_length; | |
421 | } | |
422 | } | |
65dbf343 AV |
423 | } |
424 | ||
4ac24a87 | 425 | |
ed99c541 NF |
426 | /*Handle after command sent ready*/ |
427 | static int at91_mci_handle_cmdrdy(struct at91mci_host *host) | |
428 | { | |
429 | if (!host->cmd) | |
430 | return 1; | |
431 | else if (!host->cmd->data) { | |
432 | if (host->flags & FL_SENT_STOP) { | |
433 | /*After multi block write, we must wait for NOTBUSY*/ | |
434 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
435 | } else return 1; | |
436 | } else if (host->cmd->data->flags & MMC_DATA_WRITE) { | |
437 | /*After sendding multi-block-write command, start DMA transfer*/ | |
4ac24a87 | 438 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); |
ed99c541 NF |
439 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); |
440 | } | |
441 | ||
442 | /* command not completed, have to wait */ | |
443 | return 0; | |
444 | } | |
445 | ||
446 | ||
65dbf343 AV |
447 | /* |
448 | * Enable the controller | |
449 | */ | |
e0b19b83 | 450 | static void at91_mci_enable(struct at91mci_host *host) |
65dbf343 | 451 | { |
ed99c541 NF |
452 | unsigned int mr; |
453 | ||
e0b19b83 | 454 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); |
f3a8efa9 | 455 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); |
e0b19b83 | 456 | at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); |
ed99c541 NF |
457 | mr = AT91_MCI_PDCMODE | 0x34a; |
458 | ||
459 | if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) | |
460 | mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; | |
461 | ||
462 | at91_mci_write(host, AT91_MCI_MR, mr); | |
99eeb8df AV |
463 | |
464 | /* use Slot A or B (only one at same time) */ | |
465 | at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b); | |
65dbf343 AV |
466 | } |
467 | ||
468 | /* | |
469 | * Disable the controller | |
470 | */ | |
e0b19b83 | 471 | static void at91_mci_disable(struct at91mci_host *host) |
65dbf343 | 472 | { |
e0b19b83 | 473 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); |
65dbf343 AV |
474 | } |
475 | ||
476 | /* | |
477 | * Send a command | |
65dbf343 | 478 | */ |
ed99c541 | 479 | static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd) |
65dbf343 AV |
480 | { |
481 | unsigned int cmdr, mr; | |
482 | unsigned int block_length; | |
483 | struct mmc_data *data = cmd->data; | |
484 | ||
485 | unsigned int blocks; | |
486 | unsigned int ier = 0; | |
487 | ||
488 | host->cmd = cmd; | |
489 | ||
ed99c541 | 490 | /* Needed for leaving busy state before CMD1 */ |
e0b19b83 | 491 | if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) { |
b44fb7a0 | 492 | pr_debug("Clearing timeout\n"); |
e0b19b83 AV |
493 | at91_mci_write(host, AT91_MCI_ARGR, 0); |
494 | at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD); | |
495 | while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) { | |
65dbf343 | 496 | /* spin */ |
e0b19b83 | 497 | pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR)); |
65dbf343 AV |
498 | } |
499 | } | |
ed99c541 | 500 | |
65dbf343 AV |
501 | cmdr = cmd->opcode; |
502 | ||
503 | if (mmc_resp_type(cmd) == MMC_RSP_NONE) | |
504 | cmdr |= AT91_MCI_RSPTYP_NONE; | |
505 | else { | |
506 | /* if a response is expected then allow maximum response latancy */ | |
507 | cmdr |= AT91_MCI_MAXLAT; | |
508 | /* set 136 bit response for R2, 48 bit response otherwise */ | |
509 | if (mmc_resp_type(cmd) == MMC_RSP_R2) | |
510 | cmdr |= AT91_MCI_RSPTYP_136; | |
511 | else | |
512 | cmdr |= AT91_MCI_RSPTYP_48; | |
513 | } | |
514 | ||
515 | if (data) { | |
1d4de9ed | 516 | |
80f92546 | 517 | if ( cpu_is_at91rm9200() && (data->blksz & 0x3) ) { |
1d4de9ed MP |
518 | pr_debug("Unsupported block size\n"); |
519 | cmd->error = -EINVAL; | |
520 | mmc_request_done(host->mmc, host->request); | |
521 | return; | |
522 | } | |
523 | ||
a3fd4a1b | 524 | block_length = data->blksz; |
65dbf343 AV |
525 | blocks = data->blocks; |
526 | ||
527 | /* always set data start - also set direction flag for read */ | |
528 | if (data->flags & MMC_DATA_READ) | |
529 | cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); | |
530 | else if (data->flags & MMC_DATA_WRITE) | |
531 | cmdr |= AT91_MCI_TRCMD_START; | |
532 | ||
533 | if (data->flags & MMC_DATA_STREAM) | |
534 | cmdr |= AT91_MCI_TRTYP_STREAM; | |
be0192aa | 535 | if (data->blocks > 1) |
65dbf343 AV |
536 | cmdr |= AT91_MCI_TRTYP_MULTIPLE; |
537 | } | |
538 | else { | |
539 | block_length = 0; | |
540 | blocks = 0; | |
541 | } | |
542 | ||
b6cedb38 | 543 | if (host->flags & FL_SENT_STOP) |
65dbf343 AV |
544 | cmdr |= AT91_MCI_TRCMD_STOP; |
545 | ||
546 | if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
547 | cmdr |= AT91_MCI_OPDCMD; | |
548 | ||
549 | /* | |
550 | * Set the arguments and send the command | |
551 | */ | |
f3a8efa9 | 552 | pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", |
e0b19b83 | 553 | cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR)); |
65dbf343 AV |
554 | |
555 | if (!data) { | |
93a3ddc2 AV |
556 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS); |
557 | at91_mci_write(host, ATMEL_PDC_RPR, 0); | |
558 | at91_mci_write(host, ATMEL_PDC_RCR, 0); | |
559 | at91_mci_write(host, ATMEL_PDC_RNPR, 0); | |
560 | at91_mci_write(host, ATMEL_PDC_RNCR, 0); | |
561 | at91_mci_write(host, ATMEL_PDC_TPR, 0); | |
562 | at91_mci_write(host, ATMEL_PDC_TCR, 0); | |
563 | at91_mci_write(host, ATMEL_PDC_TNPR, 0); | |
564 | at91_mci_write(host, ATMEL_PDC_TNCR, 0); | |
ed99c541 NF |
565 | ier = AT91_MCI_CMDRDY; |
566 | } else { | |
567 | /* zero block length and PDC mode */ | |
568 | mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; | |
80f92546 MP |
569 | mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0; |
570 | mr |= (block_length << 16); | |
571 | mr |= AT91_MCI_PDCMODE; | |
572 | at91_mci_write(host, AT91_MCI_MR, mr); | |
e0b19b83 | 573 | |
c5a89c6c MP |
574 | if (!cpu_is_at91rm9200()) |
575 | at91_mci_write(host, AT91_MCI_BLKR, | |
576 | AT91_MCI_BLKR_BCNT(blocks) | | |
577 | AT91_MCI_BLKR_BLKLEN(block_length)); | |
578 | ||
ed99c541 NF |
579 | /* |
580 | * Disable the PDC controller | |
581 | */ | |
582 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); | |
65dbf343 | 583 | |
ed99c541 NF |
584 | if (cmdr & AT91_MCI_TRCMD_START) { |
585 | data->bytes_xfered = 0; | |
586 | host->transfer_index = 0; | |
587 | host->in_use_index = 0; | |
588 | if (cmdr & AT91_MCI_TRDIR) { | |
589 | /* | |
590 | * Handle a read | |
591 | */ | |
592 | host->buffer = NULL; | |
593 | host->total_length = 0; | |
594 | ||
595 | at91_mci_pre_dma_read(host); | |
596 | ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; | |
597 | } | |
598 | else { | |
599 | /* | |
600 | * Handle a write | |
601 | */ | |
602 | host->total_length = block_length * blocks; | |
603 | host->buffer = dma_alloc_coherent(NULL, | |
604 | host->total_length, | |
605 | &host->physical_address, GFP_KERNEL); | |
606 | ||
607 | at91_mci_sg_to_dma(host, data); | |
608 | ||
609 | pr_debug("Transmitting %d bytes\n", host->total_length); | |
610 | ||
611 | at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address); | |
80f92546 MP |
612 | at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ? |
613 | host->total_length : host->total_length / 4); | |
614 | ||
ed99c541 NF |
615 | ier = AT91_MCI_CMDRDY; |
616 | } | |
65dbf343 AV |
617 | } |
618 | } | |
619 | ||
620 | /* | |
621 | * Send the command and then enable the PDC - not the other way round as | |
622 | * the data sheet says | |
623 | */ | |
624 | ||
e0b19b83 AV |
625 | at91_mci_write(host, AT91_MCI_ARGR, cmd->arg); |
626 | at91_mci_write(host, AT91_MCI_CMDR, cmdr); | |
65dbf343 AV |
627 | |
628 | if (cmdr & AT91_MCI_TRCMD_START) { | |
629 | if (cmdr & AT91_MCI_TRDIR) | |
93a3ddc2 | 630 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); |
65dbf343 | 631 | } |
65dbf343 | 632 | |
ed99c541 | 633 | /* Enable selected interrupts */ |
df05a303 | 634 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier); |
65dbf343 AV |
635 | } |
636 | ||
637 | /* | |
638 | * Process the next step in the request | |
639 | */ | |
e8d04d3d | 640 | static void at91_mci_process_next(struct at91mci_host *host) |
65dbf343 AV |
641 | { |
642 | if (!(host->flags & FL_SENT_COMMAND)) { | |
643 | host->flags |= FL_SENT_COMMAND; | |
ed99c541 | 644 | at91_mci_send_command(host, host->request->cmd); |
65dbf343 AV |
645 | } |
646 | else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) { | |
647 | host->flags |= FL_SENT_STOP; | |
ed99c541 | 648 | at91_mci_send_command(host, host->request->stop); |
e181dce8 MP |
649 | } else { |
650 | del_timer(&host->timer); | |
c5a89c6c MP |
651 | /* the at91rm9200 mci controller hangs after some transfers, |
652 | * and the workaround is to reset it after each transfer. | |
653 | */ | |
654 | if (cpu_is_at91rm9200()) | |
655 | at91_reset_host(host); | |
65dbf343 | 656 | mmc_request_done(host->mmc, host->request); |
e181dce8 | 657 | } |
65dbf343 AV |
658 | } |
659 | ||
660 | /* | |
661 | * Handle a command that has been completed | |
662 | */ | |
ba7deeed | 663 | static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status) |
65dbf343 AV |
664 | { |
665 | struct mmc_command *cmd = host->cmd; | |
fa1fe010 | 666 | struct mmc_data *data = cmd->data; |
65dbf343 | 667 | |
7a6588ba | 668 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
65dbf343 | 669 | |
e0b19b83 AV |
670 | cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0)); |
671 | cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1)); | |
672 | cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2)); | |
673 | cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3)); | |
65dbf343 AV |
674 | |
675 | if (host->buffer) { | |
676 | dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address); | |
677 | host->buffer = NULL; | |
678 | } | |
679 | ||
ba7deeed NF |
680 | pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n", |
681 | status, at91_mci_read(host, AT91_MCI_SR), | |
682 | cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); | |
65dbf343 | 683 | |
9e3866b5 | 684 | if (status & AT91_MCI_ERRORS) { |
b6cedb38 | 685 | if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) { |
17b0429d | 686 | cmd->error = 0; |
65dbf343 AV |
687 | } |
688 | else { | |
fa1fe010 NF |
689 | if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) { |
690 | if (data) { | |
691 | if (status & AT91_MCI_DTOE) | |
692 | data->error = -ETIMEDOUT; | |
693 | else if (status & AT91_MCI_DCRCE) | |
694 | data->error = -EILSEQ; | |
695 | } | |
696 | } else { | |
697 | if (status & AT91_MCI_RTOE) | |
698 | cmd->error = -ETIMEDOUT; | |
699 | else if (status & AT91_MCI_RCRCE) | |
700 | cmd->error = -EILSEQ; | |
701 | else | |
702 | cmd->error = -EIO; | |
703 | } | |
65dbf343 | 704 | |
fa1fe010 NF |
705 | pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n", |
706 | cmd->error, data ? data->error : 0, | |
707 | cmd->opcode, cmd->retries); | |
65dbf343 AV |
708 | } |
709 | } | |
710 | else | |
17b0429d | 711 | cmd->error = 0; |
65dbf343 | 712 | |
e8d04d3d | 713 | at91_mci_process_next(host); |
65dbf343 AV |
714 | } |
715 | ||
716 | /* | |
717 | * Handle an MMC request | |
718 | */ | |
719 | static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
720 | { | |
721 | struct at91mci_host *host = mmc_priv(mmc); | |
722 | host->request = mrq; | |
723 | host->flags = 0; | |
724 | ||
e181dce8 MP |
725 | mod_timer(&host->timer, jiffies + HZ); |
726 | ||
e8d04d3d | 727 | at91_mci_process_next(host); |
65dbf343 AV |
728 | } |
729 | ||
730 | /* | |
731 | * Set the IOS | |
732 | */ | |
733 | static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
734 | { | |
735 | int clkdiv; | |
736 | struct at91mci_host *host = mmc_priv(mmc); | |
3dd3b039 | 737 | unsigned long at91_master_clock = clk_get_rate(host->mci_clk); |
65dbf343 | 738 | |
b44fb7a0 | 739 | host->bus_mode = ios->bus_mode; |
65dbf343 AV |
740 | |
741 | if (ios->clock == 0) { | |
742 | /* Disable the MCI controller */ | |
e0b19b83 | 743 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS); |
65dbf343 AV |
744 | clkdiv = 0; |
745 | } | |
746 | else { | |
747 | /* Enable the MCI controller */ | |
e0b19b83 | 748 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); |
65dbf343 AV |
749 | |
750 | if ((at91_master_clock % (ios->clock * 2)) == 0) | |
751 | clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; | |
752 | else | |
753 | clkdiv = (at91_master_clock / ios->clock) / 2; | |
754 | ||
b44fb7a0 | 755 | pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv, |
65dbf343 AV |
756 | at91_master_clock / (2 * (clkdiv + 1))); |
757 | } | |
758 | if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) { | |
b44fb7a0 | 759 | pr_debug("MMC: Setting controller bus width to 4\n"); |
e0b19b83 | 760 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS); |
65dbf343 AV |
761 | } |
762 | else { | |
b44fb7a0 | 763 | pr_debug("MMC: Setting controller bus width to 1\n"); |
e0b19b83 | 764 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
65dbf343 AV |
765 | } |
766 | ||
767 | /* Set the clock divider */ | |
e0b19b83 | 768 | at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); |
65dbf343 AV |
769 | |
770 | /* maybe switch power to the card */ | |
b44fb7a0 | 771 | if (host->board->vcc_pin) { |
65dbf343 AV |
772 | switch (ios->power_mode) { |
773 | case MMC_POWER_OFF: | |
6e996ee8 | 774 | gpio_set_value(host->board->vcc_pin, 0); |
65dbf343 AV |
775 | break; |
776 | case MMC_POWER_UP: | |
6e996ee8 | 777 | gpio_set_value(host->board->vcc_pin, 1); |
65dbf343 | 778 | break; |
e5c0ef90 MP |
779 | case MMC_POWER_ON: |
780 | break; | |
781 | default: | |
782 | WARN_ON(1); | |
65dbf343 AV |
783 | } |
784 | } | |
785 | } | |
786 | ||
787 | /* | |
788 | * Handle an interrupt | |
789 | */ | |
7d12e780 | 790 | static irqreturn_t at91_mci_irq(int irq, void *devid) |
65dbf343 AV |
791 | { |
792 | struct at91mci_host *host = devid; | |
793 | int completed = 0; | |
df05a303 | 794 | unsigned int int_status, int_mask; |
65dbf343 | 795 | |
e0b19b83 | 796 | int_status = at91_mci_read(host, AT91_MCI_SR); |
df05a303 | 797 | int_mask = at91_mci_read(host, AT91_MCI_IMR); |
37b758e8 | 798 | |
f3a8efa9 | 799 | pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, |
df05a303 | 800 | int_status & int_mask); |
37b758e8 | 801 | |
df05a303 AV |
802 | int_status = int_status & int_mask; |
803 | ||
804 | if (int_status & AT91_MCI_ERRORS) { | |
65dbf343 | 805 | completed = 1; |
37b758e8 | 806 | |
df05a303 AV |
807 | if (int_status & AT91_MCI_UNRE) |
808 | pr_debug("MMC: Underrun error\n"); | |
809 | if (int_status & AT91_MCI_OVRE) | |
810 | pr_debug("MMC: Overrun error\n"); | |
811 | if (int_status & AT91_MCI_DTOE) | |
812 | pr_debug("MMC: Data timeout\n"); | |
813 | if (int_status & AT91_MCI_DCRCE) | |
814 | pr_debug("MMC: CRC error in data\n"); | |
815 | if (int_status & AT91_MCI_RTOE) | |
816 | pr_debug("MMC: Response timeout\n"); | |
817 | if (int_status & AT91_MCI_RENDE) | |
818 | pr_debug("MMC: Response end bit error\n"); | |
819 | if (int_status & AT91_MCI_RCRCE) | |
820 | pr_debug("MMC: Response CRC error\n"); | |
821 | if (int_status & AT91_MCI_RDIRE) | |
822 | pr_debug("MMC: Response direction error\n"); | |
823 | if (int_status & AT91_MCI_RINDE) | |
824 | pr_debug("MMC: Response index error\n"); | |
825 | } else { | |
826 | /* Only continue processing if no errors */ | |
65dbf343 | 827 | |
65dbf343 | 828 | if (int_status & AT91_MCI_TXBUFE) { |
b44fb7a0 | 829 | pr_debug("TX buffer empty\n"); |
65dbf343 AV |
830 | at91_mci_handle_transmitted(host); |
831 | } | |
832 | ||
ed99c541 NF |
833 | if (int_status & AT91_MCI_ENDRX) { |
834 | pr_debug("ENDRX\n"); | |
835 | at91_mci_post_dma_read(host); | |
836 | } | |
837 | ||
65dbf343 | 838 | if (int_status & AT91_MCI_RXBUFF) { |
b44fb7a0 | 839 | pr_debug("RX buffer full\n"); |
ed99c541 NF |
840 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
841 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); | |
842 | completed = 1; | |
65dbf343 AV |
843 | } |
844 | ||
df05a303 | 845 | if (int_status & AT91_MCI_ENDTX) |
b44fb7a0 | 846 | pr_debug("Transmit has ended\n"); |
65dbf343 | 847 | |
65dbf343 | 848 | if (int_status & AT91_MCI_NOTBUSY) { |
b44fb7a0 | 849 | pr_debug("Card is ready\n"); |
4ac24a87 | 850 | at91_mci_update_bytes_xfered(host); |
ed99c541 | 851 | completed = 1; |
65dbf343 AV |
852 | } |
853 | ||
df05a303 | 854 | if (int_status & AT91_MCI_DTIP) |
b44fb7a0 | 855 | pr_debug("Data transfer in progress\n"); |
65dbf343 | 856 | |
ed99c541 | 857 | if (int_status & AT91_MCI_BLKE) { |
b44fb7a0 | 858 | pr_debug("Block transfer has ended\n"); |
4ac24a87 NF |
859 | if (host->request->data && host->request->data->blocks > 1) { |
860 | /* multi block write : complete multi write | |
861 | * command and send stop */ | |
862 | completed = 1; | |
863 | } else { | |
864 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
865 | } | |
ed99c541 | 866 | } |
65dbf343 | 867 | |
7a6588ba EB |
868 | if (int_status & AT91_MCI_SDIOIRQA) |
869 | mmc_signal_sdio_irq(host->mmc); | |
870 | ||
871 | if (int_status & AT91_MCI_SDIOIRQB) | |
872 | mmc_signal_sdio_irq(host->mmc); | |
873 | ||
df05a303 | 874 | if (int_status & AT91_MCI_TXRDY) |
b44fb7a0 | 875 | pr_debug("Ready to transmit\n"); |
65dbf343 | 876 | |
df05a303 | 877 | if (int_status & AT91_MCI_RXRDY) |
b44fb7a0 | 878 | pr_debug("Ready to receive\n"); |
65dbf343 AV |
879 | |
880 | if (int_status & AT91_MCI_CMDRDY) { | |
b44fb7a0 | 881 | pr_debug("Command ready\n"); |
ed99c541 | 882 | completed = at91_mci_handle_cmdrdy(host); |
65dbf343 AV |
883 | } |
884 | } | |
65dbf343 AV |
885 | |
886 | if (completed) { | |
b44fb7a0 | 887 | pr_debug("Completed command\n"); |
7a6588ba | 888 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
ba7deeed | 889 | at91_mci_completed_command(host, int_status); |
df05a303 | 890 | } else |
7a6588ba | 891 | at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
65dbf343 AV |
892 | |
893 | return IRQ_HANDLED; | |
894 | } | |
895 | ||
7d12e780 | 896 | static irqreturn_t at91_mmc_det_irq(int irq, void *_host) |
65dbf343 AV |
897 | { |
898 | struct at91mci_host *host = _host; | |
6e996ee8 | 899 | int present = !gpio_get_value(irq_to_gpio(irq)); |
65dbf343 AV |
900 | |
901 | /* | |
902 | * we expect this irq on both insert and remove, | |
903 | * and use a short delay to debounce. | |
904 | */ | |
905 | if (present != host->present) { | |
906 | host->present = present; | |
b44fb7a0 | 907 | pr_debug("%s: card %s\n", mmc_hostname(host->mmc), |
65dbf343 AV |
908 | present ? "insert" : "remove"); |
909 | if (!present) { | |
b44fb7a0 | 910 | pr_debug("****** Resetting SD-card bus width ******\n"); |
99eeb8df | 911 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
65dbf343 AV |
912 | } |
913 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); | |
914 | } | |
915 | return IRQ_HANDLED; | |
916 | } | |
917 | ||
a26b498c | 918 | static int at91_mci_get_ro(struct mmc_host *mmc) |
65dbf343 | 919 | { |
65dbf343 AV |
920 | struct at91mci_host *host = mmc_priv(mmc); |
921 | ||
08f80bb5 AV |
922 | if (host->board->wp_pin) |
923 | return !!gpio_get_value(host->board->wp_pin); | |
924 | /* | |
925 | * Board doesn't support read only detection; let the mmc core | |
926 | * decide what to do. | |
927 | */ | |
928 | return -ENOSYS; | |
65dbf343 AV |
929 | } |
930 | ||
7a6588ba EB |
931 | static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
932 | { | |
933 | struct at91mci_host *host = mmc_priv(mmc); | |
934 | ||
935 | pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc), | |
936 | host->board->slot_b ? 'B':'A', enable ? "enable" : "disable"); | |
937 | at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR, | |
938 | host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA); | |
939 | ||
940 | } | |
941 | ||
ab7aefd0 | 942 | static const struct mmc_host_ops at91_mci_ops = { |
65dbf343 AV |
943 | .request = at91_mci_request, |
944 | .set_ios = at91_mci_set_ios, | |
945 | .get_ro = at91_mci_get_ro, | |
7a6588ba | 946 | .enable_sdio_irq = at91_mci_enable_sdio_irq, |
65dbf343 AV |
947 | }; |
948 | ||
949 | /* | |
950 | * Probe for the device | |
951 | */ | |
a26b498c | 952 | static int __init at91_mci_probe(struct platform_device *pdev) |
65dbf343 AV |
953 | { |
954 | struct mmc_host *mmc; | |
955 | struct at91mci_host *host; | |
17ea0595 | 956 | struct resource *res; |
65dbf343 AV |
957 | int ret; |
958 | ||
17ea0595 AV |
959 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
960 | if (!res) | |
961 | return -ENXIO; | |
962 | ||
963 | if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME)) | |
964 | return -EBUSY; | |
965 | ||
65dbf343 AV |
966 | mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); |
967 | if (!mmc) { | |
6e996ee8 DB |
968 | ret = -ENOMEM; |
969 | dev_dbg(&pdev->dev, "couldn't allocate mmc host\n"); | |
970 | goto fail6; | |
65dbf343 AV |
971 | } |
972 | ||
973 | mmc->ops = &at91_mci_ops; | |
974 | mmc->f_min = 375000; | |
975 | mmc->f_max = 25000000; | |
976 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
7a6588ba | 977 | mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ; |
65dbf343 | 978 | |
fe4a3c7a | 979 | mmc->max_blk_size = 4095; |
55db890a | 980 | mmc->max_blk_count = mmc->max_req_size; |
fe4a3c7a | 981 | |
65dbf343 AV |
982 | host = mmc_priv(mmc); |
983 | host->mmc = mmc; | |
984 | host->buffer = NULL; | |
985 | host->bus_mode = 0; | |
986 | host->board = pdev->dev.platform_data; | |
987 | if (host->board->wire4) { | |
ed99c541 NF |
988 | if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) |
989 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
990 | else | |
6e996ee8 | 991 | dev_warn(&pdev->dev, "4 wire bus mode not supported" |
ed99c541 | 992 | " - using 1 wire\n"); |
65dbf343 AV |
993 | } |
994 | ||
6e996ee8 DB |
995 | /* |
996 | * Reserve GPIOs ... board init code makes sure these pins are set | |
997 | * up as GPIOs with the right direction (input, except for vcc) | |
998 | */ | |
999 | if (host->board->det_pin) { | |
1000 | ret = gpio_request(host->board->det_pin, "mmc_detect"); | |
1001 | if (ret < 0) { | |
1002 | dev_dbg(&pdev->dev, "couldn't claim card detect pin\n"); | |
1003 | goto fail5; | |
1004 | } | |
1005 | } | |
1006 | if (host->board->wp_pin) { | |
1007 | ret = gpio_request(host->board->wp_pin, "mmc_wp"); | |
1008 | if (ret < 0) { | |
1009 | dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n"); | |
1010 | goto fail4; | |
1011 | } | |
1012 | } | |
1013 | if (host->board->vcc_pin) { | |
1014 | ret = gpio_request(host->board->vcc_pin, "mmc_vcc"); | |
1015 | if (ret < 0) { | |
1016 | dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n"); | |
1017 | goto fail3; | |
1018 | } | |
1019 | } | |
1020 | ||
65dbf343 AV |
1021 | /* |
1022 | * Get Clock | |
1023 | */ | |
3dd3b039 AV |
1024 | host->mci_clk = clk_get(&pdev->dev, "mci_clk"); |
1025 | if (IS_ERR(host->mci_clk)) { | |
6e996ee8 DB |
1026 | ret = -ENODEV; |
1027 | dev_dbg(&pdev->dev, "no mci_clk?\n"); | |
1028 | goto fail2; | |
65dbf343 | 1029 | } |
65dbf343 | 1030 | |
17ea0595 AV |
1031 | /* |
1032 | * Map I/O region | |
1033 | */ | |
1034 | host->baseaddr = ioremap(res->start, res->end - res->start + 1); | |
1035 | if (!host->baseaddr) { | |
6e996ee8 DB |
1036 | ret = -ENOMEM; |
1037 | goto fail1; | |
17ea0595 | 1038 | } |
e0b19b83 AV |
1039 | |
1040 | /* | |
1041 | * Reset hardware | |
1042 | */ | |
3dd3b039 | 1043 | clk_enable(host->mci_clk); /* Enable the peripheral clock */ |
e0b19b83 AV |
1044 | at91_mci_disable(host); |
1045 | at91_mci_enable(host); | |
1046 | ||
65dbf343 AV |
1047 | /* |
1048 | * Allocate the MCI interrupt | |
1049 | */ | |
17ea0595 | 1050 | host->irq = platform_get_irq(pdev, 0); |
6e996ee8 DB |
1051 | ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED, |
1052 | mmc_hostname(mmc), host); | |
65dbf343 | 1053 | if (ret) { |
6e996ee8 DB |
1054 | dev_dbg(&pdev->dev, "request MCI interrupt failed\n"); |
1055 | goto fail0; | |
65dbf343 AV |
1056 | } |
1057 | ||
1058 | platform_set_drvdata(pdev, mmc); | |
1059 | ||
1060 | /* | |
1061 | * Add host to MMC layer | |
1062 | */ | |
63b66438 | 1063 | if (host->board->det_pin) { |
6e996ee8 | 1064 | host->present = !gpio_get_value(host->board->det_pin); |
63b66438 | 1065 | } |
65dbf343 AV |
1066 | else |
1067 | host->present = -1; | |
1068 | ||
1069 | mmc_add_host(mmc); | |
1070 | ||
e181dce8 MP |
1071 | setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host); |
1072 | ||
65dbf343 AV |
1073 | /* |
1074 | * monitor card insertion/removal if we can | |
1075 | */ | |
1076 | if (host->board->det_pin) { | |
6e996ee8 DB |
1077 | ret = request_irq(gpio_to_irq(host->board->det_pin), |
1078 | at91_mmc_det_irq, 0, mmc_hostname(mmc), host); | |
65dbf343 | 1079 | if (ret) |
6e996ee8 DB |
1080 | dev_warn(&pdev->dev, "request MMC detect irq failed\n"); |
1081 | else | |
1082 | device_init_wakeup(&pdev->dev, 1); | |
65dbf343 AV |
1083 | } |
1084 | ||
f3a8efa9 | 1085 | pr_debug("Added MCI driver\n"); |
65dbf343 AV |
1086 | |
1087 | return 0; | |
6e996ee8 DB |
1088 | |
1089 | fail0: | |
1090 | clk_disable(host->mci_clk); | |
1091 | iounmap(host->baseaddr); | |
1092 | fail1: | |
1093 | clk_put(host->mci_clk); | |
1094 | fail2: | |
1095 | if (host->board->vcc_pin) | |
1096 | gpio_free(host->board->vcc_pin); | |
1097 | fail3: | |
1098 | if (host->board->wp_pin) | |
1099 | gpio_free(host->board->wp_pin); | |
1100 | fail4: | |
1101 | if (host->board->det_pin) | |
1102 | gpio_free(host->board->det_pin); | |
1103 | fail5: | |
1104 | mmc_free_host(mmc); | |
1105 | fail6: | |
1106 | release_mem_region(res->start, res->end - res->start + 1); | |
1107 | dev_err(&pdev->dev, "probe failed, err %d\n", ret); | |
1108 | return ret; | |
65dbf343 AV |
1109 | } |
1110 | ||
1111 | /* | |
1112 | * Remove a device | |
1113 | */ | |
a26b498c | 1114 | static int __exit at91_mci_remove(struct platform_device *pdev) |
65dbf343 AV |
1115 | { |
1116 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1117 | struct at91mci_host *host; | |
17ea0595 | 1118 | struct resource *res; |
65dbf343 AV |
1119 | |
1120 | if (!mmc) | |
1121 | return -1; | |
1122 | ||
1123 | host = mmc_priv(mmc); | |
1124 | ||
e0cda54e | 1125 | if (host->board->det_pin) { |
6e996ee8 DB |
1126 | if (device_can_wakeup(&pdev->dev)) |
1127 | free_irq(gpio_to_irq(host->board->det_pin), host); | |
63b66438 | 1128 | device_init_wakeup(&pdev->dev, 0); |
6e996ee8 | 1129 | gpio_free(host->board->det_pin); |
65dbf343 AV |
1130 | } |
1131 | ||
e0b19b83 | 1132 | at91_mci_disable(host); |
e181dce8 | 1133 | del_timer_sync(&host->timer); |
17ea0595 AV |
1134 | mmc_remove_host(mmc); |
1135 | free_irq(host->irq, host); | |
65dbf343 | 1136 | |
3dd3b039 AV |
1137 | clk_disable(host->mci_clk); /* Disable the peripheral clock */ |
1138 | clk_put(host->mci_clk); | |
65dbf343 | 1139 | |
6e996ee8 DB |
1140 | if (host->board->vcc_pin) |
1141 | gpio_free(host->board->vcc_pin); | |
1142 | if (host->board->wp_pin) | |
1143 | gpio_free(host->board->wp_pin); | |
1144 | ||
17ea0595 AV |
1145 | iounmap(host->baseaddr); |
1146 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1147 | release_mem_region(res->start, res->end - res->start + 1); | |
65dbf343 | 1148 | |
17ea0595 AV |
1149 | mmc_free_host(mmc); |
1150 | platform_set_drvdata(pdev, NULL); | |
b44fb7a0 | 1151 | pr_debug("MCI Removed\n"); |
65dbf343 AV |
1152 | |
1153 | return 0; | |
1154 | } | |
1155 | ||
1156 | #ifdef CONFIG_PM | |
1157 | static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state) | |
1158 | { | |
1159 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
63b66438 | 1160 | struct at91mci_host *host = mmc_priv(mmc); |
65dbf343 AV |
1161 | int ret = 0; |
1162 | ||
e0cda54e | 1163 | if (host->board->det_pin && device_may_wakeup(&pdev->dev)) |
63b66438 MP |
1164 | enable_irq_wake(host->board->det_pin); |
1165 | ||
65dbf343 AV |
1166 | if (mmc) |
1167 | ret = mmc_suspend_host(mmc, state); | |
1168 | ||
1169 | return ret; | |
1170 | } | |
1171 | ||
1172 | static int at91_mci_resume(struct platform_device *pdev) | |
1173 | { | |
1174 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
63b66438 | 1175 | struct at91mci_host *host = mmc_priv(mmc); |
65dbf343 AV |
1176 | int ret = 0; |
1177 | ||
e0cda54e | 1178 | if (host->board->det_pin && device_may_wakeup(&pdev->dev)) |
63b66438 MP |
1179 | disable_irq_wake(host->board->det_pin); |
1180 | ||
65dbf343 AV |
1181 | if (mmc) |
1182 | ret = mmc_resume_host(mmc); | |
1183 | ||
1184 | return ret; | |
1185 | } | |
1186 | #else | |
1187 | #define at91_mci_suspend NULL | |
1188 | #define at91_mci_resume NULL | |
1189 | #endif | |
1190 | ||
1191 | static struct platform_driver at91_mci_driver = { | |
a26b498c | 1192 | .remove = __exit_p(at91_mci_remove), |
65dbf343 AV |
1193 | .suspend = at91_mci_suspend, |
1194 | .resume = at91_mci_resume, | |
1195 | .driver = { | |
1196 | .name = DRIVER_NAME, | |
1197 | .owner = THIS_MODULE, | |
1198 | }, | |
1199 | }; | |
1200 | ||
1201 | static int __init at91_mci_init(void) | |
1202 | { | |
a26b498c | 1203 | return platform_driver_probe(&at91_mci_driver, at91_mci_probe); |
65dbf343 AV |
1204 | } |
1205 | ||
1206 | static void __exit at91_mci_exit(void) | |
1207 | { | |
1208 | platform_driver_unregister(&at91_mci_driver); | |
1209 | } | |
1210 | ||
1211 | module_init(at91_mci_init); | |
1212 | module_exit(at91_mci_exit); | |
1213 | ||
1214 | MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver"); | |
1215 | MODULE_AUTHOR("Nick Randell"); | |
1216 | MODULE_LICENSE("GPL"); | |
bc65c724 | 1217 | MODULE_ALIAS("platform:at91_mci"); |