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7d2be074 HS |
1 | /* |
2 | * Atmel MultiMedia Card Interface driver | |
3 | * | |
4 | * Copyright (C) 2004-2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/blkdev.h> | |
11 | #include <linux/clk.h> | |
deec9ae3 | 12 | #include <linux/debugfs.h> |
7d2be074 | 13 | #include <linux/device.h> |
65e8b083 HS |
14 | #include <linux/dmaengine.h> |
15 | #include <linux/dma-mapping.h> | |
fbfca4b8 | 16 | #include <linux/err.h> |
3c26e170 | 17 | #include <linux/gpio.h> |
7d2be074 HS |
18 | #include <linux/init.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/scatterlist.h> | |
deec9ae3 | 24 | #include <linux/seq_file.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
deec9ae3 | 26 | #include <linux/stat.h> |
7d2be074 HS |
27 | |
28 | #include <linux/mmc/host.h> | |
2f1d7918 | 29 | #include <linux/mmc/sdio.h> |
2635d1ba NF |
30 | |
31 | #include <mach/atmel-mci.h> | |
c42aa775 | 32 | #include <linux/atmel-mci.h> |
7d2be074 | 33 | |
7d2be074 HS |
34 | #include <asm/io.h> |
35 | #include <asm/unaligned.h> | |
36 | ||
04d699c3 | 37 | #include <mach/cpu.h> |
3663b736 | 38 | #include <mach/board.h> |
7d2be074 HS |
39 | |
40 | #include "atmel-mci-regs.h" | |
41 | ||
42 | #define ATMCI_DATA_ERROR_FLAGS (MCI_DCRCE | MCI_DTOE | MCI_OVRE | MCI_UNRE) | |
65e8b083 | 43 | #define ATMCI_DMA_THRESHOLD 16 |
7d2be074 HS |
44 | |
45 | enum { | |
46 | EVENT_CMD_COMPLETE = 0, | |
7d2be074 | 47 | EVENT_XFER_COMPLETE, |
c06ad258 HS |
48 | EVENT_DATA_COMPLETE, |
49 | EVENT_DATA_ERROR, | |
50 | }; | |
51 | ||
52 | enum atmel_mci_state { | |
965ebf33 HS |
53 | STATE_IDLE = 0, |
54 | STATE_SENDING_CMD, | |
c06ad258 HS |
55 | STATE_SENDING_DATA, |
56 | STATE_DATA_BUSY, | |
57 | STATE_SENDING_STOP, | |
58 | STATE_DATA_ERROR, | |
7d2be074 HS |
59 | }; |
60 | ||
65e8b083 HS |
61 | struct atmel_mci_dma { |
62 | #ifdef CONFIG_MMC_ATMELMCI_DMA | |
65e8b083 HS |
63 | struct dma_chan *chan; |
64 | struct dma_async_tx_descriptor *data_desc; | |
65 | #endif | |
66 | }; | |
67 | ||
965ebf33 HS |
68 | /** |
69 | * struct atmel_mci - MMC controller state shared between all slots | |
70 | * @lock: Spinlock protecting the queue and associated data. | |
71 | * @regs: Pointer to MMIO registers. | |
72 | * @sg: Scatterlist entry currently being processed by PIO code, if any. | |
73 | * @pio_offset: Offset into the current scatterlist entry. | |
74 | * @cur_slot: The slot which is currently using the controller. | |
75 | * @mrq: The request currently being processed on @cur_slot, | |
76 | * or NULL if the controller is idle. | |
77 | * @cmd: The command currently being sent to the card, or NULL. | |
78 | * @data: The data currently being transferred, or NULL if no data | |
79 | * transfer is in progress. | |
65e8b083 HS |
80 | * @dma: DMA client state. |
81 | * @data_chan: DMA channel being used for the current data transfer. | |
965ebf33 HS |
82 | * @cmd_status: Snapshot of SR taken upon completion of the current |
83 | * command. Only valid when EVENT_CMD_COMPLETE is pending. | |
84 | * @data_status: Snapshot of SR taken upon completion of the current | |
85 | * data transfer. Only valid when EVENT_DATA_COMPLETE or | |
86 | * EVENT_DATA_ERROR is pending. | |
87 | * @stop_cmdr: Value to be loaded into CMDR when the stop command is | |
88 | * to be sent. | |
89 | * @tasklet: Tasklet running the request state machine. | |
90 | * @pending_events: Bitmask of events flagged by the interrupt handler | |
91 | * to be processed by the tasklet. | |
92 | * @completed_events: Bitmask of events which the state machine has | |
93 | * processed. | |
94 | * @state: Tasklet state. | |
95 | * @queue: List of slots waiting for access to the controller. | |
96 | * @need_clock_update: Update the clock rate before the next request. | |
97 | * @need_reset: Reset controller before next request. | |
98 | * @mode_reg: Value of the MR register. | |
74791a2d | 99 | * @cfg_reg: Value of the CFG register. |
965ebf33 HS |
100 | * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus |
101 | * rate and timeout calculations. | |
102 | * @mapbase: Physical address of the MMIO registers. | |
103 | * @mck: The peripheral bus clock hooked up to the MMC controller. | |
104 | * @pdev: Platform device associated with the MMC controller. | |
105 | * @slot: Slots sharing this MMC controller. | |
106 | * | |
107 | * Locking | |
108 | * ======= | |
109 | * | |
110 | * @lock is a softirq-safe spinlock protecting @queue as well as | |
111 | * @cur_slot, @mrq and @state. These must always be updated | |
112 | * at the same time while holding @lock. | |
113 | * | |
114 | * @lock also protects mode_reg and need_clock_update since these are | |
115 | * used to synchronize mode register updates with the queue | |
116 | * processing. | |
117 | * | |
118 | * The @mrq field of struct atmel_mci_slot is also protected by @lock, | |
119 | * and must always be written at the same time as the slot is added to | |
120 | * @queue. | |
121 | * | |
122 | * @pending_events and @completed_events are accessed using atomic bit | |
123 | * operations, so they don't need any locking. | |
124 | * | |
125 | * None of the fields touched by the interrupt handler need any | |
126 | * locking. However, ordering is important: Before EVENT_DATA_ERROR or | |
127 | * EVENT_DATA_COMPLETE is set in @pending_events, all data-related | |
128 | * interrupts must be disabled and @data_status updated with a | |
129 | * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the | |
130 | * CMDRDY interupt must be disabled and @cmd_status updated with a | |
131 | * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the | |
132 | * bytes_xfered field of @data must be written. This is ensured by | |
133 | * using barriers. | |
134 | */ | |
7d2be074 | 135 | struct atmel_mci { |
965ebf33 | 136 | spinlock_t lock; |
7d2be074 HS |
137 | void __iomem *regs; |
138 | ||
139 | struct scatterlist *sg; | |
140 | unsigned int pio_offset; | |
141 | ||
965ebf33 | 142 | struct atmel_mci_slot *cur_slot; |
7d2be074 HS |
143 | struct mmc_request *mrq; |
144 | struct mmc_command *cmd; | |
145 | struct mmc_data *data; | |
146 | ||
65e8b083 HS |
147 | struct atmel_mci_dma dma; |
148 | struct dma_chan *data_chan; | |
149 | ||
7d2be074 HS |
150 | u32 cmd_status; |
151 | u32 data_status; | |
7d2be074 HS |
152 | u32 stop_cmdr; |
153 | ||
7d2be074 HS |
154 | struct tasklet_struct tasklet; |
155 | unsigned long pending_events; | |
156 | unsigned long completed_events; | |
c06ad258 | 157 | enum atmel_mci_state state; |
965ebf33 | 158 | struct list_head queue; |
7d2be074 | 159 | |
965ebf33 HS |
160 | bool need_clock_update; |
161 | bool need_reset; | |
162 | u32 mode_reg; | |
74791a2d | 163 | u32 cfg_reg; |
7d2be074 HS |
164 | unsigned long bus_hz; |
165 | unsigned long mapbase; | |
166 | struct clk *mck; | |
167 | struct platform_device *pdev; | |
965ebf33 HS |
168 | |
169 | struct atmel_mci_slot *slot[ATMEL_MCI_MAX_NR_SLOTS]; | |
170 | }; | |
171 | ||
172 | /** | |
173 | * struct atmel_mci_slot - MMC slot state | |
174 | * @mmc: The mmc_host representing this slot. | |
175 | * @host: The MMC controller this slot is using. | |
176 | * @sdc_reg: Value of SDCR to be written before using this slot. | |
88ff82ed | 177 | * @sdio_irq: SDIO irq mask for this slot. |
965ebf33 HS |
178 | * @mrq: mmc_request currently being processed or waiting to be |
179 | * processed, or NULL when the slot is idle. | |
180 | * @queue_node: List node for placing this node in the @queue list of | |
181 | * &struct atmel_mci. | |
182 | * @clock: Clock rate configured by set_ios(). Protected by host->lock. | |
183 | * @flags: Random state bits associated with the slot. | |
184 | * @detect_pin: GPIO pin used for card detection, or negative if not | |
185 | * available. | |
186 | * @wp_pin: GPIO pin used for card write protect sending, or negative | |
187 | * if not available. | |
1c1452be | 188 | * @detect_is_active_high: The state of the detect pin when it is active. |
965ebf33 HS |
189 | * @detect_timer: Timer used for debouncing @detect_pin interrupts. |
190 | */ | |
191 | struct atmel_mci_slot { | |
192 | struct mmc_host *mmc; | |
193 | struct atmel_mci *host; | |
194 | ||
195 | u32 sdc_reg; | |
88ff82ed | 196 | u32 sdio_irq; |
965ebf33 HS |
197 | |
198 | struct mmc_request *mrq; | |
199 | struct list_head queue_node; | |
200 | ||
201 | unsigned int clock; | |
202 | unsigned long flags; | |
203 | #define ATMCI_CARD_PRESENT 0 | |
204 | #define ATMCI_CARD_NEED_INIT 1 | |
205 | #define ATMCI_SHUTDOWN 2 | |
206 | ||
207 | int detect_pin; | |
208 | int wp_pin; | |
1c1452be | 209 | bool detect_is_active_high; |
965ebf33 HS |
210 | |
211 | struct timer_list detect_timer; | |
7d2be074 HS |
212 | }; |
213 | ||
7d2be074 HS |
214 | #define atmci_test_and_clear_pending(host, event) \ |
215 | test_and_clear_bit(event, &host->pending_events) | |
7d2be074 HS |
216 | #define atmci_set_completed(host, event) \ |
217 | set_bit(event, &host->completed_events) | |
218 | #define atmci_set_pending(host, event) \ | |
219 | set_bit(event, &host->pending_events) | |
7d2be074 | 220 | |
04d699c3 RE |
221 | /* |
222 | * Enable or disable features/registers based on | |
223 | * whether the processor supports them | |
224 | */ | |
225 | static bool mci_has_rwproof(void) | |
226 | { | |
227 | if (cpu_is_at91sam9261() || cpu_is_at91rm9200()) | |
228 | return false; | |
229 | else | |
230 | return true; | |
231 | } | |
232 | ||
74791a2d NF |
233 | /* |
234 | * The new MCI2 module isn't 100% compatible with the old MCI module, | |
235 | * and it has a few nice features which we want to use... | |
236 | */ | |
237 | static inline bool atmci_is_mci2(void) | |
238 | { | |
239 | if (cpu_is_at91sam9g45()) | |
240 | return true; | |
241 | ||
242 | return false; | |
243 | } | |
244 | ||
245 | ||
deec9ae3 HS |
246 | /* |
247 | * The debugfs stuff below is mostly optimized away when | |
248 | * CONFIG_DEBUG_FS is not set. | |
249 | */ | |
250 | static int atmci_req_show(struct seq_file *s, void *v) | |
251 | { | |
965ebf33 HS |
252 | struct atmel_mci_slot *slot = s->private; |
253 | struct mmc_request *mrq; | |
deec9ae3 HS |
254 | struct mmc_command *cmd; |
255 | struct mmc_command *stop; | |
256 | struct mmc_data *data; | |
257 | ||
258 | /* Make sure we get a consistent snapshot */ | |
965ebf33 HS |
259 | spin_lock_bh(&slot->host->lock); |
260 | mrq = slot->mrq; | |
deec9ae3 HS |
261 | |
262 | if (mrq) { | |
263 | cmd = mrq->cmd; | |
264 | data = mrq->data; | |
265 | stop = mrq->stop; | |
266 | ||
267 | if (cmd) | |
268 | seq_printf(s, | |
269 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
270 | cmd->opcode, cmd->arg, cmd->flags, | |
271 | cmd->resp[0], cmd->resp[1], cmd->resp[2], | |
d586ebbb | 272 | cmd->resp[3], cmd->error); |
deec9ae3 HS |
273 | if (data) |
274 | seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", | |
275 | data->bytes_xfered, data->blocks, | |
276 | data->blksz, data->flags, data->error); | |
277 | if (stop) | |
278 | seq_printf(s, | |
279 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
280 | stop->opcode, stop->arg, stop->flags, | |
281 | stop->resp[0], stop->resp[1], stop->resp[2], | |
d586ebbb | 282 | stop->resp[3], stop->error); |
deec9ae3 HS |
283 | } |
284 | ||
965ebf33 | 285 | spin_unlock_bh(&slot->host->lock); |
deec9ae3 HS |
286 | |
287 | return 0; | |
288 | } | |
289 | ||
290 | static int atmci_req_open(struct inode *inode, struct file *file) | |
291 | { | |
292 | return single_open(file, atmci_req_show, inode->i_private); | |
293 | } | |
294 | ||
295 | static const struct file_operations atmci_req_fops = { | |
296 | .owner = THIS_MODULE, | |
297 | .open = atmci_req_open, | |
298 | .read = seq_read, | |
299 | .llseek = seq_lseek, | |
300 | .release = single_release, | |
301 | }; | |
302 | ||
303 | static void atmci_show_status_reg(struct seq_file *s, | |
304 | const char *regname, u32 value) | |
305 | { | |
306 | static const char *sr_bit[] = { | |
307 | [0] = "CMDRDY", | |
308 | [1] = "RXRDY", | |
309 | [2] = "TXRDY", | |
310 | [3] = "BLKE", | |
311 | [4] = "DTIP", | |
312 | [5] = "NOTBUSY", | |
04d699c3 RE |
313 | [6] = "ENDRX", |
314 | [7] = "ENDTX", | |
deec9ae3 HS |
315 | [8] = "SDIOIRQA", |
316 | [9] = "SDIOIRQB", | |
04d699c3 RE |
317 | [12] = "SDIOWAIT", |
318 | [14] = "RXBUFF", | |
319 | [15] = "TXBUFE", | |
deec9ae3 HS |
320 | [16] = "RINDE", |
321 | [17] = "RDIRE", | |
322 | [18] = "RCRCE", | |
323 | [19] = "RENDE", | |
324 | [20] = "RTOE", | |
325 | [21] = "DCRCE", | |
326 | [22] = "DTOE", | |
04d699c3 RE |
327 | [23] = "CSTOE", |
328 | [24] = "BLKOVRE", | |
329 | [25] = "DMADONE", | |
330 | [26] = "FIFOEMPTY", | |
331 | [27] = "XFRDONE", | |
deec9ae3 HS |
332 | [30] = "OVRE", |
333 | [31] = "UNRE", | |
334 | }; | |
335 | unsigned int i; | |
336 | ||
337 | seq_printf(s, "%s:\t0x%08x", regname, value); | |
338 | for (i = 0; i < ARRAY_SIZE(sr_bit); i++) { | |
339 | if (value & (1 << i)) { | |
340 | if (sr_bit[i]) | |
341 | seq_printf(s, " %s", sr_bit[i]); | |
342 | else | |
343 | seq_puts(s, " UNKNOWN"); | |
344 | } | |
345 | } | |
346 | seq_putc(s, '\n'); | |
347 | } | |
348 | ||
349 | static int atmci_regs_show(struct seq_file *s, void *v) | |
350 | { | |
351 | struct atmel_mci *host = s->private; | |
352 | u32 *buf; | |
353 | ||
354 | buf = kmalloc(MCI_REGS_SIZE, GFP_KERNEL); | |
355 | if (!buf) | |
356 | return -ENOMEM; | |
357 | ||
965ebf33 HS |
358 | /* |
359 | * Grab a more or less consistent snapshot. Note that we're | |
360 | * not disabling interrupts, so IMR and SR may not be | |
361 | * consistent. | |
362 | */ | |
363 | spin_lock_bh(&host->lock); | |
87e60f2b | 364 | clk_enable(host->mck); |
deec9ae3 | 365 | memcpy_fromio(buf, host->regs, MCI_REGS_SIZE); |
87e60f2b | 366 | clk_disable(host->mck); |
965ebf33 | 367 | spin_unlock_bh(&host->lock); |
deec9ae3 HS |
368 | |
369 | seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n", | |
370 | buf[MCI_MR / 4], | |
371 | buf[MCI_MR / 4] & MCI_MR_RDPROOF ? " RDPROOF" : "", | |
372 | buf[MCI_MR / 4] & MCI_MR_WRPROOF ? " WRPROOF" : "", | |
373 | buf[MCI_MR / 4] & 0xff); | |
374 | seq_printf(s, "DTOR:\t0x%08x\n", buf[MCI_DTOR / 4]); | |
375 | seq_printf(s, "SDCR:\t0x%08x\n", buf[MCI_SDCR / 4]); | |
376 | seq_printf(s, "ARGR:\t0x%08x\n", buf[MCI_ARGR / 4]); | |
377 | seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", | |
378 | buf[MCI_BLKR / 4], | |
379 | buf[MCI_BLKR / 4] & 0xffff, | |
380 | (buf[MCI_BLKR / 4] >> 16) & 0xffff); | |
74791a2d NF |
381 | if (atmci_is_mci2()) |
382 | seq_printf(s, "CSTOR:\t0x%08x\n", buf[MCI_CSTOR / 4]); | |
deec9ae3 HS |
383 | |
384 | /* Don't read RSPR and RDR; it will consume the data there */ | |
385 | ||
386 | atmci_show_status_reg(s, "SR", buf[MCI_SR / 4]); | |
387 | atmci_show_status_reg(s, "IMR", buf[MCI_IMR / 4]); | |
388 | ||
74791a2d NF |
389 | if (atmci_is_mci2()) { |
390 | u32 val; | |
391 | ||
392 | val = buf[MCI_DMA / 4]; | |
393 | seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", | |
394 | val, val & 3, | |
395 | ((val >> 4) & 3) ? | |
396 | 1 << (((val >> 4) & 3) + 1) : 1, | |
397 | val & MCI_DMAEN ? " DMAEN" : ""); | |
398 | ||
399 | val = buf[MCI_CFG / 4]; | |
400 | seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", | |
401 | val, | |
402 | val & MCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", | |
403 | val & MCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", | |
404 | val & MCI_CFG_HSMODE ? " HSMODE" : "", | |
405 | val & MCI_CFG_LSYNC ? " LSYNC" : ""); | |
406 | } | |
407 | ||
b17339a1 HS |
408 | kfree(buf); |
409 | ||
deec9ae3 HS |
410 | return 0; |
411 | } | |
412 | ||
413 | static int atmci_regs_open(struct inode *inode, struct file *file) | |
414 | { | |
415 | return single_open(file, atmci_regs_show, inode->i_private); | |
416 | } | |
417 | ||
418 | static const struct file_operations atmci_regs_fops = { | |
419 | .owner = THIS_MODULE, | |
420 | .open = atmci_regs_open, | |
421 | .read = seq_read, | |
422 | .llseek = seq_lseek, | |
423 | .release = single_release, | |
424 | }; | |
425 | ||
965ebf33 | 426 | static void atmci_init_debugfs(struct atmel_mci_slot *slot) |
deec9ae3 | 427 | { |
965ebf33 HS |
428 | struct mmc_host *mmc = slot->mmc; |
429 | struct atmel_mci *host = slot->host; | |
430 | struct dentry *root; | |
431 | struct dentry *node; | |
deec9ae3 | 432 | |
deec9ae3 HS |
433 | root = mmc->debugfs_root; |
434 | if (!root) | |
435 | return; | |
436 | ||
437 | node = debugfs_create_file("regs", S_IRUSR, root, host, | |
438 | &atmci_regs_fops); | |
439 | if (IS_ERR(node)) | |
440 | return; | |
441 | if (!node) | |
442 | goto err; | |
443 | ||
965ebf33 | 444 | node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops); |
deec9ae3 HS |
445 | if (!node) |
446 | goto err; | |
447 | ||
c06ad258 HS |
448 | node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); |
449 | if (!node) | |
450 | goto err; | |
451 | ||
deec9ae3 HS |
452 | node = debugfs_create_x32("pending_events", S_IRUSR, root, |
453 | (u32 *)&host->pending_events); | |
454 | if (!node) | |
455 | goto err; | |
456 | ||
457 | node = debugfs_create_x32("completed_events", S_IRUSR, root, | |
458 | (u32 *)&host->completed_events); | |
459 | if (!node) | |
460 | goto err; | |
461 | ||
462 | return; | |
463 | ||
464 | err: | |
965ebf33 | 465 | dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); |
deec9ae3 | 466 | } |
7d2be074 | 467 | |
7d2be074 HS |
468 | static inline unsigned int ns_to_clocks(struct atmel_mci *host, |
469 | unsigned int ns) | |
470 | { | |
471 | return (ns * (host->bus_hz / 1000000) + 999) / 1000; | |
472 | } | |
473 | ||
474 | static void atmci_set_timeout(struct atmel_mci *host, | |
965ebf33 | 475 | struct atmel_mci_slot *slot, struct mmc_data *data) |
7d2be074 HS |
476 | { |
477 | static unsigned dtomul_to_shift[] = { | |
478 | 0, 4, 7, 8, 10, 12, 16, 20 | |
479 | }; | |
480 | unsigned timeout; | |
481 | unsigned dtocyc; | |
482 | unsigned dtomul; | |
483 | ||
484 | timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks; | |
485 | ||
486 | for (dtomul = 0; dtomul < 8; dtomul++) { | |
487 | unsigned shift = dtomul_to_shift[dtomul]; | |
488 | dtocyc = (timeout + (1 << shift) - 1) >> shift; | |
489 | if (dtocyc < 15) | |
490 | break; | |
491 | } | |
492 | ||
493 | if (dtomul >= 8) { | |
494 | dtomul = 7; | |
495 | dtocyc = 15; | |
496 | } | |
497 | ||
965ebf33 | 498 | dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", |
7d2be074 HS |
499 | dtocyc << dtomul_to_shift[dtomul]); |
500 | mci_writel(host, DTOR, (MCI_DTOMUL(dtomul) | MCI_DTOCYC(dtocyc))); | |
501 | } | |
502 | ||
503 | /* | |
504 | * Return mask with command flags to be enabled for this command. | |
505 | */ | |
506 | static u32 atmci_prepare_command(struct mmc_host *mmc, | |
507 | struct mmc_command *cmd) | |
508 | { | |
509 | struct mmc_data *data; | |
510 | u32 cmdr; | |
511 | ||
512 | cmd->error = -EINPROGRESS; | |
513 | ||
514 | cmdr = MCI_CMDR_CMDNB(cmd->opcode); | |
515 | ||
516 | if (cmd->flags & MMC_RSP_PRESENT) { | |
517 | if (cmd->flags & MMC_RSP_136) | |
518 | cmdr |= MCI_CMDR_RSPTYP_136BIT; | |
519 | else | |
520 | cmdr |= MCI_CMDR_RSPTYP_48BIT; | |
521 | } | |
522 | ||
523 | /* | |
524 | * This should really be MAXLAT_5 for CMD2 and ACMD41, but | |
525 | * it's too difficult to determine whether this is an ACMD or | |
526 | * not. Better make it 64. | |
527 | */ | |
528 | cmdr |= MCI_CMDR_MAXLAT_64CYC; | |
529 | ||
530 | if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) | |
531 | cmdr |= MCI_CMDR_OPDCMD; | |
532 | ||
533 | data = cmd->data; | |
534 | if (data) { | |
535 | cmdr |= MCI_CMDR_START_XFER; | |
2f1d7918 NF |
536 | |
537 | if (cmd->opcode == SD_IO_RW_EXTENDED) { | |
538 | cmdr |= MCI_CMDR_SDIO_BLOCK; | |
539 | } else { | |
540 | if (data->flags & MMC_DATA_STREAM) | |
541 | cmdr |= MCI_CMDR_STREAM; | |
542 | else if (data->blocks > 1) | |
543 | cmdr |= MCI_CMDR_MULTI_BLOCK; | |
544 | else | |
545 | cmdr |= MCI_CMDR_BLOCK; | |
546 | } | |
7d2be074 HS |
547 | |
548 | if (data->flags & MMC_DATA_READ) | |
549 | cmdr |= MCI_CMDR_TRDIR_READ; | |
550 | } | |
551 | ||
552 | return cmdr; | |
553 | } | |
554 | ||
555 | static void atmci_start_command(struct atmel_mci *host, | |
965ebf33 | 556 | struct mmc_command *cmd, u32 cmd_flags) |
7d2be074 | 557 | { |
7d2be074 HS |
558 | WARN_ON(host->cmd); |
559 | host->cmd = cmd; | |
560 | ||
965ebf33 | 561 | dev_vdbg(&host->pdev->dev, |
7d2be074 HS |
562 | "start command: ARGR=0x%08x CMDR=0x%08x\n", |
563 | cmd->arg, cmd_flags); | |
564 | ||
565 | mci_writel(host, ARGR, cmd->arg); | |
566 | mci_writel(host, CMDR, cmd_flags); | |
567 | } | |
568 | ||
965ebf33 | 569 | static void send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) |
7d2be074 | 570 | { |
7d2be074 HS |
571 | atmci_start_command(host, data->stop, host->stop_cmdr); |
572 | mci_writel(host, IER, MCI_CMDRDY); | |
573 | } | |
574 | ||
65e8b083 HS |
575 | #ifdef CONFIG_MMC_ATMELMCI_DMA |
576 | static void atmci_dma_cleanup(struct atmel_mci *host) | |
577 | { | |
578 | struct mmc_data *data = host->data; | |
579 | ||
009a891b NF |
580 | if (data) |
581 | dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, | |
582 | ((data->flags & MMC_DATA_WRITE) | |
583 | ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); | |
65e8b083 HS |
584 | } |
585 | ||
586 | static void atmci_stop_dma(struct atmel_mci *host) | |
587 | { | |
588 | struct dma_chan *chan = host->data_chan; | |
589 | ||
590 | if (chan) { | |
05827630 | 591 | chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); |
65e8b083 HS |
592 | atmci_dma_cleanup(host); |
593 | } else { | |
594 | /* Data transfer was stopped by the interrupt handler */ | |
595 | atmci_set_pending(host, EVENT_XFER_COMPLETE); | |
596 | mci_writel(host, IER, MCI_NOTBUSY); | |
597 | } | |
598 | } | |
599 | ||
600 | /* This function is called by the DMA driver from tasklet context. */ | |
601 | static void atmci_dma_complete(void *arg) | |
602 | { | |
603 | struct atmel_mci *host = arg; | |
604 | struct mmc_data *data = host->data; | |
605 | ||
606 | dev_vdbg(&host->pdev->dev, "DMA complete\n"); | |
607 | ||
74791a2d NF |
608 | if (atmci_is_mci2()) |
609 | /* Disable DMA hardware handshaking on MCI */ | |
610 | mci_writel(host, DMA, mci_readl(host, DMA) & ~MCI_DMAEN); | |
611 | ||
65e8b083 HS |
612 | atmci_dma_cleanup(host); |
613 | ||
614 | /* | |
615 | * If the card was removed, data will be NULL. No point trying | |
616 | * to send the stop command or waiting for NBUSY in this case. | |
617 | */ | |
618 | if (data) { | |
619 | atmci_set_pending(host, EVENT_XFER_COMPLETE); | |
620 | tasklet_schedule(&host->tasklet); | |
621 | ||
622 | /* | |
623 | * Regardless of what the documentation says, we have | |
624 | * to wait for NOTBUSY even after block read | |
625 | * operations. | |
626 | * | |
627 | * When the DMA transfer is complete, the controller | |
628 | * may still be reading the CRC from the card, i.e. | |
629 | * the data transfer is still in progress and we | |
630 | * haven't seen all the potential error bits yet. | |
631 | * | |
632 | * The interrupt handler will schedule a different | |
633 | * tasklet to finish things up when the data transfer | |
634 | * is completely done. | |
635 | * | |
636 | * We may not complete the mmc request here anyway | |
637 | * because the mmc layer may call back and cause us to | |
638 | * violate the "don't submit new operations from the | |
639 | * completion callback" rule of the dma engine | |
640 | * framework. | |
641 | */ | |
642 | mci_writel(host, IER, MCI_NOTBUSY); | |
643 | } | |
644 | } | |
645 | ||
646 | static int | |
74791a2d | 647 | atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) |
65e8b083 HS |
648 | { |
649 | struct dma_chan *chan; | |
650 | struct dma_async_tx_descriptor *desc; | |
651 | struct scatterlist *sg; | |
652 | unsigned int i; | |
653 | enum dma_data_direction direction; | |
657a77fa | 654 | unsigned int sglen; |
65e8b083 HS |
655 | |
656 | /* | |
657 | * We don't do DMA on "complex" transfers, i.e. with | |
658 | * non-word-aligned buffers or lengths. Also, we don't bother | |
659 | * with all the DMA setup overhead for short transfers. | |
660 | */ | |
661 | if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) | |
662 | return -EINVAL; | |
663 | if (data->blksz & 3) | |
664 | return -EINVAL; | |
665 | ||
666 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
667 | if (sg->offset & 3 || sg->length & 3) | |
668 | return -EINVAL; | |
669 | } | |
670 | ||
671 | /* If we don't have a channel, we can't do DMA */ | |
672 | chan = host->dma.chan; | |
6f49a57a | 673 | if (chan) |
65e8b083 | 674 | host->data_chan = chan; |
65e8b083 HS |
675 | |
676 | if (!chan) | |
677 | return -ENODEV; | |
678 | ||
74791a2d NF |
679 | if (atmci_is_mci2()) |
680 | mci_writel(host, DMA, MCI_DMA_CHKSIZE(3) | MCI_DMAEN); | |
681 | ||
65e8b083 HS |
682 | if (data->flags & MMC_DATA_READ) |
683 | direction = DMA_FROM_DEVICE; | |
684 | else | |
685 | direction = DMA_TO_DEVICE; | |
686 | ||
657a77fa AN |
687 | sglen = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, direction); |
688 | if (sglen != data->sg_len) | |
689 | goto unmap_exit; | |
65e8b083 HS |
690 | desc = chan->device->device_prep_slave_sg(chan, |
691 | data->sg, data->sg_len, direction, | |
692 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
693 | if (!desc) | |
657a77fa | 694 | goto unmap_exit; |
65e8b083 HS |
695 | |
696 | host->dma.data_desc = desc; | |
697 | desc->callback = atmci_dma_complete; | |
698 | desc->callback_param = host; | |
65e8b083 HS |
699 | |
700 | return 0; | |
657a77fa AN |
701 | unmap_exit: |
702 | dma_unmap_sg(&host->pdev->dev, data->sg, sglen, direction); | |
703 | return -ENOMEM; | |
65e8b083 HS |
704 | } |
705 | ||
74791a2d NF |
706 | static void atmci_submit_data(struct atmel_mci *host) |
707 | { | |
708 | struct dma_chan *chan = host->data_chan; | |
709 | struct dma_async_tx_descriptor *desc = host->dma.data_desc; | |
710 | ||
711 | if (chan) { | |
712 | desc->tx_submit(desc); | |
713 | chan->device->device_issue_pending(chan); | |
714 | } | |
715 | } | |
716 | ||
65e8b083 HS |
717 | #else /* CONFIG_MMC_ATMELMCI_DMA */ |
718 | ||
74791a2d | 719 | static int atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) |
65e8b083 HS |
720 | { |
721 | return -ENOSYS; | |
722 | } | |
723 | ||
74791a2d NF |
724 | static void atmci_submit_data(struct atmel_mci *host) {} |
725 | ||
65e8b083 HS |
726 | static void atmci_stop_dma(struct atmel_mci *host) |
727 | { | |
728 | /* Data transfer was stopped by the interrupt handler */ | |
729 | atmci_set_pending(host, EVENT_XFER_COMPLETE); | |
730 | mci_writel(host, IER, MCI_NOTBUSY); | |
731 | } | |
732 | ||
733 | #endif /* CONFIG_MMC_ATMELMCI_DMA */ | |
734 | ||
7d2be074 HS |
735 | /* |
736 | * Returns a mask of interrupt flags to be enabled after the whole | |
737 | * request has been prepared. | |
738 | */ | |
74791a2d | 739 | static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data) |
7d2be074 | 740 | { |
965ebf33 | 741 | u32 iflags; |
7d2be074 HS |
742 | |
743 | data->error = -EINPROGRESS; | |
744 | ||
745 | WARN_ON(host->data); | |
746 | host->sg = NULL; | |
747 | host->data = data; | |
748 | ||
7d2be074 | 749 | iflags = ATMCI_DATA_ERROR_FLAGS; |
74791a2d | 750 | if (atmci_prepare_data_dma(host, data)) { |
65e8b083 | 751 | host->data_chan = NULL; |
965ebf33 | 752 | |
65e8b083 HS |
753 | /* |
754 | * Errata: MMC data write operation with less than 12 | |
755 | * bytes is impossible. | |
756 | * | |
757 | * Errata: MCI Transmit Data Register (TDR) FIFO | |
758 | * corruption when length is not multiple of 4. | |
759 | */ | |
760 | if (data->blocks * data->blksz < 12 | |
761 | || (data->blocks * data->blksz) & 3) | |
762 | host->need_reset = true; | |
965ebf33 | 763 | |
65e8b083 HS |
764 | host->sg = data->sg; |
765 | host->pio_offset = 0; | |
766 | if (data->flags & MMC_DATA_READ) | |
767 | iflags |= MCI_RXRDY; | |
768 | else | |
769 | iflags |= MCI_TXRDY; | |
770 | } | |
7d2be074 HS |
771 | |
772 | return iflags; | |
773 | } | |
774 | ||
965ebf33 HS |
775 | static void atmci_start_request(struct atmel_mci *host, |
776 | struct atmel_mci_slot *slot) | |
7d2be074 | 777 | { |
965ebf33 | 778 | struct mmc_request *mrq; |
7d2be074 | 779 | struct mmc_command *cmd; |
965ebf33 | 780 | struct mmc_data *data; |
7d2be074 | 781 | u32 iflags; |
965ebf33 | 782 | u32 cmdflags; |
7d2be074 | 783 | |
965ebf33 HS |
784 | mrq = slot->mrq; |
785 | host->cur_slot = slot; | |
7d2be074 | 786 | host->mrq = mrq; |
965ebf33 | 787 | |
7d2be074 HS |
788 | host->pending_events = 0; |
789 | host->completed_events = 0; | |
ca55f46e | 790 | host->data_status = 0; |
7d2be074 | 791 | |
965ebf33 HS |
792 | if (host->need_reset) { |
793 | mci_writel(host, CR, MCI_CR_SWRST); | |
794 | mci_writel(host, CR, MCI_CR_MCIEN); | |
795 | mci_writel(host, MR, host->mode_reg); | |
74791a2d NF |
796 | if (atmci_is_mci2()) |
797 | mci_writel(host, CFG, host->cfg_reg); | |
965ebf33 HS |
798 | host->need_reset = false; |
799 | } | |
800 | mci_writel(host, SDCR, slot->sdc_reg); | |
801 | ||
802 | iflags = mci_readl(host, IMR); | |
88ff82ed | 803 | if (iflags & ~(MCI_SDIOIRQA | MCI_SDIOIRQB)) |
965ebf33 HS |
804 | dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", |
805 | iflags); | |
806 | ||
807 | if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { | |
808 | /* Send init sequence (74 clock cycles) */ | |
809 | mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT); | |
810 | while (!(mci_readl(host, SR) & MCI_CMDRDY)) | |
811 | cpu_relax(); | |
812 | } | |
74791a2d | 813 | iflags = 0; |
7d2be074 HS |
814 | data = mrq->data; |
815 | if (data) { | |
965ebf33 | 816 | atmci_set_timeout(host, slot, data); |
a252e3e3 HS |
817 | |
818 | /* Must set block count/size before sending command */ | |
819 | mci_writel(host, BLKR, MCI_BCNT(data->blocks) | |
820 | | MCI_BLKLEN(data->blksz)); | |
965ebf33 HS |
821 | dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", |
822 | MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz)); | |
74791a2d NF |
823 | |
824 | iflags |= atmci_prepare_data(host, data); | |
7d2be074 HS |
825 | } |
826 | ||
74791a2d | 827 | iflags |= MCI_CMDRDY; |
7d2be074 | 828 | cmd = mrq->cmd; |
965ebf33 | 829 | cmdflags = atmci_prepare_command(slot->mmc, cmd); |
7d2be074 HS |
830 | atmci_start_command(host, cmd, cmdflags); |
831 | ||
832 | if (data) | |
74791a2d | 833 | atmci_submit_data(host); |
7d2be074 HS |
834 | |
835 | if (mrq->stop) { | |
965ebf33 | 836 | host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); |
7d2be074 HS |
837 | host->stop_cmdr |= MCI_CMDR_STOP_XFER; |
838 | if (!(data->flags & MMC_DATA_WRITE)) | |
839 | host->stop_cmdr |= MCI_CMDR_TRDIR_READ; | |
840 | if (data->flags & MMC_DATA_STREAM) | |
841 | host->stop_cmdr |= MCI_CMDR_STREAM; | |
842 | else | |
843 | host->stop_cmdr |= MCI_CMDR_MULTI_BLOCK; | |
844 | } | |
845 | ||
846 | /* | |
847 | * We could have enabled interrupts earlier, but I suspect | |
848 | * that would open up a nice can of interesting race | |
849 | * conditions (e.g. command and data complete, but stop not | |
850 | * prepared yet.) | |
851 | */ | |
852 | mci_writel(host, IER, iflags); | |
965ebf33 | 853 | } |
7d2be074 | 854 | |
965ebf33 HS |
855 | static void atmci_queue_request(struct atmel_mci *host, |
856 | struct atmel_mci_slot *slot, struct mmc_request *mrq) | |
857 | { | |
858 | dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", | |
859 | host->state); | |
860 | ||
861 | spin_lock_bh(&host->lock); | |
862 | slot->mrq = mrq; | |
863 | if (host->state == STATE_IDLE) { | |
864 | host->state = STATE_SENDING_CMD; | |
865 | atmci_start_request(host, slot); | |
866 | } else { | |
867 | list_add_tail(&slot->queue_node, &host->queue); | |
868 | } | |
869 | spin_unlock_bh(&host->lock); | |
870 | } | |
7d2be074 | 871 | |
965ebf33 HS |
872 | static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
873 | { | |
874 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
875 | struct atmel_mci *host = slot->host; | |
876 | struct mmc_data *data; | |
877 | ||
878 | WARN_ON(slot->mrq); | |
879 | ||
880 | /* | |
881 | * We may "know" the card is gone even though there's still an | |
882 | * electrical connection. If so, we really need to communicate | |
883 | * this to the MMC core since there won't be any more | |
884 | * interrupts as the card is completely removed. Otherwise, | |
885 | * the MMC core might believe the card is still there even | |
886 | * though the card was just removed very slowly. | |
887 | */ | |
888 | if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { | |
889 | mrq->cmd->error = -ENOMEDIUM; | |
890 | mmc_request_done(mmc, mrq); | |
891 | return; | |
892 | } | |
893 | ||
894 | /* We don't support multiple blocks of weird lengths. */ | |
895 | data = mrq->data; | |
896 | if (data && data->blocks > 1 && data->blksz & 3) { | |
897 | mrq->cmd->error = -EINVAL; | |
898 | mmc_request_done(mmc, mrq); | |
899 | } | |
900 | ||
901 | atmci_queue_request(host, slot, mrq); | |
7d2be074 HS |
902 | } |
903 | ||
904 | static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
905 | { | |
965ebf33 HS |
906 | struct atmel_mci_slot *slot = mmc_priv(mmc); |
907 | struct atmel_mci *host = slot->host; | |
908 | unsigned int i; | |
7d2be074 | 909 | |
965ebf33 | 910 | slot->sdc_reg &= ~MCI_SDCBUS_MASK; |
945533b5 HS |
911 | switch (ios->bus_width) { |
912 | case MMC_BUS_WIDTH_1: | |
965ebf33 | 913 | slot->sdc_reg |= MCI_SDCBUS_1BIT; |
945533b5 HS |
914 | break; |
915 | case MMC_BUS_WIDTH_4: | |
32ab83a5 | 916 | slot->sdc_reg |= MCI_SDCBUS_4BIT; |
945533b5 HS |
917 | break; |
918 | } | |
919 | ||
7d2be074 | 920 | if (ios->clock) { |
965ebf33 | 921 | unsigned int clock_min = ~0U; |
7d2be074 HS |
922 | u32 clkdiv; |
923 | ||
965ebf33 HS |
924 | spin_lock_bh(&host->lock); |
925 | if (!host->mode_reg) { | |
945533b5 | 926 | clk_enable(host->mck); |
965ebf33 HS |
927 | mci_writel(host, CR, MCI_CR_SWRST); |
928 | mci_writel(host, CR, MCI_CR_MCIEN); | |
74791a2d NF |
929 | if (atmci_is_mci2()) |
930 | mci_writel(host, CFG, host->cfg_reg); | |
965ebf33 | 931 | } |
945533b5 | 932 | |
965ebf33 HS |
933 | /* |
934 | * Use mirror of ios->clock to prevent race with mmc | |
935 | * core ios update when finding the minimum. | |
936 | */ | |
937 | slot->clock = ios->clock; | |
938 | for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { | |
939 | if (host->slot[i] && host->slot[i]->clock | |
940 | && host->slot[i]->clock < clock_min) | |
941 | clock_min = host->slot[i]->clock; | |
942 | } | |
943 | ||
944 | /* Calculate clock divider */ | |
945 | clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; | |
7d2be074 HS |
946 | if (clkdiv > 255) { |
947 | dev_warn(&mmc->class_dev, | |
948 | "clock %u too slow; using %lu\n", | |
965ebf33 | 949 | clock_min, host->bus_hz / (2 * 256)); |
7d2be074 HS |
950 | clkdiv = 255; |
951 | } | |
952 | ||
04d699c3 RE |
953 | host->mode_reg = MCI_MR_CLKDIV(clkdiv); |
954 | ||
965ebf33 HS |
955 | /* |
956 | * WRPROOF and RDPROOF prevent overruns/underruns by | |
957 | * stopping the clock when the FIFO is full/empty. | |
958 | * This state is not expected to last for long. | |
959 | */ | |
04d699c3 RE |
960 | if (mci_has_rwproof()) |
961 | host->mode_reg |= (MCI_MR_WRPROOF | MCI_MR_RDPROOF); | |
7d2be074 | 962 | |
99ddffd8 NF |
963 | if (atmci_is_mci2()) { |
964 | /* setup High Speed mode in relation with card capacity */ | |
965 | if (ios->timing == MMC_TIMING_SD_HS) | |
966 | host->cfg_reg |= MCI_CFG_HSMODE; | |
967 | else | |
968 | host->cfg_reg &= ~MCI_CFG_HSMODE; | |
969 | } | |
970 | ||
971 | if (list_empty(&host->queue)) { | |
965ebf33 | 972 | mci_writel(host, MR, host->mode_reg); |
99ddffd8 NF |
973 | if (atmci_is_mci2()) |
974 | mci_writel(host, CFG, host->cfg_reg); | |
975 | } else { | |
965ebf33 | 976 | host->need_clock_update = true; |
99ddffd8 | 977 | } |
965ebf33 HS |
978 | |
979 | spin_unlock_bh(&host->lock); | |
945533b5 | 980 | } else { |
965ebf33 HS |
981 | bool any_slot_active = false; |
982 | ||
983 | spin_lock_bh(&host->lock); | |
984 | slot->clock = 0; | |
985 | for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { | |
986 | if (host->slot[i] && host->slot[i]->clock) { | |
987 | any_slot_active = true; | |
988 | break; | |
989 | } | |
945533b5 | 990 | } |
965ebf33 HS |
991 | if (!any_slot_active) { |
992 | mci_writel(host, CR, MCI_CR_MCIDIS); | |
993 | if (host->mode_reg) { | |
994 | mci_readl(host, MR); | |
995 | clk_disable(host->mck); | |
996 | } | |
997 | host->mode_reg = 0; | |
998 | } | |
999 | spin_unlock_bh(&host->lock); | |
7d2be074 HS |
1000 | } |
1001 | ||
1002 | switch (ios->power_mode) { | |
965ebf33 HS |
1003 | case MMC_POWER_UP: |
1004 | set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); | |
1005 | break; | |
7d2be074 HS |
1006 | default: |
1007 | /* | |
1008 | * TODO: None of the currently available AVR32-based | |
1009 | * boards allow MMC power to be turned off. Implement | |
1010 | * power control when this can be tested properly. | |
965ebf33 HS |
1011 | * |
1012 | * We also need to hook this into the clock management | |
1013 | * somehow so that newly inserted cards aren't | |
1014 | * subjected to a fast clock before we have a chance | |
1015 | * to figure out what the maximum rate is. Currently, | |
1016 | * there's no way to avoid this, and there never will | |
1017 | * be for boards that don't support power control. | |
7d2be074 HS |
1018 | */ |
1019 | break; | |
1020 | } | |
1021 | } | |
1022 | ||
1023 | static int atmci_get_ro(struct mmc_host *mmc) | |
1024 | { | |
965ebf33 HS |
1025 | int read_only = -ENOSYS; |
1026 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
7d2be074 | 1027 | |
965ebf33 HS |
1028 | if (gpio_is_valid(slot->wp_pin)) { |
1029 | read_only = gpio_get_value(slot->wp_pin); | |
7d2be074 HS |
1030 | dev_dbg(&mmc->class_dev, "card is %s\n", |
1031 | read_only ? "read-only" : "read-write"); | |
7d2be074 HS |
1032 | } |
1033 | ||
1034 | return read_only; | |
1035 | } | |
1036 | ||
965ebf33 HS |
1037 | static int atmci_get_cd(struct mmc_host *mmc) |
1038 | { | |
1039 | int present = -ENOSYS; | |
1040 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
1041 | ||
1042 | if (gpio_is_valid(slot->detect_pin)) { | |
1c1452be JL |
1043 | present = !(gpio_get_value(slot->detect_pin) ^ |
1044 | slot->detect_is_active_high); | |
965ebf33 HS |
1045 | dev_dbg(&mmc->class_dev, "card is %spresent\n", |
1046 | present ? "" : "not "); | |
1047 | } | |
1048 | ||
1049 | return present; | |
1050 | } | |
1051 | ||
88ff82ed AG |
1052 | static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1053 | { | |
1054 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
1055 | struct atmel_mci *host = slot->host; | |
1056 | ||
1057 | if (enable) | |
1058 | mci_writel(host, IER, slot->sdio_irq); | |
1059 | else | |
1060 | mci_writel(host, IDR, slot->sdio_irq); | |
1061 | } | |
1062 | ||
965ebf33 | 1063 | static const struct mmc_host_ops atmci_ops = { |
7d2be074 HS |
1064 | .request = atmci_request, |
1065 | .set_ios = atmci_set_ios, | |
1066 | .get_ro = atmci_get_ro, | |
965ebf33 | 1067 | .get_cd = atmci_get_cd, |
88ff82ed | 1068 | .enable_sdio_irq = atmci_enable_sdio_irq, |
7d2be074 HS |
1069 | }; |
1070 | ||
965ebf33 HS |
1071 | /* Called with host->lock held */ |
1072 | static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) | |
1073 | __releases(&host->lock) | |
1074 | __acquires(&host->lock) | |
1075 | { | |
1076 | struct atmel_mci_slot *slot = NULL; | |
1077 | struct mmc_host *prev_mmc = host->cur_slot->mmc; | |
1078 | ||
1079 | WARN_ON(host->cmd || host->data); | |
1080 | ||
1081 | /* | |
1082 | * Update the MMC clock rate if necessary. This may be | |
1083 | * necessary if set_ios() is called when a different slot is | |
1084 | * busy transfering data. | |
1085 | */ | |
99ddffd8 | 1086 | if (host->need_clock_update) { |
965ebf33 | 1087 | mci_writel(host, MR, host->mode_reg); |
99ddffd8 NF |
1088 | if (atmci_is_mci2()) |
1089 | mci_writel(host, CFG, host->cfg_reg); | |
1090 | } | |
965ebf33 HS |
1091 | |
1092 | host->cur_slot->mrq = NULL; | |
1093 | host->mrq = NULL; | |
1094 | if (!list_empty(&host->queue)) { | |
1095 | slot = list_entry(host->queue.next, | |
1096 | struct atmel_mci_slot, queue_node); | |
1097 | list_del(&slot->queue_node); | |
1098 | dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", | |
1099 | mmc_hostname(slot->mmc)); | |
1100 | host->state = STATE_SENDING_CMD; | |
1101 | atmci_start_request(host, slot); | |
1102 | } else { | |
1103 | dev_vdbg(&host->pdev->dev, "list empty\n"); | |
1104 | host->state = STATE_IDLE; | |
1105 | } | |
1106 | ||
1107 | spin_unlock(&host->lock); | |
1108 | mmc_request_done(prev_mmc, mrq); | |
1109 | spin_lock(&host->lock); | |
1110 | } | |
1111 | ||
7d2be074 | 1112 | static void atmci_command_complete(struct atmel_mci *host, |
c06ad258 | 1113 | struct mmc_command *cmd) |
7d2be074 | 1114 | { |
c06ad258 HS |
1115 | u32 status = host->cmd_status; |
1116 | ||
7d2be074 HS |
1117 | /* Read the response from the card (up to 16 bytes) */ |
1118 | cmd->resp[0] = mci_readl(host, RSPR); | |
1119 | cmd->resp[1] = mci_readl(host, RSPR); | |
1120 | cmd->resp[2] = mci_readl(host, RSPR); | |
1121 | cmd->resp[3] = mci_readl(host, RSPR); | |
1122 | ||
1123 | if (status & MCI_RTOE) | |
1124 | cmd->error = -ETIMEDOUT; | |
1125 | else if ((cmd->flags & MMC_RSP_CRC) && (status & MCI_RCRCE)) | |
1126 | cmd->error = -EILSEQ; | |
1127 | else if (status & (MCI_RINDE | MCI_RDIRE | MCI_RENDE)) | |
1128 | cmd->error = -EIO; | |
1129 | else | |
1130 | cmd->error = 0; | |
1131 | ||
1132 | if (cmd->error) { | |
965ebf33 | 1133 | dev_dbg(&host->pdev->dev, |
7d2be074 HS |
1134 | "command error: status=0x%08x\n", status); |
1135 | ||
1136 | if (cmd->data) { | |
65e8b083 | 1137 | atmci_stop_dma(host); |
009a891b | 1138 | host->data = NULL; |
7d2be074 HS |
1139 | mci_writel(host, IDR, MCI_NOTBUSY |
1140 | | MCI_TXRDY | MCI_RXRDY | |
1141 | | ATMCI_DATA_ERROR_FLAGS); | |
1142 | } | |
1143 | } | |
1144 | } | |
1145 | ||
1146 | static void atmci_detect_change(unsigned long data) | |
1147 | { | |
965ebf33 HS |
1148 | struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data; |
1149 | bool present; | |
1150 | bool present_old; | |
7d2be074 HS |
1151 | |
1152 | /* | |
965ebf33 HS |
1153 | * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before |
1154 | * freeing the interrupt. We must not re-enable the interrupt | |
1155 | * if it has been freed, and if we're shutting down, it | |
1156 | * doesn't really matter whether the card is present or not. | |
7d2be074 HS |
1157 | */ |
1158 | smp_rmb(); | |
965ebf33 | 1159 | if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) |
7d2be074 HS |
1160 | return; |
1161 | ||
965ebf33 | 1162 | enable_irq(gpio_to_irq(slot->detect_pin)); |
1c1452be JL |
1163 | present = !(gpio_get_value(slot->detect_pin) ^ |
1164 | slot->detect_is_active_high); | |
965ebf33 | 1165 | present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); |
7d2be074 | 1166 | |
965ebf33 HS |
1167 | dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", |
1168 | present, present_old); | |
7d2be074 | 1169 | |
965ebf33 HS |
1170 | if (present != present_old) { |
1171 | struct atmel_mci *host = slot->host; | |
1172 | struct mmc_request *mrq; | |
1173 | ||
1174 | dev_dbg(&slot->mmc->class_dev, "card %s\n", | |
7d2be074 | 1175 | present ? "inserted" : "removed"); |
7d2be074 | 1176 | |
965ebf33 HS |
1177 | spin_lock(&host->lock); |
1178 | ||
1179 | if (!present) | |
1180 | clear_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
1181 | else | |
1182 | set_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
7d2be074 HS |
1183 | |
1184 | /* Clean up queue if present */ | |
965ebf33 | 1185 | mrq = slot->mrq; |
7d2be074 | 1186 | if (mrq) { |
965ebf33 HS |
1187 | if (mrq == host->mrq) { |
1188 | /* | |
1189 | * Reset controller to terminate any ongoing | |
1190 | * commands or data transfers. | |
1191 | */ | |
1192 | mci_writel(host, CR, MCI_CR_SWRST); | |
1193 | mci_writel(host, CR, MCI_CR_MCIEN); | |
1194 | mci_writel(host, MR, host->mode_reg); | |
74791a2d NF |
1195 | if (atmci_is_mci2()) |
1196 | mci_writel(host, CFG, host->cfg_reg); | |
965ebf33 HS |
1197 | |
1198 | host->data = NULL; | |
1199 | host->cmd = NULL; | |
1200 | ||
1201 | switch (host->state) { | |
1202 | case STATE_IDLE: | |
c06ad258 | 1203 | break; |
965ebf33 HS |
1204 | case STATE_SENDING_CMD: |
1205 | mrq->cmd->error = -ENOMEDIUM; | |
1206 | if (!mrq->data) | |
1207 | break; | |
1208 | /* fall through */ | |
1209 | case STATE_SENDING_DATA: | |
c06ad258 | 1210 | mrq->data->error = -ENOMEDIUM; |
65e8b083 | 1211 | atmci_stop_dma(host); |
c06ad258 | 1212 | break; |
965ebf33 HS |
1213 | case STATE_DATA_BUSY: |
1214 | case STATE_DATA_ERROR: | |
1215 | if (mrq->data->error == -EINPROGRESS) | |
1216 | mrq->data->error = -ENOMEDIUM; | |
1217 | if (!mrq->stop) | |
1218 | break; | |
1219 | /* fall through */ | |
1220 | case STATE_SENDING_STOP: | |
1221 | mrq->stop->error = -ENOMEDIUM; | |
1222 | break; | |
1223 | } | |
7d2be074 | 1224 | |
965ebf33 HS |
1225 | atmci_request_end(host, mrq); |
1226 | } else { | |
1227 | list_del(&slot->queue_node); | |
1228 | mrq->cmd->error = -ENOMEDIUM; | |
1229 | if (mrq->data) | |
1230 | mrq->data->error = -ENOMEDIUM; | |
1231 | if (mrq->stop) | |
1232 | mrq->stop->error = -ENOMEDIUM; | |
1233 | ||
1234 | spin_unlock(&host->lock); | |
1235 | mmc_request_done(slot->mmc, mrq); | |
1236 | spin_lock(&host->lock); | |
1237 | } | |
7d2be074 | 1238 | } |
965ebf33 | 1239 | spin_unlock(&host->lock); |
7d2be074 | 1240 | |
965ebf33 | 1241 | mmc_detect_change(slot->mmc, 0); |
7d2be074 HS |
1242 | } |
1243 | } | |
1244 | ||
1245 | static void atmci_tasklet_func(unsigned long priv) | |
1246 | { | |
965ebf33 | 1247 | struct atmel_mci *host = (struct atmel_mci *)priv; |
7d2be074 HS |
1248 | struct mmc_request *mrq = host->mrq; |
1249 | struct mmc_data *data = host->data; | |
c06ad258 HS |
1250 | struct mmc_command *cmd = host->cmd; |
1251 | enum atmel_mci_state state = host->state; | |
1252 | enum atmel_mci_state prev_state; | |
1253 | u32 status; | |
1254 | ||
965ebf33 HS |
1255 | spin_lock(&host->lock); |
1256 | ||
c06ad258 | 1257 | state = host->state; |
7d2be074 | 1258 | |
965ebf33 | 1259 | dev_vdbg(&host->pdev->dev, |
c06ad258 HS |
1260 | "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", |
1261 | state, host->pending_events, host->completed_events, | |
7d2be074 HS |
1262 | mci_readl(host, IMR)); |
1263 | ||
c06ad258 HS |
1264 | do { |
1265 | prev_state = state; | |
7d2be074 | 1266 | |
c06ad258 | 1267 | switch (state) { |
965ebf33 HS |
1268 | case STATE_IDLE: |
1269 | break; | |
1270 | ||
c06ad258 HS |
1271 | case STATE_SENDING_CMD: |
1272 | if (!atmci_test_and_clear_pending(host, | |
1273 | EVENT_CMD_COMPLETE)) | |
1274 | break; | |
7d2be074 | 1275 | |
c06ad258 HS |
1276 | host->cmd = NULL; |
1277 | atmci_set_completed(host, EVENT_CMD_COMPLETE); | |
1278 | atmci_command_complete(host, mrq->cmd); | |
1279 | if (!mrq->data || cmd->error) { | |
965ebf33 HS |
1280 | atmci_request_end(host, host->mrq); |
1281 | goto unlock; | |
c06ad258 | 1282 | } |
7d2be074 | 1283 | |
c06ad258 HS |
1284 | prev_state = state = STATE_SENDING_DATA; |
1285 | /* fall through */ | |
7d2be074 | 1286 | |
c06ad258 HS |
1287 | case STATE_SENDING_DATA: |
1288 | if (atmci_test_and_clear_pending(host, | |
1289 | EVENT_DATA_ERROR)) { | |
65e8b083 | 1290 | atmci_stop_dma(host); |
c06ad258 | 1291 | if (data->stop) |
965ebf33 | 1292 | send_stop_cmd(host, data); |
c06ad258 HS |
1293 | state = STATE_DATA_ERROR; |
1294 | break; | |
1295 | } | |
7d2be074 | 1296 | |
c06ad258 HS |
1297 | if (!atmci_test_and_clear_pending(host, |
1298 | EVENT_XFER_COMPLETE)) | |
1299 | break; | |
7d2be074 | 1300 | |
c06ad258 HS |
1301 | atmci_set_completed(host, EVENT_XFER_COMPLETE); |
1302 | prev_state = state = STATE_DATA_BUSY; | |
1303 | /* fall through */ | |
7d2be074 | 1304 | |
c06ad258 HS |
1305 | case STATE_DATA_BUSY: |
1306 | if (!atmci_test_and_clear_pending(host, | |
1307 | EVENT_DATA_COMPLETE)) | |
1308 | break; | |
1309 | ||
1310 | host->data = NULL; | |
1311 | atmci_set_completed(host, EVENT_DATA_COMPLETE); | |
1312 | status = host->data_status; | |
1313 | if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) { | |
1314 | if (status & MCI_DTOE) { | |
965ebf33 | 1315 | dev_dbg(&host->pdev->dev, |
c06ad258 HS |
1316 | "data timeout error\n"); |
1317 | data->error = -ETIMEDOUT; | |
1318 | } else if (status & MCI_DCRCE) { | |
965ebf33 | 1319 | dev_dbg(&host->pdev->dev, |
c06ad258 HS |
1320 | "data CRC error\n"); |
1321 | data->error = -EILSEQ; | |
1322 | } else { | |
965ebf33 | 1323 | dev_dbg(&host->pdev->dev, |
c06ad258 HS |
1324 | "data FIFO error (status=%08x)\n", |
1325 | status); | |
1326 | data->error = -EIO; | |
1327 | } | |
1328 | } else { | |
1329 | data->bytes_xfered = data->blocks * data->blksz; | |
1330 | data->error = 0; | |
abc2c9fd | 1331 | mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS); |
c06ad258 HS |
1332 | } |
1333 | ||
1334 | if (!data->stop) { | |
965ebf33 HS |
1335 | atmci_request_end(host, host->mrq); |
1336 | goto unlock; | |
c06ad258 | 1337 | } |
7d2be074 | 1338 | |
c06ad258 HS |
1339 | prev_state = state = STATE_SENDING_STOP; |
1340 | if (!data->error) | |
965ebf33 | 1341 | send_stop_cmd(host, data); |
c06ad258 HS |
1342 | /* fall through */ |
1343 | ||
1344 | case STATE_SENDING_STOP: | |
1345 | if (!atmci_test_and_clear_pending(host, | |
1346 | EVENT_CMD_COMPLETE)) | |
1347 | break; | |
1348 | ||
1349 | host->cmd = NULL; | |
1350 | atmci_command_complete(host, mrq->stop); | |
965ebf33 HS |
1351 | atmci_request_end(host, host->mrq); |
1352 | goto unlock; | |
c06ad258 HS |
1353 | |
1354 | case STATE_DATA_ERROR: | |
1355 | if (!atmci_test_and_clear_pending(host, | |
1356 | EVENT_XFER_COMPLETE)) | |
1357 | break; | |
1358 | ||
1359 | state = STATE_DATA_BUSY; | |
1360 | break; | |
1361 | } | |
1362 | } while (state != prev_state); | |
1363 | ||
1364 | host->state = state; | |
965ebf33 HS |
1365 | |
1366 | unlock: | |
1367 | spin_unlock(&host->lock); | |
7d2be074 HS |
1368 | } |
1369 | ||
1370 | static void atmci_read_data_pio(struct atmel_mci *host) | |
1371 | { | |
1372 | struct scatterlist *sg = host->sg; | |
1373 | void *buf = sg_virt(sg); | |
1374 | unsigned int offset = host->pio_offset; | |
1375 | struct mmc_data *data = host->data; | |
1376 | u32 value; | |
1377 | u32 status; | |
1378 | unsigned int nbytes = 0; | |
1379 | ||
1380 | do { | |
1381 | value = mci_readl(host, RDR); | |
1382 | if (likely(offset + 4 <= sg->length)) { | |
1383 | put_unaligned(value, (u32 *)(buf + offset)); | |
1384 | ||
1385 | offset += 4; | |
1386 | nbytes += 4; | |
1387 | ||
1388 | if (offset == sg->length) { | |
5e7184ae | 1389 | flush_dcache_page(sg_page(sg)); |
7d2be074 HS |
1390 | host->sg = sg = sg_next(sg); |
1391 | if (!sg) | |
1392 | goto done; | |
1393 | ||
1394 | offset = 0; | |
1395 | buf = sg_virt(sg); | |
1396 | } | |
1397 | } else { | |
1398 | unsigned int remaining = sg->length - offset; | |
1399 | memcpy(buf + offset, &value, remaining); | |
1400 | nbytes += remaining; | |
1401 | ||
1402 | flush_dcache_page(sg_page(sg)); | |
1403 | host->sg = sg = sg_next(sg); | |
1404 | if (!sg) | |
1405 | goto done; | |
1406 | ||
1407 | offset = 4 - remaining; | |
1408 | buf = sg_virt(sg); | |
1409 | memcpy(buf, (u8 *)&value + remaining, offset); | |
1410 | nbytes += offset; | |
1411 | } | |
1412 | ||
1413 | status = mci_readl(host, SR); | |
1414 | if (status & ATMCI_DATA_ERROR_FLAGS) { | |
1415 | mci_writel(host, IDR, (MCI_NOTBUSY | MCI_RXRDY | |
1416 | | ATMCI_DATA_ERROR_FLAGS)); | |
1417 | host->data_status = status; | |
965ebf33 HS |
1418 | data->bytes_xfered += nbytes; |
1419 | smp_wmb(); | |
7d2be074 HS |
1420 | atmci_set_pending(host, EVENT_DATA_ERROR); |
1421 | tasklet_schedule(&host->tasklet); | |
965ebf33 | 1422 | return; |
7d2be074 HS |
1423 | } |
1424 | } while (status & MCI_RXRDY); | |
1425 | ||
1426 | host->pio_offset = offset; | |
1427 | data->bytes_xfered += nbytes; | |
1428 | ||
1429 | return; | |
1430 | ||
1431 | done: | |
1432 | mci_writel(host, IDR, MCI_RXRDY); | |
1433 | mci_writel(host, IER, MCI_NOTBUSY); | |
1434 | data->bytes_xfered += nbytes; | |
965ebf33 | 1435 | smp_wmb(); |
c06ad258 | 1436 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
7d2be074 HS |
1437 | } |
1438 | ||
1439 | static void atmci_write_data_pio(struct atmel_mci *host) | |
1440 | { | |
1441 | struct scatterlist *sg = host->sg; | |
1442 | void *buf = sg_virt(sg); | |
1443 | unsigned int offset = host->pio_offset; | |
1444 | struct mmc_data *data = host->data; | |
1445 | u32 value; | |
1446 | u32 status; | |
1447 | unsigned int nbytes = 0; | |
1448 | ||
1449 | do { | |
1450 | if (likely(offset + 4 <= sg->length)) { | |
1451 | value = get_unaligned((u32 *)(buf + offset)); | |
1452 | mci_writel(host, TDR, value); | |
1453 | ||
1454 | offset += 4; | |
1455 | nbytes += 4; | |
1456 | if (offset == sg->length) { | |
1457 | host->sg = sg = sg_next(sg); | |
1458 | if (!sg) | |
1459 | goto done; | |
1460 | ||
1461 | offset = 0; | |
1462 | buf = sg_virt(sg); | |
1463 | } | |
1464 | } else { | |
1465 | unsigned int remaining = sg->length - offset; | |
1466 | ||
1467 | value = 0; | |
1468 | memcpy(&value, buf + offset, remaining); | |
1469 | nbytes += remaining; | |
1470 | ||
1471 | host->sg = sg = sg_next(sg); | |
1472 | if (!sg) { | |
1473 | mci_writel(host, TDR, value); | |
1474 | goto done; | |
1475 | } | |
1476 | ||
1477 | offset = 4 - remaining; | |
1478 | buf = sg_virt(sg); | |
1479 | memcpy((u8 *)&value + remaining, buf, offset); | |
1480 | mci_writel(host, TDR, value); | |
1481 | nbytes += offset; | |
1482 | } | |
1483 | ||
1484 | status = mci_readl(host, SR); | |
1485 | if (status & ATMCI_DATA_ERROR_FLAGS) { | |
1486 | mci_writel(host, IDR, (MCI_NOTBUSY | MCI_TXRDY | |
1487 | | ATMCI_DATA_ERROR_FLAGS)); | |
1488 | host->data_status = status; | |
965ebf33 HS |
1489 | data->bytes_xfered += nbytes; |
1490 | smp_wmb(); | |
7d2be074 HS |
1491 | atmci_set_pending(host, EVENT_DATA_ERROR); |
1492 | tasklet_schedule(&host->tasklet); | |
965ebf33 | 1493 | return; |
7d2be074 HS |
1494 | } |
1495 | } while (status & MCI_TXRDY); | |
1496 | ||
1497 | host->pio_offset = offset; | |
1498 | data->bytes_xfered += nbytes; | |
1499 | ||
1500 | return; | |
1501 | ||
1502 | done: | |
1503 | mci_writel(host, IDR, MCI_TXRDY); | |
1504 | mci_writel(host, IER, MCI_NOTBUSY); | |
1505 | data->bytes_xfered += nbytes; | |
965ebf33 | 1506 | smp_wmb(); |
c06ad258 | 1507 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
7d2be074 HS |
1508 | } |
1509 | ||
965ebf33 | 1510 | static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status) |
7d2be074 | 1511 | { |
7d2be074 HS |
1512 | mci_writel(host, IDR, MCI_CMDRDY); |
1513 | ||
c06ad258 | 1514 | host->cmd_status = status; |
965ebf33 | 1515 | smp_wmb(); |
c06ad258 | 1516 | atmci_set_pending(host, EVENT_CMD_COMPLETE); |
7d2be074 HS |
1517 | tasklet_schedule(&host->tasklet); |
1518 | } | |
1519 | ||
88ff82ed AG |
1520 | static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status) |
1521 | { | |
1522 | int i; | |
1523 | ||
1524 | for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { | |
1525 | struct atmel_mci_slot *slot = host->slot[i]; | |
1526 | if (slot && (status & slot->sdio_irq)) { | |
1527 | mmc_signal_sdio_irq(slot->mmc); | |
1528 | } | |
1529 | } | |
1530 | } | |
1531 | ||
1532 | ||
7d2be074 HS |
1533 | static irqreturn_t atmci_interrupt(int irq, void *dev_id) |
1534 | { | |
965ebf33 | 1535 | struct atmel_mci *host = dev_id; |
7d2be074 HS |
1536 | u32 status, mask, pending; |
1537 | unsigned int pass_count = 0; | |
1538 | ||
7d2be074 HS |
1539 | do { |
1540 | status = mci_readl(host, SR); | |
1541 | mask = mci_readl(host, IMR); | |
1542 | pending = status & mask; | |
1543 | if (!pending) | |
1544 | break; | |
1545 | ||
1546 | if (pending & ATMCI_DATA_ERROR_FLAGS) { | |
1547 | mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS | |
1548 | | MCI_RXRDY | MCI_TXRDY); | |
1549 | pending &= mci_readl(host, IMR); | |
965ebf33 | 1550 | |
7d2be074 | 1551 | host->data_status = status; |
965ebf33 | 1552 | smp_wmb(); |
7d2be074 HS |
1553 | atmci_set_pending(host, EVENT_DATA_ERROR); |
1554 | tasklet_schedule(&host->tasklet); | |
1555 | } | |
1556 | if (pending & MCI_NOTBUSY) { | |
c06ad258 HS |
1557 | mci_writel(host, IDR, |
1558 | ATMCI_DATA_ERROR_FLAGS | MCI_NOTBUSY); | |
ca55f46e HS |
1559 | if (!host->data_status) |
1560 | host->data_status = status; | |
965ebf33 | 1561 | smp_wmb(); |
7d2be074 HS |
1562 | atmci_set_pending(host, EVENT_DATA_COMPLETE); |
1563 | tasklet_schedule(&host->tasklet); | |
1564 | } | |
1565 | if (pending & MCI_RXRDY) | |
1566 | atmci_read_data_pio(host); | |
1567 | if (pending & MCI_TXRDY) | |
1568 | atmci_write_data_pio(host); | |
1569 | ||
1570 | if (pending & MCI_CMDRDY) | |
965ebf33 | 1571 | atmci_cmd_interrupt(host, status); |
88ff82ed AG |
1572 | |
1573 | if (pending & (MCI_SDIOIRQA | MCI_SDIOIRQB)) | |
1574 | atmci_sdio_interrupt(host, status); | |
1575 | ||
7d2be074 HS |
1576 | } while (pass_count++ < 5); |
1577 | ||
7d2be074 HS |
1578 | return pass_count ? IRQ_HANDLED : IRQ_NONE; |
1579 | } | |
1580 | ||
1581 | static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) | |
1582 | { | |
965ebf33 | 1583 | struct atmel_mci_slot *slot = dev_id; |
7d2be074 HS |
1584 | |
1585 | /* | |
1586 | * Disable interrupts until the pin has stabilized and check | |
1587 | * the state then. Use mod_timer() since we may be in the | |
1588 | * middle of the timer routine when this interrupt triggers. | |
1589 | */ | |
1590 | disable_irq_nosync(irq); | |
965ebf33 | 1591 | mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); |
7d2be074 HS |
1592 | |
1593 | return IRQ_HANDLED; | |
1594 | } | |
1595 | ||
965ebf33 HS |
1596 | static int __init atmci_init_slot(struct atmel_mci *host, |
1597 | struct mci_slot_pdata *slot_data, unsigned int id, | |
88ff82ed | 1598 | u32 sdc_reg, u32 sdio_irq) |
965ebf33 HS |
1599 | { |
1600 | struct mmc_host *mmc; | |
1601 | struct atmel_mci_slot *slot; | |
1602 | ||
1603 | mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); | |
1604 | if (!mmc) | |
1605 | return -ENOMEM; | |
1606 | ||
1607 | slot = mmc_priv(mmc); | |
1608 | slot->mmc = mmc; | |
1609 | slot->host = host; | |
1610 | slot->detect_pin = slot_data->detect_pin; | |
1611 | slot->wp_pin = slot_data->wp_pin; | |
1c1452be | 1612 | slot->detect_is_active_high = slot_data->detect_is_active_high; |
965ebf33 | 1613 | slot->sdc_reg = sdc_reg; |
88ff82ed | 1614 | slot->sdio_irq = sdio_irq; |
965ebf33 HS |
1615 | |
1616 | mmc->ops = &atmci_ops; | |
1617 | mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); | |
1618 | mmc->f_max = host->bus_hz / 2; | |
1619 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
88ff82ed AG |
1620 | if (sdio_irq) |
1621 | mmc->caps |= MMC_CAP_SDIO_IRQ; | |
99ddffd8 NF |
1622 | if (atmci_is_mci2()) |
1623 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; | |
965ebf33 HS |
1624 | if (slot_data->bus_width >= 4) |
1625 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1626 | ||
a36274e0 | 1627 | mmc->max_segs = 64; |
965ebf33 HS |
1628 | mmc->max_req_size = 32768 * 512; |
1629 | mmc->max_blk_size = 32768; | |
1630 | mmc->max_blk_count = 512; | |
1631 | ||
1632 | /* Assume card is present initially */ | |
1633 | set_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
1634 | if (gpio_is_valid(slot->detect_pin)) { | |
1635 | if (gpio_request(slot->detect_pin, "mmc_detect")) { | |
1636 | dev_dbg(&mmc->class_dev, "no detect pin available\n"); | |
1637 | slot->detect_pin = -EBUSY; | |
1c1452be JL |
1638 | } else if (gpio_get_value(slot->detect_pin) ^ |
1639 | slot->detect_is_active_high) { | |
965ebf33 HS |
1640 | clear_bit(ATMCI_CARD_PRESENT, &slot->flags); |
1641 | } | |
1642 | } | |
1643 | ||
1644 | if (!gpio_is_valid(slot->detect_pin)) | |
1645 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
1646 | ||
1647 | if (gpio_is_valid(slot->wp_pin)) { | |
1648 | if (gpio_request(slot->wp_pin, "mmc_wp")) { | |
1649 | dev_dbg(&mmc->class_dev, "no WP pin available\n"); | |
1650 | slot->wp_pin = -EBUSY; | |
1651 | } | |
1652 | } | |
1653 | ||
1654 | host->slot[id] = slot; | |
1655 | mmc_add_host(mmc); | |
1656 | ||
1657 | if (gpio_is_valid(slot->detect_pin)) { | |
1658 | int ret; | |
1659 | ||
1660 | setup_timer(&slot->detect_timer, atmci_detect_change, | |
1661 | (unsigned long)slot); | |
1662 | ||
1663 | ret = request_irq(gpio_to_irq(slot->detect_pin), | |
1664 | atmci_detect_interrupt, | |
1665 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | |
1666 | "mmc-detect", slot); | |
1667 | if (ret) { | |
1668 | dev_dbg(&mmc->class_dev, | |
1669 | "could not request IRQ %d for detect pin\n", | |
1670 | gpio_to_irq(slot->detect_pin)); | |
1671 | gpio_free(slot->detect_pin); | |
1672 | slot->detect_pin = -EBUSY; | |
1673 | } | |
1674 | } | |
1675 | ||
1676 | atmci_init_debugfs(slot); | |
1677 | ||
1678 | return 0; | |
1679 | } | |
1680 | ||
1681 | static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot, | |
1682 | unsigned int id) | |
1683 | { | |
1684 | /* Debugfs stuff is cleaned up by mmc core */ | |
1685 | ||
1686 | set_bit(ATMCI_SHUTDOWN, &slot->flags); | |
1687 | smp_wmb(); | |
1688 | ||
1689 | mmc_remove_host(slot->mmc); | |
1690 | ||
1691 | if (gpio_is_valid(slot->detect_pin)) { | |
1692 | int pin = slot->detect_pin; | |
1693 | ||
1694 | free_irq(gpio_to_irq(pin), slot); | |
1695 | del_timer_sync(&slot->detect_timer); | |
1696 | gpio_free(pin); | |
1697 | } | |
1698 | if (gpio_is_valid(slot->wp_pin)) | |
1699 | gpio_free(slot->wp_pin); | |
1700 | ||
1701 | slot->host->slot[id] = NULL; | |
1702 | mmc_free_host(slot->mmc); | |
1703 | } | |
1704 | ||
74465b4f | 1705 | #ifdef CONFIG_MMC_ATMELMCI_DMA |
7dd60251 | 1706 | static bool filter(struct dma_chan *chan, void *slave) |
74465b4f | 1707 | { |
2635d1ba | 1708 | struct mci_dma_data *sl = slave; |
74465b4f | 1709 | |
2635d1ba NF |
1710 | if (sl && find_slave_dev(sl) == chan->device->dev) { |
1711 | chan->private = slave_data_ptr(sl); | |
7dd60251 | 1712 | return true; |
2635d1ba | 1713 | } else { |
7dd60251 | 1714 | return false; |
2635d1ba | 1715 | } |
74465b4f | 1716 | } |
2635d1ba NF |
1717 | |
1718 | static void atmci_configure_dma(struct atmel_mci *host) | |
1719 | { | |
1720 | struct mci_platform_data *pdata; | |
1721 | ||
1722 | if (host == NULL) | |
1723 | return; | |
1724 | ||
1725 | pdata = host->pdev->dev.platform_data; | |
1726 | ||
1727 | if (pdata && find_slave_dev(pdata->dma_slave)) { | |
1728 | dma_cap_mask_t mask; | |
1729 | ||
1730 | setup_dma_addr(pdata->dma_slave, | |
1731 | host->mapbase + MCI_TDR, | |
1732 | host->mapbase + MCI_RDR); | |
1733 | ||
1734 | /* Try to grab a DMA channel */ | |
1735 | dma_cap_zero(mask); | |
1736 | dma_cap_set(DMA_SLAVE, mask); | |
1737 | host->dma.chan = | |
1738 | dma_request_channel(mask, filter, pdata->dma_slave); | |
1739 | } | |
1740 | if (!host->dma.chan) | |
1741 | dev_notice(&host->pdev->dev, "DMA not available, using PIO\n"); | |
74791a2d NF |
1742 | else |
1743 | dev_info(&host->pdev->dev, | |
1744 | "Using %s for DMA transfers\n", | |
1745 | dma_chan_name(host->dma.chan)); | |
2635d1ba NF |
1746 | } |
1747 | #else | |
1748 | static void atmci_configure_dma(struct atmel_mci *host) {} | |
74465b4f DW |
1749 | #endif |
1750 | ||
7d2be074 HS |
1751 | static int __init atmci_probe(struct platform_device *pdev) |
1752 | { | |
1753 | struct mci_platform_data *pdata; | |
965ebf33 HS |
1754 | struct atmel_mci *host; |
1755 | struct resource *regs; | |
1756 | unsigned int nr_slots; | |
1757 | int irq; | |
1758 | int ret; | |
7d2be074 HS |
1759 | |
1760 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1761 | if (!regs) | |
1762 | return -ENXIO; | |
1763 | pdata = pdev->dev.platform_data; | |
1764 | if (!pdata) | |
1765 | return -ENXIO; | |
1766 | irq = platform_get_irq(pdev, 0); | |
1767 | if (irq < 0) | |
1768 | return irq; | |
1769 | ||
965ebf33 HS |
1770 | host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL); |
1771 | if (!host) | |
7d2be074 HS |
1772 | return -ENOMEM; |
1773 | ||
7d2be074 | 1774 | host->pdev = pdev; |
965ebf33 HS |
1775 | spin_lock_init(&host->lock); |
1776 | INIT_LIST_HEAD(&host->queue); | |
7d2be074 HS |
1777 | |
1778 | host->mck = clk_get(&pdev->dev, "mci_clk"); | |
1779 | if (IS_ERR(host->mck)) { | |
1780 | ret = PTR_ERR(host->mck); | |
1781 | goto err_clk_get; | |
1782 | } | |
1783 | ||
1784 | ret = -ENOMEM; | |
e8e3f6ca | 1785 | host->regs = ioremap(regs->start, resource_size(regs)); |
7d2be074 HS |
1786 | if (!host->regs) |
1787 | goto err_ioremap; | |
1788 | ||
1789 | clk_enable(host->mck); | |
1790 | mci_writel(host, CR, MCI_CR_SWRST); | |
1791 | host->bus_hz = clk_get_rate(host->mck); | |
1792 | clk_disable(host->mck); | |
1793 | ||
1794 | host->mapbase = regs->start; | |
1795 | ||
965ebf33 | 1796 | tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host); |
7d2be074 | 1797 | |
89c8aa20 | 1798 | ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host); |
7d2be074 HS |
1799 | if (ret) |
1800 | goto err_request_irq; | |
1801 | ||
2635d1ba | 1802 | atmci_configure_dma(host); |
65e8b083 | 1803 | |
7d2be074 HS |
1804 | platform_set_drvdata(pdev, host); |
1805 | ||
965ebf33 HS |
1806 | /* We need at least one slot to succeed */ |
1807 | nr_slots = 0; | |
1808 | ret = -ENODEV; | |
1809 | if (pdata->slot[0].bus_width) { | |
1810 | ret = atmci_init_slot(host, &pdata->slot[0], | |
88ff82ed | 1811 | 0, MCI_SDCSEL_SLOT_A, MCI_SDIOIRQA); |
965ebf33 HS |
1812 | if (!ret) |
1813 | nr_slots++; | |
1814 | } | |
1815 | if (pdata->slot[1].bus_width) { | |
1816 | ret = atmci_init_slot(host, &pdata->slot[1], | |
88ff82ed | 1817 | 1, MCI_SDCSEL_SLOT_B, MCI_SDIOIRQB); |
965ebf33 HS |
1818 | if (!ret) |
1819 | nr_slots++; | |
7d2be074 HS |
1820 | } |
1821 | ||
04d699c3 RE |
1822 | if (!nr_slots) { |
1823 | dev_err(&pdev->dev, "init failed: no slot defined\n"); | |
965ebf33 | 1824 | goto err_init_slot; |
04d699c3 | 1825 | } |
7d2be074 | 1826 | |
965ebf33 HS |
1827 | dev_info(&pdev->dev, |
1828 | "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", | |
1829 | host->mapbase, irq, nr_slots); | |
deec9ae3 | 1830 | |
7d2be074 HS |
1831 | return 0; |
1832 | ||
965ebf33 | 1833 | err_init_slot: |
65e8b083 | 1834 | #ifdef CONFIG_MMC_ATMELMCI_DMA |
74465b4f DW |
1835 | if (host->dma.chan) |
1836 | dma_release_channel(host->dma.chan); | |
65e8b083 | 1837 | #endif |
965ebf33 | 1838 | free_irq(irq, host); |
7d2be074 HS |
1839 | err_request_irq: |
1840 | iounmap(host->regs); | |
1841 | err_ioremap: | |
1842 | clk_put(host->mck); | |
1843 | err_clk_get: | |
965ebf33 | 1844 | kfree(host); |
7d2be074 HS |
1845 | return ret; |
1846 | } | |
1847 | ||
1848 | static int __exit atmci_remove(struct platform_device *pdev) | |
1849 | { | |
965ebf33 HS |
1850 | struct atmel_mci *host = platform_get_drvdata(pdev); |
1851 | unsigned int i; | |
7d2be074 HS |
1852 | |
1853 | platform_set_drvdata(pdev, NULL); | |
1854 | ||
965ebf33 HS |
1855 | for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { |
1856 | if (host->slot[i]) | |
1857 | atmci_cleanup_slot(host->slot[i], i); | |
1858 | } | |
7d2be074 | 1859 | |
965ebf33 HS |
1860 | clk_enable(host->mck); |
1861 | mci_writel(host, IDR, ~0UL); | |
1862 | mci_writel(host, CR, MCI_CR_MCIDIS); | |
1863 | mci_readl(host, SR); | |
1864 | clk_disable(host->mck); | |
7d2be074 | 1865 | |
65e8b083 | 1866 | #ifdef CONFIG_MMC_ATMELMCI_DMA |
74465b4f DW |
1867 | if (host->dma.chan) |
1868 | dma_release_channel(host->dma.chan); | |
65e8b083 HS |
1869 | #endif |
1870 | ||
965ebf33 HS |
1871 | free_irq(platform_get_irq(pdev, 0), host); |
1872 | iounmap(host->regs); | |
7d2be074 | 1873 | |
965ebf33 HS |
1874 | clk_put(host->mck); |
1875 | kfree(host); | |
7d2be074 | 1876 | |
7d2be074 HS |
1877 | return 0; |
1878 | } | |
1879 | ||
1880 | static struct platform_driver atmci_driver = { | |
1881 | .remove = __exit_p(atmci_remove), | |
1882 | .driver = { | |
1883 | .name = "atmel_mci", | |
1884 | }, | |
1885 | }; | |
1886 | ||
1887 | static int __init atmci_init(void) | |
1888 | { | |
1889 | return platform_driver_probe(&atmci_driver, atmci_probe); | |
1890 | } | |
1891 | ||
1892 | static void __exit atmci_exit(void) | |
1893 | { | |
1894 | platform_driver_unregister(&atmci_driver); | |
1895 | } | |
1896 | ||
74465b4f | 1897 | late_initcall(atmci_init); /* try to load after dma driver when built-in */ |
7d2be074 HS |
1898 | module_exit(atmci_exit); |
1899 | ||
1900 | MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); | |
1901 | MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>"); | |
1902 | MODULE_LICENSE("GPL v2"); |