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[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / bfin_sdh.c
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eb962d5b
CC		 1/*
2 * bfin_sdh.c - Analog Devices Blackfin SDH Controller
3 *
4 * Copyright (C) 2007-2009 Analog Device Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#define DRIVER_NAME "bfin-sdh"
10
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/ioport.h>
14#include <linux/platform_device.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/dma-mapping.h>
18#include <linux/mmc/host.h>
19#include <linux/proc_fs.h>
20
21#include <asm/cacheflush.h>
22#include <asm/dma.h>
23#include <asm/portmux.h>
24#include <asm/bfin_sdh.h>
25
26#if defined(CONFIG_BF51x)
27#define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CTL
28#define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CTL
29#define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CTL
30#define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CTL
31#define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
32#define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
33#define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
34#define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
35#define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
36#define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
37#define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
38#define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
39#define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CTL
40#define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CTL
41#define bfin_read_SDH_DATA_CNT bfin_read_RSI_DATA_CNT
42#define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUS_CLR
43#define bfin_read_SDH_E_STATUS bfin_read_RSI_E_STATUS
44#define bfin_write_SDH_E_STATUS bfin_write_RSI_E_STATUS
45#define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
46#define bfin_write_SDH_MASK0 bfin_write_RSI_MASK0
47#define bfin_read_SDH_CFG bfin_read_RSI_CFG
48#define bfin_write_SDH_CFG bfin_write_RSI_CFG
49#endif
50
51struct dma_desc_array {
52 unsigned long start_addr;
53 unsigned short cfg;
54 unsigned short x_count;
55 short x_modify;
56} __packed;
57
58struct sdh_host {
59 struct mmc_host *mmc;
60 spinlock_t lock;
61 struct resource *res;
62 void __iomem *base;
63 int irq;
64 int stat_irq;
65 int dma_ch;
66 int dma_dir;
67 struct dma_desc_array *sg_cpu;
68 dma_addr_t sg_dma;
69 int dma_len;
70
71 unsigned int imask;
72 unsigned int power_mode;
73 unsigned int clk_div;
74
75 struct mmc_request *mrq;
76 struct mmc_command *cmd;
77 struct mmc_data *data;
78};
79
80static struct bfin_sd_host *get_sdh_data(struct platform_device *pdev)
81{
82 return pdev->dev.platform_data;
83}
84
85static void sdh_stop_clock(struct sdh_host *host)
86{
87 bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() & ~CLK_E);
88 SSYNC();
89}
90
91static void sdh_enable_stat_irq(struct sdh_host *host, unsigned int mask)
92{
93 unsigned long flags;
94
95 spin_lock_irqsave(&host->lock, flags);
96 host->imask |= mask;
97 bfin_write_SDH_MASK0(mask);
98 SSYNC();
99 spin_unlock_irqrestore(&host->lock, flags);
100}
101
102static void sdh_disable_stat_irq(struct sdh_host *host, unsigned int mask)
103{
104 unsigned long flags;
105
106 spin_lock_irqsave(&host->lock, flags);
107 host->imask &= ~mask;
108 bfin_write_SDH_MASK0(host->imask);
109 SSYNC();
110 spin_unlock_irqrestore(&host->lock, flags);
111}
112
113static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
114{
115 unsigned int length;
116 unsigned int data_ctl;
117 unsigned int dma_cfg;
729adf1b 118 unsigned int cycle_ns, timeout;
eb962d5b
CC		 119
120 dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags);
121 host->data = data;
122 data_ctl = 0;
123 dma_cfg = 0;
124
125 length = data->blksz * data->blocks;
126 bfin_write_SDH_DATA_LGTH(length);
127
128 if (data->flags & MMC_DATA_STREAM)
129 data_ctl |= DTX_MODE;
130
131 if (data->flags & MMC_DATA_READ)
132 data_ctl |= DTX_DIR;
133 /* Only supports power-of-2 block size */
134 if (data->blksz & (data->blksz - 1))
135 return -EINVAL;
136 data_ctl |= ((ffs(data->blksz) - 1) << 4);
137
138 bfin_write_SDH_DATA_CTL(data_ctl);
729adf1b
CC		 139 /* the time of a host clock period in ns */
140 cycle_ns = 1000000000 / (get_sclk() / (2 * (host->clk_div + 1)));
141 timeout = data->timeout_ns / cycle_ns;
142 timeout += data->timeout_clks;
143 bfin_write_SDH_DATA_TIMER(timeout);
eb962d5b
CC		 144 SSYNC();
145
146 if (data->flags & MMC_DATA_READ) {
147 host->dma_dir = DMA_FROM_DEVICE;
148 dma_cfg |= WNR;
149 } else
150 host->dma_dir = DMA_TO_DEVICE;
151
152 sdh_enable_stat_irq(host, (DAT_CRC_FAIL | DAT_TIME_OUT | DAT_END));
153 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
154#if defined(CONFIG_BF54x)
155 dma_cfg |= DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_32 | DMAEN;
156 {
c744d988 157 struct scatterlist *sg;
eb962d5b
CC		 158 int i;
159 for_each_sg(data->sg, sg, host->dma_len, i) {
160 host->sg_cpu[i].start_addr = sg_dma_address(sg);
161 host->sg_cpu[i].cfg = dma_cfg;
162 host->sg_cpu[i].x_count = sg_dma_len(sg) / 4;
163 host->sg_cpu[i].x_modify = 4;
164 dev_dbg(mmc_dev(host->mmc), "%d: start_addr:0x%lx, "
165 "cfg:0x%x, x_count:0x%x, x_modify:0x%x\n",
166 i, host->sg_cpu[i].start_addr,
167 host->sg_cpu[i].cfg, host->sg_cpu[i].x_count,
168 host->sg_cpu[i].x_modify);
169 }
170 }
171 flush_dcache_range((unsigned int)host->sg_cpu,
172 (unsigned int)host->sg_cpu +
173 host->dma_len * sizeof(struct dma_desc_array));
174 /* Set the last descriptor to stop mode */
175 host->sg_cpu[host->dma_len - 1].cfg &= ~(DMAFLOW | NDSIZE);
176 host->sg_cpu[host->dma_len - 1].cfg |= DI_EN;
177
178 set_dma_curr_desc_addr(host->dma_ch, (unsigned long *)host->sg_dma);
179 set_dma_x_count(host->dma_ch, 0);
180 set_dma_x_modify(host->dma_ch, 0);
181 set_dma_config(host->dma_ch, dma_cfg);
182#elif defined(CONFIG_BF51x)
183 /* RSI DMA doesn't work in array mode */
184 dma_cfg |= WDSIZE_32 | DMAEN;
185 set_dma_start_addr(host->dma_ch, sg_dma_address(&data->sg[0]));
186 set_dma_x_count(host->dma_ch, length / 4);
187 set_dma_x_modify(host->dma_ch, 4);
188 set_dma_config(host->dma_ch, dma_cfg);
189#endif
190 bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
191
192 SSYNC();
193
194 dev_dbg(mmc_dev(host->mmc), "%s exit\n", __func__);
195 return 0;
196}
197
198static void sdh_start_cmd(struct sdh_host *host, struct mmc_command *cmd)
199{
200 unsigned int sdh_cmd;
201 unsigned int stat_mask;
202
203 dev_dbg(mmc_dev(host->mmc), "%s enter cmd: 0x%p\n", __func__, cmd);
204 WARN_ON(host->cmd != NULL);
205 host->cmd = cmd;
206
207 sdh_cmd = 0;
208 stat_mask = 0;
209
210 sdh_cmd |= cmd->opcode;
211
212 if (cmd->flags & MMC_RSP_PRESENT) {
213 sdh_cmd |= CMD_RSP;
214 stat_mask |= CMD_RESP_END;
215 } else {
216 stat_mask |= CMD_SENT;
217 }
218
219 if (cmd->flags & MMC_RSP_136)
220 sdh_cmd |= CMD_L_RSP;
221
222 stat_mask |= CMD_CRC_FAIL | CMD_TIME_OUT;
223
224 sdh_enable_stat_irq(host, stat_mask);
225
226 bfin_write_SDH_ARGUMENT(cmd->arg);
227 bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
228 bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() | CLK_E);
229 SSYNC();
230}
231
232static void sdh_finish_request(struct sdh_host *host, struct mmc_request *mrq)
233{
234 dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
235 host->mrq = NULL;
236 host->cmd = NULL;
237 host->data = NULL;
238 mmc_request_done(host->mmc, mrq);
239}
240
241static int sdh_cmd_done(struct sdh_host *host, unsigned int stat)
242{
243 struct mmc_command *cmd = host->cmd;
244 int ret = 0;
245
246 dev_dbg(mmc_dev(host->mmc), "%s enter cmd: %p\n", __func__, cmd);
247 if (!cmd)
248 return 0;
249
250 host->cmd = NULL;
251
252 if (cmd->flags & MMC_RSP_PRESENT) {
253 cmd->resp[0] = bfin_read_SDH_RESPONSE0();
254 if (cmd->flags & MMC_RSP_136) {
255 cmd->resp[1] = bfin_read_SDH_RESPONSE1();
256 cmd->resp[2] = bfin_read_SDH_RESPONSE2();
257 cmd->resp[3] = bfin_read_SDH_RESPONSE3();
258 }
259 }
260 if (stat & CMD_TIME_OUT)
261 cmd->error = -ETIMEDOUT;
262 else if (stat & CMD_CRC_FAIL && cmd->flags & MMC_RSP_CRC)
263 cmd->error = -EILSEQ;
264
265 sdh_disable_stat_irq(host, (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL));
266
267 if (host->data && !cmd->error) {
268 if (host->data->flags & MMC_DATA_WRITE) {
269 ret = sdh_setup_data(host, host->data);
270 if (ret)
271 return 0;
272 }
273
274 sdh_enable_stat_irq(host, DAT_END | RX_OVERRUN | TX_UNDERRUN | DAT_TIME_OUT);
275 } else
276 sdh_finish_request(host, host->mrq);
277
278 return 1;
279}
280
281static int sdh_data_done(struct sdh_host *host, unsigned int stat)
282{
283 struct mmc_data *data = host->data;
284
285 dev_dbg(mmc_dev(host->mmc), "%s enter stat: 0x%x\n", __func__, stat);
286 if (!data)
287 return 0;
288
289 disable_dma(host->dma_ch);
290 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
291 host->dma_dir);
292
293 if (stat & DAT_TIME_OUT)
294 data->error = -ETIMEDOUT;
295 else if (stat & DAT_CRC_FAIL)
296 data->error = -EILSEQ;
297 else if (stat & (RX_OVERRUN | TX_UNDERRUN))
298 data->error = -EIO;
299
300 if (!data->error)
301 data->bytes_xfered = data->blocks * data->blksz;
302 else
303 data->bytes_xfered = 0;
304
305 sdh_disable_stat_irq(host, DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN);
306 bfin_write_SDH_STATUS_CLR(DAT_END_STAT | DAT_TIMEOUT_STAT | \
307 DAT_CRC_FAIL_STAT | DAT_BLK_END_STAT | RX_OVERRUN | TX_UNDERRUN);
308 bfin_write_SDH_DATA_CTL(0);
309 SSYNC();
310
311 host->data = NULL;
312 if (host->mrq->stop) {
313 sdh_stop_clock(host);
314 sdh_start_cmd(host, host->mrq->stop);
315 } else {
316 sdh_finish_request(host, host->mrq);
317 }
318
319 return 1;
320}
321
322static void sdh_request(struct mmc_host *mmc, struct mmc_request *mrq)
323{
324 struct sdh_host *host = mmc_priv(mmc);
325 int ret = 0;
326
327 dev_dbg(mmc_dev(host->mmc), "%s enter, mrp:%p, cmd:%p\n", __func__, mrq, mrq->cmd);
328 WARN_ON(host->mrq != NULL);
329
330 host->mrq = mrq;
331 host->data = mrq->data;
332
333 if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
334 ret = sdh_setup_data(host, mrq->data);
335 if (ret)
336 return;
337 }
338
339 sdh_start_cmd(host, mrq->cmd);
340}
341
342static void sdh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
343{
344 struct sdh_host *host;
345 unsigned long flags;
346 u16 clk_ctl = 0;
347 u16 pwr_ctl = 0;
348 u16 cfg;
349 host = mmc_priv(mmc);
350
351 spin_lock_irqsave(&host->lock, flags);
352 if (ios->clock) {
353 unsigned long sys_clk, ios_clk;
354 unsigned char clk_div;
355 ios_clk = 2 * ios->clock;
356 sys_clk = get_sclk();
357 clk_div = sys_clk / ios_clk;
358 if (sys_clk % ios_clk == 0)
359 clk_div -= 1;
360 clk_div = min_t(unsigned char, clk_div, 0xFF);
361 clk_ctl |= clk_div;
362 clk_ctl |= CLK_E;
363 host->clk_div = clk_div;
364 } else
365 sdh_stop_clock(host);
366
367 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
368#ifdef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
369 pwr_ctl |= ROD_CTL;
370#else
371 pwr_ctl |= SD_CMD_OD | ROD_CTL;
372#endif
373
374 if (ios->bus_width == MMC_BUS_WIDTH_4) {
375 cfg = bfin_read_SDH_CFG();
376 cfg &= ~PD_SDDAT3;
377 cfg |= PUP_SDDAT3;
378 /* Enable 4 bit SDIO */
379 cfg |= (SD4E | MWE);
380 bfin_write_SDH_CFG(cfg);
381 clk_ctl |= WIDE_BUS;
382 } else {
383 cfg = bfin_read_SDH_CFG();
384 cfg |= MWE;
385 bfin_write_SDH_CFG(cfg);
386 }
387
388 bfin_write_SDH_CLK_CTL(clk_ctl);
389
390 host->power_mode = ios->power_mode;
391 if (ios->power_mode == MMC_POWER_ON)
392 pwr_ctl |= PWR_ON;
393
394 bfin_write_SDH_PWR_CTL(pwr_ctl);
395 SSYNC();
396
397 spin_unlock_irqrestore(&host->lock, flags);
398
399 dev_dbg(mmc_dev(host->mmc), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
400 host->clk_div,
401 host->clk_div ? get_sclk() / (2 * (host->clk_div + 1)) : 0,
402 ios->clock);
403}
404
405static const struct mmc_host_ops sdh_ops = {
406 .request = sdh_request,
407 .set_ios = sdh_set_ios,
408};
409
410static irqreturn_t sdh_dma_irq(int irq, void *devid)
411{
412 struct sdh_host *host = devid;
413
414 dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04x\n", __func__,
415 get_dma_curr_irqstat(host->dma_ch));
416 clear_dma_irqstat(host->dma_ch);
417 SSYNC();
418
419 return IRQ_HANDLED;
420}
421
422static irqreturn_t sdh_stat_irq(int irq, void *devid)
423{
424 struct sdh_host *host = devid;
425 unsigned int status;
426 int handled = 0;
427
428 dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
429 status = bfin_read_SDH_E_STATUS();
430 if (status & SD_CARD_DET) {
431 mmc_detect_change(host->mmc, 0);
432 bfin_write_SDH_E_STATUS(SD_CARD_DET);
433 }
434 status = bfin_read_SDH_STATUS();
435 if (status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL)) {
436 handled |= sdh_cmd_done(host, status);
437 bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | \
438 CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
439 SSYNC();
440 }
441
442 status = bfin_read_SDH_STATUS();
443 if (status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN))
444 handled |= sdh_data_done(host, status);
445
446 dev_dbg(mmc_dev(host->mmc), "%s exit\n\n", __func__);
447
448 return IRQ_RETVAL(handled);
449}
450
451static int __devinit sdh_probe(struct platform_device *pdev)
452{
453 struct mmc_host *mmc;
454 struct sdh_host *host;
455 struct bfin_sd_host *drv_data = get_sdh_data(pdev);
456 int ret;
457
458 if (!drv_data) {
459 dev_err(&pdev->dev, "missing platform driver data\n");
460 ret = -EINVAL;
461 goto out;
462 }
463
464 mmc = mmc_alloc_host(sizeof(*mmc), &pdev->dev);
465 if (!mmc) {
466 ret = -ENOMEM;
467 goto out;
468 }
469
470 mmc->ops = &sdh_ops;
471 mmc->max_phys_segs = 32;
472 mmc->max_seg_size = 1 << 16;
473 mmc->max_blk_size = 1 << 11;
474 mmc->max_blk_count = 1 << 11;
475 mmc->max_req_size = PAGE_SIZE;
476 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
477 mmc->f_max = get_sclk();
478 mmc->f_min = mmc->f_max >> 9;
479 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL;
480 host = mmc_priv(mmc);
481 host->mmc = mmc;
482
483 spin_lock_init(&host->lock);
484 host->irq = drv_data->irq_int0;
485 host->dma_ch = drv_data->dma_chan;
486
487 ret = request_dma(host->dma_ch, DRIVER_NAME "DMA");
488 if (ret) {
489 dev_err(&pdev->dev, "unable to request DMA channel\n");
490 goto out1;
491 }
492
493 ret = set_dma_callback(host->dma_ch, sdh_dma_irq, host);
494 if (ret) {
495 dev_err(&pdev->dev, "unable to request DMA irq\n");
496 goto out2;
497 }
498
499 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
500 if (host->sg_cpu == NULL) {
501 ret = -ENOMEM;
502 goto out2;
503 }
504
505 platform_set_drvdata(pdev, mmc);
506 mmc_add_host(mmc);
507
508 ret = request_irq(host->irq, sdh_stat_irq, 0, "SDH Status IRQ", host);
509 if (ret) {
510 dev_err(&pdev->dev, "unable to request status irq\n");
511 goto out3;
512 }
513
514 ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
515 if (ret) {
516 dev_err(&pdev->dev, "unable to request peripheral pins\n");
517 goto out4;
518 }
519#if defined(CONFIG_BF54x)
520 /* Secure Digital Host shares DMA with Nand controller */
521 bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
522#endif
523
524 bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
525 SSYNC();
526
527 /* Disable card inserting detection pin. set MMC_CAP_NEES_POLL, and
528 * mmc stack will do the detection.
529 */
530 bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
531 SSYNC();
532
533 return 0;
534
535out4:
536 free_irq(host->irq, host);
537out3:
538 mmc_remove_host(mmc);
539 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
540out2:
541 free_dma(host->dma_ch);
542out1:
543 mmc_free_host(mmc);
544 out:
545 return ret;
546}
547
548static int __devexit sdh_remove(struct platform_device *pdev)
549{
550 struct mmc_host *mmc = platform_get_drvdata(pdev);
551
552 platform_set_drvdata(pdev, NULL);
553
554 if (mmc) {
555 struct sdh_host *host = mmc_priv(mmc);
556
557 mmc_remove_host(mmc);
558
559 sdh_stop_clock(host);
560 free_irq(host->irq, host);
561 free_dma(host->dma_ch);
562 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
563
564 mmc_free_host(mmc);
565 }
566
567 return 0;
568}
569
570#ifdef CONFIG_PM
571static int sdh_suspend(struct platform_device *dev, pm_message_t state)
572{
573 struct mmc_host *mmc = platform_get_drvdata(dev);
574 struct bfin_sd_host *drv_data = get_sdh_data(dev);
575 int ret = 0;
576
577 if (mmc)
578 ret = mmc_suspend_host(mmc, state);
579
580 bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() & ~PWR_ON);
581 peripheral_free_list(drv_data->pin_req);
582
583 return ret;
584}
585
586static int sdh_resume(struct platform_device *dev)
587{
588 struct mmc_host *mmc = platform_get_drvdata(dev);
589 struct bfin_sd_host *drv_data = get_sdh_data(dev);
590 int ret = 0;
591
592 ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
593 if (ret) {
594 dev_err(&dev->dev, "unable to request peripheral pins\n");
595 return ret;
596 }
597
598 bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() | PWR_ON);
599#if defined(CONFIG_BF54x)
600 /* Secure Digital Host shares DMA with Nand controller */
601 bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
602#endif
603 bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
604 SSYNC();
605
606 bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
607 SSYNC();
608
609 if (mmc)
610 ret = mmc_resume_host(mmc);
611
612 return ret;
613}
614#else
615# define sdh_suspend NULL
616# define sdh_resume NULL
617#endif
618
619static struct platform_driver sdh_driver = {
620 .probe = sdh_probe,
621 .remove = __devexit_p(sdh_remove),
622 .suspend = sdh_suspend,
623 .resume = sdh_resume,
624 .driver = {
625 .name = DRIVER_NAME,
626 },
627};
628
629static int __init sdh_init(void)
630{
631 return platform_driver_register(&sdh_driver);
632}
633module_init(sdh_init);
634
635static void __exit sdh_exit(void)
636{
637 platform_driver_unregister(&sdh_driver);
638}
639module_exit(sdh_exit);
640
641MODULE_DESCRIPTION("Blackfin Secure Digital Host Driver");
642MODULE_AUTHOR("Cliff Cai, Roy Huang");
643MODULE_LICENSE("GPL");
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