[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / bfin_sdh.c

/*
 * bfin_sdh.c - Analog Devices Blackfin SDH Controller
 *
 * Copyright (C) 2007-2009 Analog Device Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#define DRIVER_NAME	"bfin-sdh"

#include <linux/module.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/mmc/host.h>
#include <linux/proc_fs.h>
#include <linux/gfp.h>

#include <asm/cacheflush.h>
#include <asm/dma.h>
#include <asm/portmux.h>
#include <asm/bfin_sdh.h>

#if defined(CONFIG_BF51x) || defined(__ADSPBF60x__)
#define bfin_read_SDH_CLK_CTL		bfin_read_RSI_CLK_CTL
#define bfin_write_SDH_CLK_CTL		bfin_write_RSI_CLK_CTL
#define bfin_write_SDH_ARGUMENT		bfin_write_RSI_ARGUMENT
#define bfin_write_SDH_COMMAND		bfin_write_RSI_COMMAND
#define bfin_write_SDH_DATA_TIMER	bfin_write_RSI_DATA_TIMER
#define bfin_read_SDH_RESPONSE0		bfin_read_RSI_RESPONSE0
#define bfin_read_SDH_RESPONSE1		bfin_read_RSI_RESPONSE1
#define bfin_read_SDH_RESPONSE2		bfin_read_RSI_RESPONSE2
#define bfin_read_SDH_RESPONSE3		bfin_read_RSI_RESPONSE3
#define bfin_write_SDH_DATA_LGTH	bfin_write_RSI_DATA_LGTH
#define bfin_read_SDH_DATA_CTL		bfin_read_RSI_DATA_CTL
#define bfin_write_SDH_DATA_CTL		bfin_write_RSI_DATA_CTL
#define bfin_read_SDH_DATA_CNT		bfin_read_RSI_DATA_CNT
#define bfin_write_SDH_STATUS_CLR	bfin_write_RSI_STATUS_CLR
#define bfin_read_SDH_E_STATUS		bfin_read_RSI_E_STATUS
#define bfin_write_SDH_E_STATUS		bfin_write_RSI_E_STATUS
#define bfin_read_SDH_STATUS		bfin_read_RSI_STATUS
#define bfin_write_SDH_MASK0		bfin_write_RSI_MASK0
#define bfin_write_SDH_E_MASK		bfin_write_RSI_E_MASK
#define bfin_read_SDH_CFG		bfin_read_RSI_CFG
#define bfin_write_SDH_CFG		bfin_write_RSI_CFG
# if defined(__ADSPBF60x__)
#  define bfin_read_SDH_BLK_SIZE	bfin_read_RSI_BLKSZ
#  define bfin_write_SDH_BLK_SIZE	bfin_write_RSI_BLKSZ
# else
#  define bfin_read_SDH_PWR_CTL		bfin_read_RSI_PWR_CTL
#  define bfin_write_SDH_PWR_CTL	bfin_write_RSI_PWR_CTL
# endif
#endif

struct sdh_host {
	struct mmc_host		*mmc;
	spinlock_t		lock;
	struct resource		*res;
	void __iomem		*base;
	int			irq;
	int			stat_irq;
	int			dma_ch;
	int			dma_dir;
	struct dma_desc_array	*sg_cpu;
	dma_addr_t		sg_dma;
	int			dma_len;

	unsigned long		sclk;
	unsigned int		imask;
	unsigned int		power_mode;
	unsigned int		clk_div;

	struct mmc_request	*mrq;
	struct mmc_command	*cmd;
	struct mmc_data		*data;
};

static struct bfin_sd_host *get_sdh_data(struct platform_device *pdev)
{
	return pdev->dev.platform_data;
}

static void sdh_stop_clock(struct sdh_host *host)
{
	bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() & ~CLK_E);
	SSYNC();
}

static void sdh_enable_stat_irq(struct sdh_host *host, unsigned int mask)
{
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);
	host->imask |= mask;
	bfin_write_SDH_MASK0(mask);
	SSYNC();
	spin_unlock_irqrestore(&host->lock, flags);
}

static void sdh_disable_stat_irq(struct sdh_host *host, unsigned int mask)
{
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);
	host->imask &= ~mask;
	bfin_write_SDH_MASK0(host->imask);
	SSYNC();
	spin_unlock_irqrestore(&host->lock, flags);
}

static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
{
	unsigned int length;
	unsigned int data_ctl;
	unsigned int dma_cfg;
	unsigned int cycle_ns, timeout;

	dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags);
	host->data = data;
	data_ctl = 0;
	dma_cfg = 0;

	length = data->blksz * data->blocks;
	bfin_write_SDH_DATA_LGTH(length);

	if (data->flags & MMC_DATA_READ)
		data_ctl |= DTX_DIR;
	/* Only supports power-of-2 block size */
	if (data->blksz & (data->blksz - 1))
		return -EINVAL;
#ifndef RSI_BLKSZ
	data_ctl |= ((ffs(data->blksz) - 1) << 4);
#else
        bfin_write_SDH_BLK_SIZE(data->blksz);
#endif

	bfin_write_SDH_DATA_CTL(data_ctl);
	/* the time of a host clock period in ns */
	cycle_ns = 1000000000 / (host->sclk / (2 * (host->clk_div + 1)));
	timeout = data->timeout_ns / cycle_ns;
	timeout += data->timeout_clks;
	bfin_write_SDH_DATA_TIMER(timeout);
	SSYNC();

	if (data->flags & MMC_DATA_READ) {
		host->dma_dir = DMA_FROM_DEVICE;
		dma_cfg |= WNR;
	} else
		host->dma_dir = DMA_TO_DEVICE;

	sdh_enable_stat_irq(host, (DAT_CRC_FAIL | DAT_TIME_OUT | DAT_END));
	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
	dma_cfg |= DMAFLOW_ARRAY | RESTART | WDSIZE_32 | DMAEN;
# ifdef RSI_BLKSZ
	dma_cfg |= PSIZE_32 | NDSIZE_3;
# else
	dma_cfg |= NDSIZE_5;
# endif
	{
		struct scatterlist *sg;
		int i;
		for_each_sg(data->sg, sg, host->dma_len, i) {
			host->sg_cpu[i].start_addr = sg_dma_address(sg);
			host->sg_cpu[i].cfg = dma_cfg;
			host->sg_cpu[i].x_count = sg_dma_len(sg) / 4;
			host->sg_cpu[i].x_modify = 4;
			dev_dbg(mmc_dev(host->mmc), "%d: start_addr:0x%lx, "
				"cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
				i, host->sg_cpu[i].start_addr,
				host->sg_cpu[i].cfg, host->sg_cpu[i].x_count,
				host->sg_cpu[i].x_modify);
		}
	}
	flush_dcache_range((unsigned int)host->sg_cpu,
		(unsigned int)host->sg_cpu +
			host->dma_len * sizeof(struct dma_desc_array));
	/* Set the last descriptor to stop mode */
	host->sg_cpu[host->dma_len - 1].cfg &= ~(DMAFLOW | NDSIZE);
	host->sg_cpu[host->dma_len - 1].cfg |= DI_EN;

	set_dma_curr_desc_addr(host->dma_ch, (unsigned long *)host->sg_dma);
	set_dma_x_count(host->dma_ch, 0);
	set_dma_x_modify(host->dma_ch, 0);
	SSYNC();
	set_dma_config(host->dma_ch, dma_cfg);
#elif defined(CONFIG_BF51x)
	/* RSI DMA doesn't work in array mode */
	dma_cfg |= WDSIZE_32 | DMAEN;
	set_dma_start_addr(host->dma_ch, sg_dma_address(&data->sg[0]));
	set_dma_x_count(host->dma_ch, length / 4);
	set_dma_x_modify(host->dma_ch, 4);
	SSYNC();
	set_dma_config(host->dma_ch, dma_cfg);
#endif
	bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);

	SSYNC();

	dev_dbg(mmc_dev(host->mmc), "%s exit\n", __func__);
	return 0;
}

static void sdh_start_cmd(struct sdh_host *host, struct mmc_command *cmd)
{
	unsigned int sdh_cmd;
	unsigned int stat_mask;

	dev_dbg(mmc_dev(host->mmc), "%s enter cmd: 0x%p\n", __func__, cmd);
	WARN_ON(host->cmd != NULL);
	host->cmd = cmd;

	sdh_cmd = 0;
	stat_mask = 0;

	sdh_cmd |= cmd->opcode;

	if (cmd->flags & MMC_RSP_PRESENT) {
		sdh_cmd |= CMD_RSP;
		stat_mask |= CMD_RESP_END;
	} else {
		stat_mask |= CMD_SENT;
	}

	if (cmd->flags & MMC_RSP_136)
		sdh_cmd |= CMD_L_RSP;

	stat_mask |= CMD_CRC_FAIL | CMD_TIME_OUT;

	sdh_enable_stat_irq(host, stat_mask);

	bfin_write_SDH_ARGUMENT(cmd->arg);
	bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
	bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() | CLK_E);
	SSYNC();
}

static void sdh_finish_request(struct sdh_host *host, struct mmc_request *mrq)
{
	dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
	host->mrq = NULL;
	host->cmd = NULL;
	host->data = NULL;
	mmc_request_done(host->mmc, mrq);
}

static int sdh_cmd_done(struct sdh_host *host, unsigned int stat)
{
	struct mmc_command *cmd = host->cmd;
	int ret = 0;

	dev_dbg(mmc_dev(host->mmc), "%s enter cmd: %p\n", __func__, cmd);
	if (!cmd)
		return 0;

	host->cmd = NULL;

	if (cmd->flags & MMC_RSP_PRESENT) {
		cmd->resp[0] = bfin_read_SDH_RESPONSE0();
		if (cmd->flags & MMC_RSP_136) {
			cmd->resp[1] = bfin_read_SDH_RESPONSE1();
			cmd->resp[2] = bfin_read_SDH_RESPONSE2();
			cmd->resp[3] = bfin_read_SDH_RESPONSE3();
		}
	}
	if (stat & CMD_TIME_OUT)
		cmd->error = -ETIMEDOUT;
	else if (stat & CMD_CRC_FAIL && cmd->flags & MMC_RSP_CRC)
		cmd->error = -EILSEQ;

	sdh_disable_stat_irq(host, (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL));

	if (host->data && !cmd->error) {
		if (host->data->flags & MMC_DATA_WRITE) {
			ret = sdh_setup_data(host, host->data);
			if (ret)
				return 0;
		}

		sdh_enable_stat_irq(host, DAT_END | RX_OVERRUN | TX_UNDERRUN | DAT_TIME_OUT);
	} else
		sdh_finish_request(host, host->mrq);

	return 1;
}

static int sdh_data_done(struct sdh_host *host, unsigned int stat)
{
	struct mmc_data *data = host->data;

	dev_dbg(mmc_dev(host->mmc), "%s enter stat: 0x%x\n", __func__, stat);
	if (!data)
		return 0;

	disable_dma(host->dma_ch);
	dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
		     host->dma_dir);

	if (stat & DAT_TIME_OUT)
		data->error = -ETIMEDOUT;
	else if (stat & DAT_CRC_FAIL)
		data->error = -EILSEQ;
	else if (stat & (RX_OVERRUN | TX_UNDERRUN))
		data->error = -EIO;

	if (!data->error)
		data->bytes_xfered = data->blocks * data->blksz;
	else
		data->bytes_xfered = 0;

	bfin_write_SDH_STATUS_CLR(DAT_END_STAT | DAT_TIMEOUT_STAT | \
			DAT_CRC_FAIL_STAT | DAT_BLK_END_STAT | RX_OVERRUN | TX_UNDERRUN);
	bfin_write_SDH_DATA_CTL(0);
	SSYNC();

	host->data = NULL;
	if (host->mrq->stop) {
		sdh_stop_clock(host);
		sdh_start_cmd(host, host->mrq->stop);
	} else {
		sdh_finish_request(host, host->mrq);
	}

	return 1;
}

static void sdh_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct sdh_host *host = mmc_priv(mmc);
	int ret = 0;

	dev_dbg(mmc_dev(host->mmc), "%s enter, mrp:%p, cmd:%p\n", __func__, mrq, mrq->cmd);
	WARN_ON(host->mrq != NULL);

	spin_lock(&host->lock);
	host->mrq = mrq;
	host->data = mrq->data;

	if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
		ret = sdh_setup_data(host, mrq->data);
		if (ret)
			goto data_err;
	}

	sdh_start_cmd(host, mrq->cmd);
data_err:
	spin_unlock(&host->lock);
}

static void sdh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct sdh_host *host;
	u16 clk_ctl = 0;
#ifndef RSI_BLKSZ
	u16 pwr_ctl = 0;
#endif
	u16 cfg;
	host = mmc_priv(mmc);

	spin_lock(&host->lock);

	cfg = bfin_read_SDH_CFG();
	cfg |= MWE;
	switch (ios->bus_width) {
	case MMC_BUS_WIDTH_4:
#ifndef RSI_BLKSZ
		cfg &= ~PD_SDDAT3;
#endif
		cfg |= PUP_SDDAT3;
		/* Enable 4 bit SDIO */
		cfg |= SD4E;
		clk_ctl |= WIDE_BUS_4;
		break;
	case MMC_BUS_WIDTH_8:
#ifndef RSI_BLKSZ
		cfg &= ~PD_SDDAT3;
#endif
		cfg |= PUP_SDDAT3;
		/* Disable 4 bit SDIO */
		cfg &= ~SD4E;
		clk_ctl |= BYTE_BUS_8;
		break;
	default:
		cfg &= ~PUP_SDDAT3;
		/* Disable 4 bit SDIO */
		cfg &= ~SD4E;
	}
	bfin_write_SDH_CFG(cfg);

	host->power_mode = ios->power_mode;
#ifndef RSI_BLKSZ
	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
		pwr_ctl |= ROD_CTL;
# ifndef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
		pwr_ctl |= SD_CMD_OD;
# endif
	}

	if (ios->power_mode != MMC_POWER_OFF)
		pwr_ctl |= PWR_ON;
	else
		pwr_ctl &= ~PWR_ON;

	bfin_write_SDH_PWR_CTL(pwr_ctl);
#else
# ifndef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
		cfg |= SD_CMD_OD;
	else
		cfg &= ~SD_CMD_OD;
# endif

	if (ios->power_mode != MMC_POWER_OFF)
		cfg |= PWR_ON;
	else
		cfg &= ~PWR_ON;

	bfin_write_SDH_CFG(cfg);
#endif
	SSYNC();

	if (ios->power_mode == MMC_POWER_ON && ios->clock) {
		unsigned char clk_div;
		clk_div = (get_sclk() / ios->clock - 1) / 2;
		clk_div = min_t(unsigned char, clk_div, 0xFF);
		clk_ctl |= clk_div;
		clk_ctl |= CLK_E;
		host->clk_div = clk_div;
		bfin_write_SDH_CLK_CTL(clk_ctl);
	} else
		sdh_stop_clock(host);

	/* set up sdh interrupt mask*/
	if (ios->power_mode == MMC_POWER_ON)
		bfin_write_SDH_MASK0(DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL |
			RX_OVERRUN | TX_UNDERRUN | CMD_SENT | CMD_RESP_END |
			CMD_TIME_OUT | CMD_CRC_FAIL);
	else
		bfin_write_SDH_MASK0(0);
	SSYNC();

	spin_unlock(&host->lock);

	dev_dbg(mmc_dev(host->mmc), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
		host->clk_div,
		host->clk_div ? get_sclk() / (2 * (host->clk_div + 1)) : 0,
		ios->clock);
}

static const struct mmc_host_ops sdh_ops = {
	.request	= sdh_request,
	.set_ios	= sdh_set_ios,
};

static irqreturn_t sdh_dma_irq(int irq, void *devid)
{
	struct sdh_host *host = devid;

	dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04lx\n", __func__,
		get_dma_curr_irqstat(host->dma_ch));
	clear_dma_irqstat(host->dma_ch);
	SSYNC();

	return IRQ_HANDLED;
}

static irqreturn_t sdh_stat_irq(int irq, void *devid)
{
	struct sdh_host *host = devid;
	unsigned int status;
	int handled = 0;

	dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);

	spin_lock(&host->lock);

	status = bfin_read_SDH_E_STATUS();
	if (status & SD_CARD_DET) {
		mmc_detect_change(host->mmc, 0);
		bfin_write_SDH_E_STATUS(SD_CARD_DET);
	}
	status = bfin_read_SDH_STATUS();
	if (status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL)) {
		handled |= sdh_cmd_done(host, status);
		bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | \
				CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
		SSYNC();
	}

	status = bfin_read_SDH_STATUS();
	if (status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN))
		handled |= sdh_data_done(host, status);

	spin_unlock(&host->lock);

	dev_dbg(mmc_dev(host->mmc), "%s exit\n\n", __func__);

	return IRQ_RETVAL(handled);
}

static void sdh_reset(void)
{
#if defined(CONFIG_BF54x)
	/* Secure Digital Host shares DMA with Nand controller */
	bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
#endif

	bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
	SSYNC();

	/* Disable card inserting detection pin. set MMC_CAP_NEEDS_POLL, and
	 * mmc stack will do the detection.
	 */
	bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
	SSYNC();
}

static int sdh_probe(struct platform_device *pdev)
{
	struct mmc_host *mmc;
	struct sdh_host *host;
	struct bfin_sd_host *drv_data = get_sdh_data(pdev);
	int ret;

	if (!drv_data) {
		dev_err(&pdev->dev, "missing platform driver data\n");
		ret = -EINVAL;
		goto out;
	}

	mmc = mmc_alloc_host(sizeof(struct sdh_host), &pdev->dev);
	if (!mmc) {
		ret = -ENOMEM;
		goto out;
	}

	mmc->ops = &sdh_ops;
#if defined(CONFIG_BF51x)
	mmc->max_segs = 1;
#else
	mmc->max_segs = PAGE_SIZE / sizeof(struct dma_desc_array);
#endif
#ifdef RSI_BLKSZ
	mmc->max_seg_size = -1;
#else
	mmc->max_seg_size = 1 << 16;
#endif
	mmc->max_blk_size = 1 << 11;
	mmc->max_blk_count = 1 << 11;
	mmc->max_req_size = PAGE_SIZE;
	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
	mmc->f_max = get_sclk();
	mmc->f_min = mmc->f_max >> 9;
	mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL;
	host = mmc_priv(mmc);
	host->mmc = mmc;
	host->sclk = get_sclk();

	spin_lock_init(&host->lock);
	host->irq = drv_data->irq_int0;
	host->dma_ch = drv_data->dma_chan;

	ret = request_dma(host->dma_ch, DRIVER_NAME "DMA");
	if (ret) {
		dev_err(&pdev->dev, "unable to request DMA channel\n");
		goto out1;
	}

	ret = set_dma_callback(host->dma_ch, sdh_dma_irq, host);
	if (ret) {
		dev_err(&pdev->dev, "unable to request DMA irq\n");
		goto out2;
	}

	host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
	if (host->sg_cpu == NULL) {
		ret = -ENOMEM;
		goto out2;
	}

	platform_set_drvdata(pdev, mmc);

	ret = request_irq(host->irq, sdh_stat_irq, 0, "SDH Status IRQ", host);
	if (ret) {
		dev_err(&pdev->dev, "unable to request status irq\n");
		goto out3;
	}

	ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
	if (ret) {
		dev_err(&pdev->dev, "unable to request peripheral pins\n");
		goto out4;
	}

	sdh_reset();

	mmc_add_host(mmc);
	return 0;

out4:
	free_irq(host->irq, host);
out3:
	mmc_remove_host(mmc);
	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
out2:
	free_dma(host->dma_ch);
out1:
	mmc_free_host(mmc);
 out:
	return ret;
}

static int sdh_remove(struct platform_device *pdev)
{
	struct mmc_host *mmc = platform_get_drvdata(pdev);

	if (mmc) {
		struct sdh_host *host = mmc_priv(mmc);

		mmc_remove_host(mmc);

		sdh_stop_clock(host);
		free_irq(host->irq, host);
		free_dma(host->dma_ch);
		dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);

		mmc_free_host(mmc);
	}

	return 0;
}

#ifdef CONFIG_PM
static int sdh_suspend(struct platform_device *dev, pm_message_t state)
{
	struct bfin_sd_host *drv_data = get_sdh_data(dev);

	peripheral_free_list(drv_data->pin_req);

	return 0;
}

static int sdh_resume(struct platform_device *dev)
{
	struct bfin_sd_host *drv_data = get_sdh_data(dev);
	int ret = 0;

	ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
	if (ret) {
		dev_err(&dev->dev, "unable to request peripheral pins\n");
		return ret;
	}

	sdh_reset();
	return ret;
}
#else
# define sdh_suspend NULL
# define sdh_resume  NULL
#endif

static struct platform_driver sdh_driver = {
	.probe   = sdh_probe,
	.remove  = sdh_remove,
	.suspend = sdh_suspend,
	.resume  = sdh_resume,
	.driver  = {
		.name = DRIVER_NAME,
	},
};

module_platform_driver(sdh_driver);

MODULE_DESCRIPTION("Blackfin Secure Digital Host Driver");
MODULE_AUTHOR("Cliff Cai, Roy Huang");
MODULE_LICENSE("GPL");
Commit	Line	Data
eb962d5b CC	1	/*
	2	* bfin_sdh.c - Analog Devices Blackfin SDH Controller
	3	*
	4	* Copyright (C) 2007-2009 Analog Device Inc.
	5	*
	6	* Licensed under the GPL-2 or later.
	7	*/
	8
	9	#define DRIVER_NAME "bfin-sdh"
	10
	11	#include <linux/module.h>
	12	#include <linux/init.h>
	13	#include <linux/ioport.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/delay.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/dma-mapping.h>
	18	#include <linux/mmc/host.h>
	19	#include <linux/proc_fs.h>
5a0e3ad6	20	#include <linux/gfp.h>
eb962d5b CC	21
	22	#include <asm/cacheflush.h>
	23	#include <asm/dma.h>
	24	#include <asm/portmux.h>
	25	#include <asm/bfin_sdh.h>
	26
4ffdcf04	27	#if defined(CONFIG_BF51x) \|\| defined(__ADSPBF60x__)
eb962d5b CC	28	#define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CTL
	29	#define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CTL
	30	#define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
	31	#define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
	32	#define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
	33	#define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
	34	#define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
	35	#define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
	36	#define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
	37	#define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
	38	#define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CTL
	39	#define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CTL
	40	#define bfin_read_SDH_DATA_CNT bfin_read_RSI_DATA_CNT
	41	#define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUS_CLR
	42	#define bfin_read_SDH_E_STATUS bfin_read_RSI_E_STATUS
	43	#define bfin_write_SDH_E_STATUS bfin_write_RSI_E_STATUS
	44	#define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
	45	#define bfin_write_SDH_MASK0 bfin_write_RSI_MASK0
4ffdcf04	46	#define bfin_write_SDH_E_MASK bfin_write_RSI_E_MASK
eb962d5b CC	47	#define bfin_read_SDH_CFG bfin_read_RSI_CFG
eb962d5b CC	48	#define bfin_write_SDH_CFG bfin_write_RSI_CFG
4ffdcf04 SZ	49	# if defined(__ADSPBF60x__)
	50	# define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ
	51	# define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ
	52	# else
	53	# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CTL
	54	# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CTL
	55	# endif
eb962d5b CC	56	#endif
eb962d5b CC	57
eb962d5b CC	58	struct sdh_host {
	59	struct mmc_host *mmc;
	60	spinlock_t lock;
	61	struct resource *res;
	62	void __iomem *base;
	63	int irq;
	64	int stat_irq;
	65	int dma_ch;
	66	int dma_dir;
	67	struct dma_desc_array *sg_cpu;
	68	dma_addr_t sg_dma;
	69	int dma_len;
	70
4ffdcf04	71	unsigned long sclk;
eb962d5b CC	72	unsigned int imask;
	73	unsigned int power_mode;
	74	unsigned int clk_div;
	75
	76	struct mmc_request *mrq;
	77	struct mmc_command *cmd;
	78	struct mmc_data *data;
	79	};
	80
	81	static struct bfin_sd_host get_sdh_data(struct platform_device pdev)
	82	{
	83	return pdev->dev.platform_data;
	84	}
	85
	86	static void sdh_stop_clock(struct sdh_host *host)
	87	{
	88	bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() & ~CLK_E);
	89	SSYNC();
	90	}
	91
	92	static void sdh_enable_stat_irq(struct sdh_host *host, unsigned int mask)
	93	{
	94	unsigned long flags;
	95
	96	spin_lock_irqsave(&host->lock, flags);
	97	host->imask \|= mask;
	98	bfin_write_SDH_MASK0(mask);
	99	SSYNC();
	100	spin_unlock_irqrestore(&host->lock, flags);
	101	}
	102
	103	static void sdh_disable_stat_irq(struct sdh_host *host, unsigned int mask)
	104	{
	105	unsigned long flags;
	106
	107	spin_lock_irqsave(&host->lock, flags);
	108	host->imask &= ~mask;
	109	bfin_write_SDH_MASK0(host->imask);
	110	SSYNC();
	111	spin_unlock_irqrestore(&host->lock, flags);
	112	}
	113
	114	static int sdh_setup_data(struct sdh_host host, struct mmc_data data)
	115	{
	116	unsigned int length;
	117	unsigned int data_ctl;
	118	unsigned int dma_cfg;
729adf1b	119	unsigned int cycle_ns, timeout;
eb962d5b CC	120
	121	dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags);
	122	host->data = data;
	123	data_ctl = 0;
	124	dma_cfg = 0;
	125
	126	length = data->blksz * data->blocks;
	127	bfin_write_SDH_DATA_LGTH(length);
	128
eb962d5b CC	129	if (data->flags & MMC_DATA_READ)
	130	data_ctl \|= DTX_DIR;
	131	/* Only supports power-of-2 block size */
	132	if (data->blksz & (data->blksz - 1))
	133	return -EINVAL;
4ffdcf04	134	#ifndef RSI_BLKSZ
eb962d5b	135	data_ctl \|= ((ffs(data->blksz) - 1) << 4);
4ffdcf04 SZ	136	#else
	137	bfin_write_SDH_BLK_SIZE(data->blksz);
	138	#endif
eb962d5b CC	139
eb962d5b CC	140	bfin_write_SDH_DATA_CTL(data_ctl);
729adf1b	141	/* the time of a host clock period in ns */
4ffdcf04	142	cycle_ns = 1000000000 / (host->sclk / (2 * (host->clk_div + 1)));
729adf1b CC	143	timeout = data->timeout_ns / cycle_ns;
	144	timeout += data->timeout_clks;
	145	bfin_write_SDH_DATA_TIMER(timeout);
eb962d5b CC	146	SSYNC();
	147
	148	if (data->flags & MMC_DATA_READ) {
	149	host->dma_dir = DMA_FROM_DEVICE;
	150	dma_cfg \|= WNR;
	151	} else
	152	host->dma_dir = DMA_TO_DEVICE;
	153
	154	sdh_enable_stat_irq(host, (DAT_CRC_FAIL \| DAT_TIME_OUT \| DAT_END));
	155	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
4ffdcf04 SZ	156	#if defined(CONFIG_BF54x) \|\| defined(CONFIG_BF60x)
	157	dma_cfg \|= DMAFLOW_ARRAY \| RESTART \| WDSIZE_32 \| DMAEN;
	158	# ifdef RSI_BLKSZ
	159	dma_cfg \|= PSIZE_32 \| NDSIZE_3;
	160	# else
	161	dma_cfg \|= NDSIZE_5;
	162	# endif
eb962d5b	163	{
c744d988	164	struct scatterlist *sg;
eb962d5b CC	165	int i;
	166	for_each_sg(data->sg, sg, host->dma_len, i) {
	167	host->sg_cpu[i].start_addr = sg_dma_address(sg);
	168	host->sg_cpu[i].cfg = dma_cfg;
	169	host->sg_cpu[i].x_count = sg_dma_len(sg) / 4;
	170	host->sg_cpu[i].x_modify = 4;
	171	dev_dbg(mmc_dev(host->mmc), "%d: start_addr:0x%lx, "
4ffdcf04	172	"cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
eb962d5b CC	173	i, host->sg_cpu[i].start_addr,
	174	host->sg_cpu[i].cfg, host->sg_cpu[i].x_count,
	175	host->sg_cpu[i].x_modify);
	176	}
	177	}
	178	flush_dcache_range((unsigned int)host->sg_cpu,
	179	(unsigned int)host->sg_cpu +
	180	host->dma_len * sizeof(struct dma_desc_array));
	181	/* Set the last descriptor to stop mode */
	182	host->sg_cpu[host->dma_len - 1].cfg &= ~(DMAFLOW \| NDSIZE);
	183	host->sg_cpu[host->dma_len - 1].cfg \|= DI_EN;
	184
	185	set_dma_curr_desc_addr(host->dma_ch, (unsigned long *)host->sg_dma);
	186	set_dma_x_count(host->dma_ch, 0);
	187	set_dma_x_modify(host->dma_ch, 0);
4ffdcf04	188	SSYNC();
eb962d5b CC	189	set_dma_config(host->dma_ch, dma_cfg);
	190	#elif defined(CONFIG_BF51x)
	191	/* RSI DMA doesn't work in array mode */
	192	dma_cfg \|= WDSIZE_32 \| DMAEN;
	193	set_dma_start_addr(host->dma_ch, sg_dma_address(&data->sg[0]));
	194	set_dma_x_count(host->dma_ch, length / 4);
	195	set_dma_x_modify(host->dma_ch, 4);
4ffdcf04	196	SSYNC();
eb962d5b CC	197	set_dma_config(host->dma_ch, dma_cfg);
	198	#endif
	199	bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() \| DTX_DMA_E \| DTX_E);
	200
	201	SSYNC();
	202
	203	dev_dbg(mmc_dev(host->mmc), "%s exit\n", __func__);
	204	return 0;
	205	}
	206
	207	static void sdh_start_cmd(struct sdh_host host, struct mmc_command cmd)
	208	{
	209	unsigned int sdh_cmd;
	210	unsigned int stat_mask;
	211
	212	dev_dbg(mmc_dev(host->mmc), "%s enter cmd: 0x%p\n", __func__, cmd);
	213	WARN_ON(host->cmd != NULL);
	214	host->cmd = cmd;
	215
	216	sdh_cmd = 0;
	217	stat_mask = 0;
	218
	219	sdh_cmd \|= cmd->opcode;
	220
	221	if (cmd->flags & MMC_RSP_PRESENT) {
	222	sdh_cmd \|= CMD_RSP;
	223	stat_mask \|= CMD_RESP_END;
	224	} else {
	225	stat_mask \|= CMD_SENT;
	226	}
	227
	228	if (cmd->flags & MMC_RSP_136)
	229	sdh_cmd \|= CMD_L_RSP;
	230
	231	stat_mask \|= CMD_CRC_FAIL \| CMD_TIME_OUT;
	232
	233	sdh_enable_stat_irq(host, stat_mask);
	234
	235	bfin_write_SDH_ARGUMENT(cmd->arg);
	236	bfin_write_SDH_COMMAND(sdh_cmd \| CMD_E);
	237	bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() \| CLK_E);
	238	SSYNC();
	239	}
	240
	241	static void sdh_finish_request(struct sdh_host host, struct mmc_request mrq)
	242	{
	243	dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
	244	host->mrq = NULL;
	245	host->cmd = NULL;
	246	host->data = NULL;
	247	mmc_request_done(host->mmc, mrq);
	248	}
	249
	250	static int sdh_cmd_done(struct sdh_host *host, unsigned int stat)
	251	{
	252	struct mmc_command *cmd = host->cmd;
	253	int ret = 0;
	254
	255	dev_dbg(mmc_dev(host->mmc), "%s enter cmd: %p\n", __func__, cmd);
	256	if (!cmd)
	257	return 0;
	258
	259	host->cmd = NULL;
	260
261	if (cmd->flags & MMC_RSP_PRESENT) {
262	cmd->resp[0] = bfin_read_SDH_RESPONSE0();
263	if (cmd->flags & MMC_RSP_136) {
264	cmd->resp[1] = bfin_read_SDH_RESPONSE1();
265	cmd->resp[2] = bfin_read_SDH_RESPONSE2();
266	cmd->resp[3] = bfin_read_SDH_RESPONSE3();
267	}
268	}
269	if (stat & CMD_TIME_OUT)
270	cmd->error = -ETIMEDOUT;
271	else if (stat & CMD_CRC_FAIL && cmd->flags & MMC_RSP_CRC)
272	cmd->error = -EILSEQ;
273
274	sdh_disable_stat_irq(host, (CMD_SENT \| CMD_RESP_END \| CMD_TIME_OUT \| CMD_CRC_FAIL));
275
276	if (host->data && !cmd->error) {
277	if (host->data->flags & MMC_DATA_WRITE) {
278	ret = sdh_setup_data(host, host->data);
279	if (ret)
280	return 0;
281	}
282
283	sdh_enable_stat_irq(host, DAT_END \| RX_OVERRUN \| TX_UNDERRUN \| DAT_TIME_OUT);
284	} else
285	sdh_finish_request(host, host->mrq);
286
287	return 1;
288	}
289
290	static int sdh_data_done(struct sdh_host *host, unsigned int stat)
291	{
292	struct mmc_data *data = host->data;
293
294	dev_dbg(mmc_dev(host->mmc), "%s enter stat: 0x%x\n", __func__, stat);
295	if (!data)
296	return 0;
297
298	disable_dma(host->dma_ch);
299	dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
300	host->dma_dir);
301
302	if (stat & DAT_TIME_OUT)
303	data->error = -ETIMEDOUT;
304	else if (stat & DAT_CRC_FAIL)
305	data->error = -EILSEQ;
306	else if (stat & (RX_OVERRUN \| TX_UNDERRUN))
307	data->error = -EIO;
308
309	if (!data->error)
310	data->bytes_xfered = data->blocks * data->blksz;
311	else
312	data->bytes_xfered = 0;
313
eb962d5b CC	314	bfin_write_SDH_STATUS_CLR(DAT_END_STAT \| DAT_TIMEOUT_STAT \| \
	315	DAT_CRC_FAIL_STAT \| DAT_BLK_END_STAT \| RX_OVERRUN \| TX_UNDERRUN);
	316	bfin_write_SDH_DATA_CTL(0);
	317	SSYNC();
	318
	319	host->data = NULL;
	320	if (host->mrq->stop) {
	321	sdh_stop_clock(host);
	322	sdh_start_cmd(host, host->mrq->stop);
	323	} else {
	324	sdh_finish_request(host, host->mrq);
	325	}
	326
	327	return 1;
	328	}
	329
	330	static void sdh_request(struct mmc_host mmc, struct mmc_request mrq)
	331	{
	332	struct sdh_host *host = mmc_priv(mmc);
	333	int ret = 0;
	334
	335	dev_dbg(mmc_dev(host->mmc), "%s enter, mrp:%p, cmd:%p\n", __func__, mrq, mrq->cmd);
	336	WARN_ON(host->mrq != NULL);
	337
4ffdcf04	338	spin_lock(&host->lock);
eb962d5b CC	339	host->mrq = mrq;
	340	host->data = mrq->data;
	341
	342	if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
	343	ret = sdh_setup_data(host, mrq->data);
	344	if (ret)
4ffdcf04	345	goto data_err;
eb962d5b CC	346	}
	347
	348	sdh_start_cmd(host, mrq->cmd);
4ffdcf04 SZ	349	data_err:
4ffdcf04 SZ	350	spin_unlock(&host->lock);
eb962d5b CC	351	}
	352
	353	static void sdh_set_ios(struct mmc_host mmc, struct mmc_ios ios)
	354	{
	355	struct sdh_host *host;
eb962d5b	356	u16 clk_ctl = 0;
4ffdcf04	357	#ifndef RSI_BLKSZ
eb962d5b	358	u16 pwr_ctl = 0;
4ffdcf04	359	#endif
eb962d5b CC	360	u16 cfg;
	361	host = mmc_priv(mmc);
	362
4ffdcf04	363	spin_lock(&host->lock);
eb962d5b	364
4ffdcf04 SZ	365	cfg = bfin_read_SDH_CFG();
	366	cfg \|= MWE;
	367	switch (ios->bus_width) {
	368	case MMC_BUS_WIDTH_4:
	369	#ifndef RSI_BLKSZ
eb962d5b	370	cfg &= ~PD_SDDAT3;
4ffdcf04	371	#endif
eb962d5b CC	372	cfg \|= PUP_SDDAT3;
eb962d5b CC	373	/* Enable 4 bit SDIO */
4ffdcf04 SZ	374	cfg \|= SD4E;
	375	clk_ctl \|= WIDE_BUS_4;
	376	break;
	377	case MMC_BUS_WIDTH_8:
	378	#ifndef RSI_BLKSZ
	379	cfg &= ~PD_SDDAT3;
	380	#endif
	381	cfg \|= PUP_SDDAT3;
	382	/* Disable 4 bit SDIO */
	383	cfg &= ~SD4E;
	384	clk_ctl \|= BYTE_BUS_8;
	385	break;
	386	default:
	387	cfg &= ~PUP_SDDAT3;
	388	/* Disable 4 bit SDIO */
	389	cfg &= ~SD4E;
eb962d5b	390	}
e69e4dff	391	bfin_write_SDH_CFG(cfg);
eb962d5b	392
eb962d5b	393	host->power_mode = ios->power_mode;
4ffdcf04 SZ	394	#ifndef RSI_BLKSZ
	395	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
	396	pwr_ctl \|= ROD_CTL;
	397	# ifndef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
	398	pwr_ctl \|= SD_CMD_OD;
	399	# endif
	400	}
	401
	402	if (ios->power_mode != MMC_POWER_OFF)
eb962d5b	403	pwr_ctl \|= PWR_ON;
4ffdcf04 SZ	404	else
4ffdcf04 SZ	405	pwr_ctl &= ~PWR_ON;
eb962d5b CC	406
eb962d5b CC	407	bfin_write_SDH_PWR_CTL(pwr_ctl);
4ffdcf04 SZ	408	#else
	409	# ifndef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
	410	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
	411	cfg \|= SD_CMD_OD;
	412	else
	413	cfg &= ~SD_CMD_OD;
	414	# endif
	415
4ffdcf04 SZ	416	if (ios->power_mode != MMC_POWER_OFF)
	417	cfg \|= PWR_ON;
	418	else
	419	cfg &= ~PWR_ON;
	420
	421	bfin_write_SDH_CFG(cfg);
	422	#endif
eb962d5b CC	423	SSYNC();
eb962d5b CC	424
4ffdcf04 SZ	425	if (ios->power_mode == MMC_POWER_ON && ios->clock) {
	426	unsigned char clk_div;
	427	clk_div = (get_sclk() / ios->clock - 1) / 2;
	428	clk_div = min_t(unsigned char, clk_div, 0xFF);
	429	clk_ctl \|= clk_div;
	430	clk_ctl \|= CLK_E;
	431	host->clk_div = clk_div;
	432	bfin_write_SDH_CLK_CTL(clk_ctl);
4ffdcf04 SZ	433	} else
	434	sdh_stop_clock(host);
	435
	436	/* set up sdh interrupt mask*/
	437	if (ios->power_mode == MMC_POWER_ON)
	438	bfin_write_SDH_MASK0(DAT_END \| DAT_TIME_OUT \| DAT_CRC_FAIL \|
	439	RX_OVERRUN \| TX_UNDERRUN \| CMD_SENT \| CMD_RESP_END \|
	440	CMD_TIME_OUT \| CMD_CRC_FAIL);
	441	else
	442	bfin_write_SDH_MASK0(0);
	443	SSYNC();
	444
	445	spin_unlock(&host->lock);
eb962d5b CC	446
	447	dev_dbg(mmc_dev(host->mmc), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
	448	host->clk_div,
	449	host->clk_div ? get_sclk() / (2 * (host->clk_div + 1)) : 0,
	450	ios->clock);
	451	}
	452
	453	static const struct mmc_host_ops sdh_ops = {
	454	.request = sdh_request,
	455	.set_ios = sdh_set_ios,
	456	};
	457
	458	static irqreturn_t sdh_dma_irq(int irq, void *devid)
	459	{
	460	struct sdh_host *host = devid;
	461
4ffdcf04	462	dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04lx\n", __func__,
eb962d5b CC	463	get_dma_curr_irqstat(host->dma_ch));
	464	clear_dma_irqstat(host->dma_ch);
	465	SSYNC();
	466
	467	return IRQ_HANDLED;
	468	}
	469
	470	static irqreturn_t sdh_stat_irq(int irq, void *devid)
	471	{
	472	struct sdh_host *host = devid;
	473	unsigned int status;
	474	int handled = 0;
	475
	476	dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
4ffdcf04 SZ	477
	478	spin_lock(&host->lock);
	479
eb962d5b CC	480	status = bfin_read_SDH_E_STATUS();
	481	if (status & SD_CARD_DET) {
	482	mmc_detect_change(host->mmc, 0);
	483	bfin_write_SDH_E_STATUS(SD_CARD_DET);
	484	}
	485	status = bfin_read_SDH_STATUS();
	486	if (status & (CMD_SENT \| CMD_RESP_END \| CMD_TIME_OUT \| CMD_CRC_FAIL)) {
	487	handled \|= sdh_cmd_done(host, status);
	488	bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT \| CMD_RESP_END_STAT \| \
	489	CMD_TIMEOUT_STAT \| CMD_CRC_FAIL_STAT);
	490	SSYNC();
	491	}
	492
	493	status = bfin_read_SDH_STATUS();
	494	if (status & (DAT_END \| DAT_TIME_OUT \| DAT_CRC_FAIL \| RX_OVERRUN \| TX_UNDERRUN))
	495	handled \|= sdh_data_done(host, status);
	496
4ffdcf04 SZ	497	spin_unlock(&host->lock);
4ffdcf04 SZ	498
eb962d5b CC	499	dev_dbg(mmc_dev(host->mmc), "%s exit\n\n", __func__);
	500
	501	return IRQ_RETVAL(handled);
	502	}
	503
7a8a43c4 SZ	504	static void sdh_reset(void)
	505	{
	506	#if defined(CONFIG_BF54x)
	507	/* Secure Digital Host shares DMA with Nand controller */
	508	bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() \| 0x1);
	509	#endif
	510
	511	bfin_write_SDH_CFG(bfin_read_SDH_CFG() \| CLKS_EN);
	512	SSYNC();
	513
	514	/* Disable card inserting detection pin. set MMC_CAP_NEEDS_POLL, and
	515	* mmc stack will do the detection.
	516	*/
	517	bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) \| (PUP_SDDAT \| PUP_SDDAT3));
	518	SSYNC();
	519	}
	520
c3be1efd	521	static int sdh_probe(struct platform_device *pdev)
eb962d5b CC	522	{
	523	struct mmc_host *mmc;
	524	struct sdh_host *host;
	525	struct bfin_sd_host *drv_data = get_sdh_data(pdev);
	526	int ret;
	527
	528	if (!drv_data) {
	529	dev_err(&pdev->dev, "missing platform driver data\n");
	530	ret = -EINVAL;
	531	goto out;
	532	}
	533
a34650f0	534	mmc = mmc_alloc_host(sizeof(struct sdh_host), &pdev->dev);
eb962d5b CC	535	if (!mmc) {
	536	ret = -ENOMEM;
	537	goto out;
	538	}
	539
	540	mmc->ops = &sdh_ops;
4ffdcf04	541	#if defined(CONFIG_BF51x)
0462566b	542	mmc->max_segs = 1;
4ffdcf04 SZ	543	#else
4ffdcf04 SZ	544	mmc->max_segs = PAGE_SIZE / sizeof(struct dma_desc_array);
0462566b	545	#endif
4ffdcf04 SZ	546	#ifdef RSI_BLKSZ
	547	mmc->max_seg_size = -1;
	548	#else
eb962d5b	549	mmc->max_seg_size = 1 << 16;
4ffdcf04	550	#endif
eb962d5b CC	551	mmc->max_blk_size = 1 << 11;
	552	mmc->max_blk_count = 1 << 11;
	553	mmc->max_req_size = PAGE_SIZE;
	554	mmc->ocr_avail = MMC_VDD_32_33 \| MMC_VDD_33_34;
	555	mmc->f_max = get_sclk();
	556	mmc->f_min = mmc->f_max >> 9;
	557	mmc->caps = MMC_CAP_4_BIT_DATA \| MMC_CAP_NEEDS_POLL;
	558	host = mmc_priv(mmc);
	559	host->mmc = mmc;
4ffdcf04	560	host->sclk = get_sclk();
eb962d5b CC	561
	562	spin_lock_init(&host->lock);
	563	host->irq = drv_data->irq_int0;
	564	host->dma_ch = drv_data->dma_chan;
	565
	566	ret = request_dma(host->dma_ch, DRIVER_NAME "DMA");
	567	if (ret) {
	568	dev_err(&pdev->dev, "unable to request DMA channel\n");
	569	goto out1;
	570	}
	571
	572	ret = set_dma_callback(host->dma_ch, sdh_dma_irq, host);
	573	if (ret) {
	574	dev_err(&pdev->dev, "unable to request DMA irq\n");
	575	goto out2;
	576	}
	577
	578	host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
	579	if (host->sg_cpu == NULL) {
	580	ret = -ENOMEM;
	581	goto out2;
	582	}
	583
	584	platform_set_drvdata(pdev, mmc);
eb962d5b CC	585
	586	ret = request_irq(host->irq, sdh_stat_irq, 0, "SDH Status IRQ", host);
	587	if (ret) {
	588	dev_err(&pdev->dev, "unable to request status irq\n");
	589	goto out3;
	590	}
	591
	592	ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
	593	if (ret) {
	594	dev_err(&pdev->dev, "unable to request peripheral pins\n");
	595	goto out4;
	596	}
eb962d5b	597
7a8a43c4	598	sdh_reset();
eb962d5b	599
4ffdcf04	600	mmc_add_host(mmc);
eb962d5b CC	601	return 0;
	602
	603	out4:
	604	free_irq(host->irq, host);
	605	out3:
	606	mmc_remove_host(mmc);
	607	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
	608	out2:
	609	free_dma(host->dma_ch);
	610	out1:
	611	mmc_free_host(mmc);
	612	out:
	613	return ret;
	614	}
	615
6e0ee714	616	static int sdh_remove(struct platform_device *pdev)
eb962d5b CC	617	{
	618	struct mmc_host *mmc = platform_get_drvdata(pdev);
	619
eb962d5b CC	620	if (mmc) {
	621	struct sdh_host *host = mmc_priv(mmc);
	622
	623	mmc_remove_host(mmc);
	624
	625	sdh_stop_clock(host);
	626	free_irq(host->irq, host);
	627	free_dma(host->dma_ch);
	628	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
	629
	630	mmc_free_host(mmc);
	631	}
	632
	633	return 0;
	634	}
	635
	636	#ifdef CONFIG_PM
	637	static int sdh_suspend(struct platform_device *dev, pm_message_t state)
	638	{
eb962d5b	639	struct bfin_sd_host *drv_data = get_sdh_data(dev);
eb962d5b	640
eb962d5b CC	641	peripheral_free_list(drv_data->pin_req);
eb962d5b CC	642
15a6af4d	643	return 0;
eb962d5b CC	644	}
	645
	646	static int sdh_resume(struct platform_device *dev)
	647	{
eb962d5b CC	648	struct bfin_sd_host *drv_data = get_sdh_data(dev);
	649	int ret = 0;
	650
	651	ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
	652	if (ret) {
	653	dev_err(&dev->dev, "unable to request peripheral pins\n");
	654	return ret;
	655	}
	656
7a8a43c4	657	sdh_reset();
eb962d5b CC	658	return ret;
	659	}
	660	#else
	661	# define sdh_suspend NULL
	662	# define sdh_resume NULL
	663	#endif
	664
	665	static struct platform_driver sdh_driver = {
	666	.probe = sdh_probe,
0433c143	667	.remove = sdh_remove,
eb962d5b CC	668	.suspend = sdh_suspend,
	669	.resume = sdh_resume,
	670	.driver = {
	671	.name = DRIVER_NAME,
	672	},
	673	};
	674
d1f81a64	675	module_platform_driver(sdh_driver);
eb962d5b CC	676
	677	MODULE_DESCRIPTION("Blackfin Secure Digital Host Driver");
	678	MODULE_AUTHOR("Cliff Cai, Roy Huang");
	679	MODULE_LICENSE("GPL");