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ba3869ff JG |
1 | /* |
2 | * Driver for MMC and SSD cards for Cavium OCTEON and ThunderX SOCs. | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 2012-2017 Cavium Inc. | |
9 | */ | |
10 | ||
11 | #ifndef _CAVIUM_MMC_H_ | |
12 | #define _CAVIUM_MMC_H_ | |
13 | ||
14 | #include <linux/bitops.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/gpio/consumer.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/mmc/host.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/scatterlist.h> | |
21 | #include <linux/semaphore.h> | |
22 | ||
23 | #define CAVIUM_MAX_MMC 4 | |
24 | ||
25 | /* DMA register addresses */ | |
cd76e5c5 JG |
26 | #define MIO_EMM_DMA_FIFO_CFG(x) (0x00 + x->reg_off_dma) |
27 | #define MIO_EMM_DMA_FIFO_ADR(x) (0x10 + x->reg_off_dma) | |
28 | #define MIO_EMM_DMA_FIFO_CMD(x) (0x18 + x->reg_off_dma) | |
29 | #define MIO_EMM_DMA_CFG(x) (0x20 + x->reg_off_dma) | |
30 | #define MIO_EMM_DMA_ADR(x) (0x28 + x->reg_off_dma) | |
31 | #define MIO_EMM_DMA_INT(x) (0x30 + x->reg_off_dma) | |
32 | #define MIO_EMM_DMA_INT_W1S(x) (0x38 + x->reg_off_dma) | |
33 | #define MIO_EMM_DMA_INT_ENA_W1S(x) (0x40 + x->reg_off_dma) | |
34 | #define MIO_EMM_DMA_INT_ENA_W1C(x) (0x48 + x->reg_off_dma) | |
ba3869ff JG |
35 | |
36 | /* register addresses */ | |
37 | #define MIO_EMM_CFG(x) (0x00 + x->reg_off) | |
38 | #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off) | |
39 | #define MIO_EMM_DMA(x) (0x50 + x->reg_off) | |
40 | #define MIO_EMM_CMD(x) (0x58 + x->reg_off) | |
41 | #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off) | |
42 | #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off) | |
43 | #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off) | |
44 | #define MIO_EMM_INT(x) (0x78 + x->reg_off) | |
45 | #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off) | |
46 | #define MIO_EMM_WDOG(x) (0x88 + x->reg_off) | |
47 | #define MIO_EMM_SAMPLE(x) (0x90 + x->reg_off) | |
48 | #define MIO_EMM_STS_MASK(x) (0x98 + x->reg_off) | |
49 | #define MIO_EMM_RCA(x) (0xa0 + x->reg_off) | |
166bac38 JG |
50 | #define MIO_EMM_INT_EN_SET(x) (0xb0 + x->reg_off) |
51 | #define MIO_EMM_INT_EN_CLR(x) (0xb8 + x->reg_off) | |
ba3869ff JG |
52 | #define MIO_EMM_BUF_IDX(x) (0xe0 + x->reg_off) |
53 | #define MIO_EMM_BUF_DAT(x) (0xe8 + x->reg_off) | |
54 | ||
55 | struct cvm_mmc_host { | |
56 | struct device *dev; | |
57 | void __iomem *base; | |
58 | void __iomem *dma_base; | |
59 | int reg_off; | |
60 | int reg_off_dma; | |
61 | u64 emm_cfg; | |
62 | u64 n_minus_one; /* OCTEON II workaround location */ | |
63 | int last_slot; | |
64 | struct clk *clk; | |
65 | int sys_freq; | |
66 | ||
67 | struct mmc_request *current_req; | |
68 | struct sg_mapping_iter smi; | |
69 | bool dma_active; | |
cd76e5c5 | 70 | bool use_sg; |
ba3869ff JG |
71 | |
72 | bool has_ciu3; | |
73 | bool big_dma_addr; | |
74 | bool need_irq_handler_lock; | |
75 | spinlock_t irq_handler_lock; | |
76 | struct semaphore mmc_serializer; | |
77 | ||
78 | struct gpio_desc *global_pwr_gpiod; | |
79 | atomic_t shared_power_users; | |
80 | ||
81 | struct cvm_mmc_slot *slot[CAVIUM_MAX_MMC]; | |
82 | struct platform_device *slot_pdev[CAVIUM_MAX_MMC]; | |
83 | ||
84 | void (*set_shared_power)(struct cvm_mmc_host *, int); | |
85 | void (*acquire_bus)(struct cvm_mmc_host *); | |
86 | void (*release_bus)(struct cvm_mmc_host *); | |
87 | void (*int_enable)(struct cvm_mmc_host *, u64); | |
88 | /* required on some MIPS models */ | |
89 | void (*dmar_fixup)(struct cvm_mmc_host *, struct mmc_command *, | |
90 | struct mmc_data *, u64); | |
91 | void (*dmar_fixup_done)(struct cvm_mmc_host *); | |
92 | }; | |
93 | ||
94 | struct cvm_mmc_slot { | |
95 | struct mmc_host *mmc; /* slot-level mmc_core object */ | |
96 | struct cvm_mmc_host *host; /* common hw for all slots */ | |
97 | ||
98 | u64 clock; | |
99 | ||
100 | u64 cached_switch; | |
101 | u64 cached_rca; | |
102 | ||
103 | unsigned int cmd_cnt; /* sample delay */ | |
104 | unsigned int dat_cnt; /* sample delay */ | |
105 | ||
106 | int bus_id; | |
107 | }; | |
108 | ||
109 | struct cvm_mmc_cr_type { | |
110 | u8 ctype; | |
111 | u8 rtype; | |
112 | }; | |
113 | ||
114 | struct cvm_mmc_cr_mods { | |
115 | u8 ctype_xor; | |
116 | u8 rtype_xor; | |
117 | }; | |
118 | ||
119 | /* Bitfield definitions */ | |
cd76e5c5 JG |
120 | #define MIO_EMM_DMA_FIFO_CFG_CLR BIT_ULL(16) |
121 | #define MIO_EMM_DMA_FIFO_CFG_INT_LVL GENMASK_ULL(12, 8) | |
122 | #define MIO_EMM_DMA_FIFO_CFG_COUNT GENMASK_ULL(4, 0) | |
123 | ||
124 | #define MIO_EMM_DMA_FIFO_CMD_RW BIT_ULL(62) | |
125 | #define MIO_EMM_DMA_FIFO_CMD_INTDIS BIT_ULL(60) | |
126 | #define MIO_EMM_DMA_FIFO_CMD_SWAP32 BIT_ULL(59) | |
127 | #define MIO_EMM_DMA_FIFO_CMD_SWAP16 BIT_ULL(58) | |
128 | #define MIO_EMM_DMA_FIFO_CMD_SWAP8 BIT_ULL(57) | |
129 | #define MIO_EMM_DMA_FIFO_CMD_ENDIAN BIT_ULL(56) | |
130 | #define MIO_EMM_DMA_FIFO_CMD_SIZE GENMASK_ULL(55, 36) | |
131 | ||
ba3869ff JG |
132 | #define MIO_EMM_CMD_SKIP_BUSY BIT_ULL(62) |
133 | #define MIO_EMM_CMD_BUS_ID GENMASK_ULL(61, 60) | |
134 | #define MIO_EMM_CMD_VAL BIT_ULL(59) | |
135 | #define MIO_EMM_CMD_DBUF BIT_ULL(55) | |
136 | #define MIO_EMM_CMD_OFFSET GENMASK_ULL(54, 49) | |
137 | #define MIO_EMM_CMD_CTYPE_XOR GENMASK_ULL(42, 41) | |
138 | #define MIO_EMM_CMD_RTYPE_XOR GENMASK_ULL(40, 38) | |
139 | #define MIO_EMM_CMD_IDX GENMASK_ULL(37, 32) | |
140 | #define MIO_EMM_CMD_ARG GENMASK_ULL(31, 0) | |
141 | ||
142 | #define MIO_EMM_DMA_SKIP_BUSY BIT_ULL(62) | |
143 | #define MIO_EMM_DMA_BUS_ID GENMASK_ULL(61, 60) | |
144 | #define MIO_EMM_DMA_VAL BIT_ULL(59) | |
145 | #define MIO_EMM_DMA_SECTOR BIT_ULL(58) | |
146 | #define MIO_EMM_DMA_DAT_NULL BIT_ULL(57) | |
147 | #define MIO_EMM_DMA_THRES GENMASK_ULL(56, 51) | |
148 | #define MIO_EMM_DMA_REL_WR BIT_ULL(50) | |
149 | #define MIO_EMM_DMA_RW BIT_ULL(49) | |
150 | #define MIO_EMM_DMA_MULTI BIT_ULL(48) | |
151 | #define MIO_EMM_DMA_BLOCK_CNT GENMASK_ULL(47, 32) | |
152 | #define MIO_EMM_DMA_CARD_ADDR GENMASK_ULL(31, 0) | |
153 | ||
154 | #define MIO_EMM_DMA_CFG_EN BIT_ULL(63) | |
155 | #define MIO_EMM_DMA_CFG_RW BIT_ULL(62) | |
156 | #define MIO_EMM_DMA_CFG_CLR BIT_ULL(61) | |
157 | #define MIO_EMM_DMA_CFG_SWAP32 BIT_ULL(59) | |
158 | #define MIO_EMM_DMA_CFG_SWAP16 BIT_ULL(58) | |
159 | #define MIO_EMM_DMA_CFG_SWAP8 BIT_ULL(57) | |
160 | #define MIO_EMM_DMA_CFG_ENDIAN BIT_ULL(56) | |
161 | #define MIO_EMM_DMA_CFG_SIZE GENMASK_ULL(55, 36) | |
162 | #define MIO_EMM_DMA_CFG_ADR GENMASK_ULL(35, 0) | |
163 | ||
164 | #define MIO_EMM_INT_SWITCH_ERR BIT_ULL(6) | |
165 | #define MIO_EMM_INT_SWITCH_DONE BIT_ULL(5) | |
166 | #define MIO_EMM_INT_DMA_ERR BIT_ULL(4) | |
167 | #define MIO_EMM_INT_CMD_ERR BIT_ULL(3) | |
168 | #define MIO_EMM_INT_DMA_DONE BIT_ULL(2) | |
169 | #define MIO_EMM_INT_CMD_DONE BIT_ULL(1) | |
170 | #define MIO_EMM_INT_BUF_DONE BIT_ULL(0) | |
171 | ||
172 | #define MIO_EMM_RSP_STS_BUS_ID GENMASK_ULL(61, 60) | |
173 | #define MIO_EMM_RSP_STS_CMD_VAL BIT_ULL(59) | |
174 | #define MIO_EMM_RSP_STS_SWITCH_VAL BIT_ULL(58) | |
175 | #define MIO_EMM_RSP_STS_DMA_VAL BIT_ULL(57) | |
176 | #define MIO_EMM_RSP_STS_DMA_PEND BIT_ULL(56) | |
177 | #define MIO_EMM_RSP_STS_DBUF_ERR BIT_ULL(28) | |
178 | #define MIO_EMM_RSP_STS_DBUF BIT_ULL(23) | |
179 | #define MIO_EMM_RSP_STS_BLK_TIMEOUT BIT_ULL(22) | |
180 | #define MIO_EMM_RSP_STS_BLK_CRC_ERR BIT_ULL(21) | |
181 | #define MIO_EMM_RSP_STS_RSP_BUSYBIT BIT_ULL(20) | |
182 | #define MIO_EMM_RSP_STS_STP_TIMEOUT BIT_ULL(19) | |
183 | #define MIO_EMM_RSP_STS_STP_CRC_ERR BIT_ULL(18) | |
184 | #define MIO_EMM_RSP_STS_STP_BAD_STS BIT_ULL(17) | |
185 | #define MIO_EMM_RSP_STS_STP_VAL BIT_ULL(16) | |
186 | #define MIO_EMM_RSP_STS_RSP_TIMEOUT BIT_ULL(15) | |
187 | #define MIO_EMM_RSP_STS_RSP_CRC_ERR BIT_ULL(14) | |
188 | #define MIO_EMM_RSP_STS_RSP_BAD_STS BIT_ULL(13) | |
189 | #define MIO_EMM_RSP_STS_RSP_VAL BIT_ULL(12) | |
190 | #define MIO_EMM_RSP_STS_RSP_TYPE GENMASK_ULL(11, 9) | |
191 | #define MIO_EMM_RSP_STS_CMD_TYPE GENMASK_ULL(8, 7) | |
192 | #define MIO_EMM_RSP_STS_CMD_IDX GENMASK_ULL(6, 1) | |
193 | #define MIO_EMM_RSP_STS_CMD_DONE BIT_ULL(0) | |
194 | ||
195 | #define MIO_EMM_SAMPLE_CMD_CNT GENMASK_ULL(25, 16) | |
196 | #define MIO_EMM_SAMPLE_DAT_CNT GENMASK_ULL(9, 0) | |
197 | ||
198 | #define MIO_EMM_SWITCH_BUS_ID GENMASK_ULL(61, 60) | |
199 | #define MIO_EMM_SWITCH_EXE BIT_ULL(59) | |
200 | #define MIO_EMM_SWITCH_ERR0 BIT_ULL(58) | |
201 | #define MIO_EMM_SWITCH_ERR1 BIT_ULL(57) | |
202 | #define MIO_EMM_SWITCH_ERR2 BIT_ULL(56) | |
203 | #define MIO_EMM_SWITCH_HS_TIMING BIT_ULL(48) | |
204 | #define MIO_EMM_SWITCH_BUS_WIDTH GENMASK_ULL(42, 40) | |
205 | #define MIO_EMM_SWITCH_POWER_CLASS GENMASK_ULL(35, 32) | |
206 | #define MIO_EMM_SWITCH_CLK_HI GENMASK_ULL(31, 16) | |
207 | #define MIO_EMM_SWITCH_CLK_LO GENMASK_ULL(15, 0) | |
208 | ||
209 | /* Protoypes */ | |
210 | irqreturn_t cvm_mmc_interrupt(int irq, void *dev_id); | |
211 | int cvm_mmc_of_slot_probe(struct device *dev, struct cvm_mmc_host *host); | |
212 | int cvm_mmc_of_slot_remove(struct cvm_mmc_slot *slot); | |
213 | extern const char *cvm_mmc_irq_names[]; | |
214 | ||
215 | #endif |