[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / dw_mmc-exynos.c

/*
 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
 *
 * Copyright (C) 2012, Samsung Electronics Co., Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/mmc/host.h>
#include <linux/mmc/dw_mmc.h>
#include <linux/mmc/mmc.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>

#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"
#include "dw_mmc-exynos.h"

/* Variations in Exynos specific dw-mshc controller */
enum dw_mci_exynos_type {
	DW_MCI_TYPE_EXYNOS4210,
	DW_MCI_TYPE_EXYNOS4412,
	DW_MCI_TYPE_EXYNOS5250,
	DW_MCI_TYPE_EXYNOS5420,
	DW_MCI_TYPE_EXYNOS5420_SMU,
	DW_MCI_TYPE_EXYNOS7,
	DW_MCI_TYPE_EXYNOS7_SMU,
};

/* Exynos implementation specific driver private data */
struct dw_mci_exynos_priv_data {
	enum dw_mci_exynos_type		ctrl_type;
	u8				ciu_div;
	u32				sdr_timing;
	u32				ddr_timing;
	u32				hs400_timing;
	u32				tuned_sample;
	u32				cur_speed;
	u32				dqs_delay;
	u32				saved_dqs_en;
	u32				saved_strobe_ctrl;
};

static struct dw_mci_exynos_compatible {
	char				*compatible;
	enum dw_mci_exynos_type		ctrl_type;
} exynos_compat[] = {
	{
		.compatible	= "samsung,exynos4210-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS4210,
	}, {
		.compatible	= "samsung,exynos4412-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS4412,
	}, {
		.compatible	= "samsung,exynos5250-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5250,
	}, {
		.compatible	= "samsung,exynos5420-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5420,
	}, {
		.compatible	= "samsung,exynos5420-dw-mshc-smu",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS5420_SMU,
	}, {
		.compatible	= "samsung,exynos7-dw-mshc",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS7,
	}, {
		.compatible	= "samsung,exynos7-dw-mshc-smu",
		.ctrl_type	= DW_MCI_TYPE_EXYNOS7_SMU,
	},
};

static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
		return EXYNOS4412_FIXED_CIU_CLK_DIV;
	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
		return EXYNOS4210_FIXED_CIU_CLK_DIV;
	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
			priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
	else
		return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
}

static void dw_mci_exynos_config_smu(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	/*
	 * If Exynos is provided the Security management,
	 * set for non-ecryption mode at this time.
	 */
	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
		mci_writel(host, MPSBEGIN0, 0);
		mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
		mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
			   SDMMC_MPSCTRL_NON_SECURE_READ_BIT |
			   SDMMC_MPSCTRL_VALID |
			   SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
	}
}

static int dw_mci_exynos_priv_init(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	dw_mci_exynos_config_smu(host);

	if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) {
		priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
		priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
		priv->saved_dqs_en |= AXI_NON_BLOCKING_WR;
		mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
		if (!priv->dqs_delay)
			priv->dqs_delay =
				DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
	}

	host->bus_hz /= (priv->ciu_div + 1);

	return 0;
}

static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	u32 clksel;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		clksel = mci_readl(host, CLKSEL64);
	else
		clksel = mci_readl(host, CLKSEL);

	clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		mci_writel(host, CLKSEL64, clksel);
	else
		mci_writel(host, CLKSEL, clksel);

	/*
	 * Exynos4412 and Exynos5250 extends the use of CMD register with the
	 * use of bit 29 (which is reserved on standard MSHC controllers) for
	 * optionally bypassing the HOLD register for command and data. The
	 * HOLD register should be bypassed in case there is no phase shift
	 * applied on CMD/DATA that is sent to the card.
	 */
	if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel))
		set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags);
}

#ifdef CONFIG_PM_SLEEP
static int dw_mci_exynos_suspend(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);

	return dw_mci_suspend(host);
}

static int dw_mci_exynos_resume(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);

	dw_mci_exynos_config_smu(host);
	return dw_mci_resume(host);
}

/**
 * dw_mci_exynos_resume_noirq - Exynos-specific resume code
 *
 * On exynos5420 there is a silicon errata that will sometimes leave the
 * WAKEUP_INT bit in the CLKSEL register asserted.  This bit is 1 to indicate
 * that it fired and we can clear it by writing a 1 back.  Clear it to prevent
 * interrupts from going off constantly.
 *
 * We run this code on all exynos variants because it doesn't hurt.
 */

static int dw_mci_exynos_resume_noirq(struct device *dev)
{
	struct dw_mci *host = dev_get_drvdata(dev);
	struct dw_mci_exynos_priv_data *priv = host->priv;
	u32 clksel;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		clksel = mci_readl(host, CLKSEL64);
	else
		clksel = mci_readl(host, CLKSEL);

	if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
		if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
			priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
			mci_writel(host, CLKSEL64, clksel);
		else
			mci_writel(host, CLKSEL, clksel);
	}

	return 0;
}
#else
#define dw_mci_exynos_suspend		NULL
#define dw_mci_exynos_resume		NULL
#define dw_mci_exynos_resume_noirq	NULL
#endif /* CONFIG_PM_SLEEP */

static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	u32 dqs, strobe;

	/*
	 * Not supported to configure register
	 * related to HS400
	 */
	if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420)
		return;

	dqs = priv->saved_dqs_en;
	strobe = priv->saved_strobe_ctrl;

	if (timing == MMC_TIMING_MMC_HS400) {
		dqs |= DATA_STROBE_EN;
		strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
	} else {
		dqs &= ~DATA_STROBE_EN;
	}

	mci_writel(host, HS400_DQS_EN, dqs);
	mci_writel(host, HS400_DLINE_CTRL, strobe);
}

static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	unsigned long actual;
	u8 div;
	int ret;
	/*
	 * Don't care if wanted clock is zero or
	 * ciu clock is unavailable
	 */
	if (!wanted || IS_ERR(host->ciu_clk))
		return;

	/* Guaranteed minimum frequency for cclkin */
	if (wanted < EXYNOS_CCLKIN_MIN)
		wanted = EXYNOS_CCLKIN_MIN;

	if (wanted == priv->cur_speed)
		return;

	div = dw_mci_exynos_get_ciu_div(host);
	ret = clk_set_rate(host->ciu_clk, wanted * div);
	if (ret)
		dev_warn(host->dev,
			"failed to set clk-rate %u error: %d\n",
			wanted * div, ret);
	actual = clk_get_rate(host->ciu_clk);
	host->bus_hz = actual / div;
	priv->cur_speed = wanted;
	host->current_speed = 0;
}

static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	unsigned int wanted = ios->clock;
	u32 timing = ios->timing, clksel;

	switch (timing) {
	case MMC_TIMING_MMC_HS400:
		/* Update tuned sample timing */
		clksel = SDMMC_CLKSEL_UP_SAMPLE(
				priv->hs400_timing, priv->tuned_sample);
		wanted <<= 1;
		break;
	case MMC_TIMING_MMC_DDR52:
		clksel = priv->ddr_timing;
		/* Should be double rate for DDR mode */
		if (ios->bus_width == MMC_BUS_WIDTH_8)
			wanted <<= 1;
		break;
	default:
		clksel = priv->sdr_timing;
	}

	/* Set clock timing for the requested speed mode*/
	dw_mci_exynos_set_clksel_timing(host, clksel);

	/* Configure setting for HS400 */
	dw_mci_exynos_config_hs400(host, timing);

	/* Configure clock rate */
	dw_mci_exynos_adjust_clock(host, wanted);
}

static int dw_mci_exynos_parse_dt(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv;
	struct device_node *np = host->dev->of_node;
	u32 timing[2];
	u32 div = 0;
	int idx;
	int ret;

	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
		if (of_device_is_compatible(np, exynos_compat[idx].compatible))
			priv->ctrl_type = exynos_compat[idx].ctrl_type;
	}

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
		priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
		priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
	else {
		of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
		priv->ciu_div = div;
	}

	ret = of_property_read_u32_array(np,
			"samsung,dw-mshc-sdr-timing", timing, 2);
	if (ret)
		return ret;

	priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);

	ret = of_property_read_u32_array(np,
			"samsung,dw-mshc-ddr-timing", timing, 2);
	if (ret)
		return ret;

	priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);

	ret = of_property_read_u32_array(np,
			"samsung,dw-mshc-hs400-timing", timing, 2);
	if (!ret && of_property_read_u32(np,
				"samsung,read-strobe-delay", &priv->dqs_delay))
		dev_dbg(host->dev,
			"read-strobe-delay is not found, assuming usage of default value\n");

	priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
						HS400_FIXED_CIU_CLK_DIV);
	host->priv = priv;
	return 0;
}

static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
	else
		return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
}

static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
{
	u32 clksel;
	struct dw_mci_exynos_priv_data *priv = host->priv;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		clksel = mci_readl(host, CLKSEL64);
	else
		clksel = mci_readl(host, CLKSEL);
	clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		mci_writel(host, CLKSEL64, clksel);
	else
		mci_writel(host, CLKSEL, clksel);
}

static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;
	u32 clksel;
	u8 sample;

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		clksel = mci_readl(host, CLKSEL64);
	else
		clksel = mci_readl(host, CLKSEL);

	sample = (clksel + 1) & 0x7;
	clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
		mci_writel(host, CLKSEL64, clksel);
	else
		mci_writel(host, CLKSEL, clksel);

	return sample;
}

static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
{
	const u8 iter = 8;
	u8 __c;
	s8 i, loc = -1;

	for (i = 0; i < iter; i++) {
		__c = ror8(candiates, i);
		if ((__c & 0xc7) == 0xc7) {
			loc = i;
			goto out;
		}
	}

	for (i = 0; i < iter; i++) {
		__c = ror8(candiates, i);
		if ((__c & 0x83) == 0x83) {
			loc = i;
			goto out;
		}
	}

out:
	return loc;
}

static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
{
	struct dw_mci *host = slot->host;
	struct dw_mci_exynos_priv_data *priv = host->priv;
	struct mmc_host *mmc = slot->mmc;
	u8 start_smpl, smpl, candiates = 0;
	s8 found = -1;
	int ret = 0;

	start_smpl = dw_mci_exynos_get_clksmpl(host);

	do {
		mci_writel(host, TMOUT, ~0);
		smpl = dw_mci_exynos_move_next_clksmpl(host);

		if (!mmc_send_tuning(mmc, opcode, NULL))
			candiates |= (1 << smpl);

	} while (start_smpl != smpl);

	found = dw_mci_exynos_get_best_clksmpl(candiates);
	if (found >= 0) {
		dw_mci_exynos_set_clksmpl(host, found);
		priv->tuned_sample = found;
	} else {
		ret = -EIO;
	}

	return ret;
}

static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
					struct mmc_ios *ios)
{
	struct dw_mci_exynos_priv_data *priv = host->priv;

	dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing);
	dw_mci_exynos_adjust_clock(host, (ios->clock) << 1);

	return 0;
}

/* Common capabilities of Exynos4/Exynos5 SoC */
static unsigned long exynos_dwmmc_caps[4] = {
	MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
};

static const struct dw_mci_drv_data exynos_drv_data = {
	.caps			= exynos_dwmmc_caps,
	.init			= dw_mci_exynos_priv_init,
	.set_ios		= dw_mci_exynos_set_ios,
	.parse_dt		= dw_mci_exynos_parse_dt,
	.execute_tuning		= dw_mci_exynos_execute_tuning,
	.prepare_hs400_tuning	= dw_mci_exynos_prepare_hs400_tuning,
};

static const struct of_device_id dw_mci_exynos_match[] = {
	{ .compatible = "samsung,exynos4412-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5250-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5420-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos5420-dw-mshc-smu",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos7-dw-mshc",
			.data = &exynos_drv_data, },
	{ .compatible = "samsung,exynos7-dw-mshc-smu",
			.data = &exynos_drv_data, },
	{},
};
MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);

static int dw_mci_exynos_probe(struct platform_device *pdev)
{
	const struct dw_mci_drv_data *drv_data;
	const struct of_device_id *match;

	match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
	drv_data = match->data;
	return dw_mci_pltfm_register(pdev, drv_data);
}

static const struct dev_pm_ops dw_mci_exynos_pmops = {
	SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
	.resume_noirq = dw_mci_exynos_resume_noirq,
	.thaw_noirq = dw_mci_exynos_resume_noirq,
	.restore_noirq = dw_mci_exynos_resume_noirq,
};

static struct platform_driver dw_mci_exynos_pltfm_driver = {
	.probe		= dw_mci_exynos_probe,
	.remove		= dw_mci_pltfm_remove,
	.driver		= {
		.name		= "dwmmc_exynos",
		.of_match_table	= dw_mci_exynos_match,
		.pm		= &dw_mci_exynos_pmops,
	},
};

module_platform_driver(dw_mci_exynos_pltfm_driver);

MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:dwmmc_exynos");
Commit	Line	Data
c3665006 TA	1	/*
	2	* Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
	3	*
	4	* Copyright (C) 2012, Samsung Electronics Co., Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/clk.h>
	15	#include <linux/mmc/host.h>
	16	#include <linux/mmc/dw_mmc.h>
c537a1c5	17	#include <linux/mmc/mmc.h>
c3665006 TA	18	#include <linux/of.h>
c3665006 TA	19	#include <linux/of_gpio.h>
c537a1c5	20	#include <linux/slab.h>
c3665006 TA	21
	22	#include "dw_mmc.h"
	23	#include "dw_mmc-pltfm.h"
0b5fce48	24	#include "dw_mmc-exynos.h"
c6d9deda	25
c3665006 TA	26	/* Variations in Exynos specific dw-mshc controller */
	27	enum dw_mci_exynos_type {
	28	DW_MCI_TYPE_EXYNOS4210,
	29	DW_MCI_TYPE_EXYNOS4412,
	30	DW_MCI_TYPE_EXYNOS5250,
00fd041b	31	DW_MCI_TYPE_EXYNOS5420,
6bce431c	32	DW_MCI_TYPE_EXYNOS5420_SMU,
89ad2be7 AK	33	DW_MCI_TYPE_EXYNOS7,
89ad2be7 AK	34	DW_MCI_TYPE_EXYNOS7_SMU,
c3665006 TA	35	};
	36
	37	/* Exynos implementation specific driver private data */
	38	struct dw_mci_exynos_priv_data {
	39	enum dw_mci_exynos_type ctrl_type;
	40	u8 ciu_div;
	41	u32 sdr_timing;
	42	u32 ddr_timing;
80113132 SJ	43	u32 hs400_timing;
80113132 SJ	44	u32 tuned_sample;
c6d9deda	45	u32 cur_speed;
80113132 SJ	46	u32 dqs_delay;
	47	u32 saved_dqs_en;
	48	u32 saved_strobe_ctrl;
c3665006 TA	49	};
	50
	51	static struct dw_mci_exynos_compatible {
	52	char *compatible;
	53	enum dw_mci_exynos_type ctrl_type;
	54	} exynos_compat[] = {
	55	{
	56	.compatible = "samsung,exynos4210-dw-mshc",
	57	.ctrl_type = DW_MCI_TYPE_EXYNOS4210,
	58	}, {
	59	.compatible = "samsung,exynos4412-dw-mshc",
	60	.ctrl_type = DW_MCI_TYPE_EXYNOS4412,
	61	}, {
	62	.compatible = "samsung,exynos5250-dw-mshc",
	63	.ctrl_type = DW_MCI_TYPE_EXYNOS5250,
00fd041b YK	64	}, {
	65	.compatible = "samsung,exynos5420-dw-mshc",
	66	.ctrl_type = DW_MCI_TYPE_EXYNOS5420,
6bce431c YK	67	}, {
	68	.compatible = "samsung,exynos5420-dw-mshc-smu",
	69	.ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
89ad2be7 AK	70	}, {
	71	.compatible = "samsung,exynos7-dw-mshc",
	72	.ctrl_type = DW_MCI_TYPE_EXYNOS7,
	73	}, {
	74	.compatible = "samsung,exynos7-dw-mshc-smu",
	75	.ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
c3665006 TA	76	},
	77	};
	78
80113132 SJ	79	static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
	80	{
	81	struct dw_mci_exynos_priv_data *priv = host->priv;
	82
	83	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
	84	return EXYNOS4412_FIXED_CIU_CLK_DIV;
	85	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
	86	return EXYNOS4210_FIXED_CIU_CLK_DIV;
	87	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	88	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	89	return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
	90	else
	91	return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
	92	}
	93
5659eead	94	static void dw_mci_exynos_config_smu(struct dw_mci *host)
c3665006	95	{
e6c784ed	96	struct dw_mci_exynos_priv_data *priv = host->priv;
c3665006	97
5659eead JC	98	/*
	99	* If Exynos is provided the Security management,
	100	* set for non-ecryption mode at this time.
	101	*/
89ad2be7 AK	102	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU \|\|
89ad2be7 AK	103	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
6bce431c	104	mci_writel(host, MPSBEGIN0, 0);
0b5fce48 SJ	105	mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
	106	mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT \|
	107	SDMMC_MPSCTRL_NON_SECURE_READ_BIT \|
	108	SDMMC_MPSCTRL_VALID \|
	109	SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
6bce431c	110	}
5659eead JC	111	}
	112
	113	static int dw_mci_exynos_priv_init(struct dw_mci *host)
	114	{
	115	struct dw_mci_exynos_priv_data *priv = host->priv;
	116
	117	dw_mci_exynos_config_smu(host);
6bce431c	118
80113132 SJ	119	if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) {
	120	priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
	121	priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
	122	priv->saved_dqs_en \|= AXI_NON_BLOCKING_WR;
	123	mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
	124	if (!priv->dqs_delay)
	125	priv->dqs_delay =
	126	DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
	127	}
	128
a2a1fed8 SJ	129	host->bus_hz /= (priv->ciu_div + 1);
a2a1fed8 SJ	130
c3665006 TA	131	return 0;
	132	}
	133
80113132 SJ	134	static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
	135	{
	136	struct dw_mci_exynos_priv_data *priv = host->priv;
	137	u32 clksel;
	138
	139	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	140	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	141	clksel = mci_readl(host, CLKSEL64);
	142	else
	143	clksel = mci_readl(host, CLKSEL);
	144
	145	clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) \| timing;
	146
	147	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	148	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	149	mci_writel(host, CLKSEL64, clksel);
	150	else
	151	mci_writel(host, CLKSEL, clksel);
aaaaeb7a JC	152
	153	/*
	154	* Exynos4412 and Exynos5250 extends the use of CMD register with the
	155	* use of bit 29 (which is reserved on standard MSHC controllers) for
	156	* optionally bypassing the HOLD register for command and data. The
	157	* HOLD register should be bypassed in case there is no phase shift
	158	* applied on CMD/DATA that is sent to the card.
	159	*/
	160	if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel))
	161	set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags);
80113132 SJ	162	}
80113132 SJ	163
e2c63599 DA	164	#ifdef CONFIG_PM_SLEEP
	165	static int dw_mci_exynos_suspend(struct device *dev)
	166	{
	167	struct dw_mci *host = dev_get_drvdata(dev);
	168
	169	return dw_mci_suspend(host);
	170	}
	171
	172	static int dw_mci_exynos_resume(struct device *dev)
	173	{
	174	struct dw_mci *host = dev_get_drvdata(dev);
	175
5659eead	176	dw_mci_exynos_config_smu(host);
e2c63599 DA	177	return dw_mci_resume(host);
	178	}
	179
	180	/**
	181	* dw_mci_exynos_resume_noirq - Exynos-specific resume code
	182	*
	183	* On exynos5420 there is a silicon errata that will sometimes leave the
	184	* WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
	185	* that it fired and we can clear it by writing a 1 back. Clear it to prevent
	186	* interrupts from going off constantly.
	187	*
	188	* We run this code on all exynos variants because it doesn't hurt.
	189	*/
	190
	191	static int dw_mci_exynos_resume_noirq(struct device *dev)
	192	{
	193	struct dw_mci *host = dev_get_drvdata(dev);
89ad2be7	194	struct dw_mci_exynos_priv_data *priv = host->priv;
e2c63599 DA	195	u32 clksel;
e2c63599 DA	196
89ad2be7 AK	197	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	198	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	199	clksel = mci_readl(host, CLKSEL64);
	200	else
	201	clksel = mci_readl(host, CLKSEL);
	202
	203	if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
	204	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	205	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	206	mci_writel(host, CLKSEL64, clksel);
	207	else
	208	mci_writel(host, CLKSEL, clksel);
	209	}
e2c63599 DA	210
	211	return 0;
	212	}
	213	#else
	214	#define dw_mci_exynos_suspend NULL
	215	#define dw_mci_exynos_resume NULL
	216	#define dw_mci_exynos_resume_noirq NULL
	217	#endif /* CONFIG_PM_SLEEP */
	218
80113132	219	static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
c3665006 TA	220	{
c3665006 TA	221	struct dw_mci_exynos_priv_data *priv = host->priv;
80113132	222	u32 dqs, strobe;
c3665006	223
80113132 SJ	224	/*
	225	* Not supported to configure register
	226	* related to HS400
	227	*/
	228	if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420)
	229	return;
	230
	231	dqs = priv->saved_dqs_en;
	232	strobe = priv->saved_strobe_ctrl;
	233
	234	if (timing == MMC_TIMING_MMC_HS400) {
	235	dqs \|= DATA_STROBE_EN;
	236	strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
c6d9deda	237	} else {
80113132	238	dqs &= ~DATA_STROBE_EN;
c6d9deda SJ	239	}
c6d9deda SJ	240
80113132 SJ	241	mci_writel(host, HS400_DQS_EN, dqs);
	242	mci_writel(host, HS400_DLINE_CTRL, strobe);
	243	}
	244
	245	static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted)
	246	{
	247	struct dw_mci_exynos_priv_data *priv = host->priv;
	248	unsigned long actual;
	249	u8 div;
	250	int ret;
a2a1fed8 SJ	251	/*
	252	* Don't care if wanted clock is zero or
	253	* ciu clock is unavailable
	254	*/
	255	if (!wanted \|\| IS_ERR(host->ciu_clk))
c6d9deda SJ	256	return;
	257
	258	/* Guaranteed minimum frequency for cclkin */
	259	if (wanted < EXYNOS_CCLKIN_MIN)
	260	wanted = EXYNOS_CCLKIN_MIN;
	261
80113132 SJ	262	if (wanted == priv->cur_speed)
	263	return;
	264
	265	div = dw_mci_exynos_get_ciu_div(host);
	266	ret = clk_set_rate(host->ciu_clk, wanted * div);
	267	if (ret)
	268	dev_warn(host->dev,
	269	"failed to set clk-rate %u error: %d\n",
	270	wanted * div, ret);
	271	actual = clk_get_rate(host->ciu_clk);
	272	host->bus_hz = actual / div;
	273	priv->cur_speed = wanted;
	274	host->current_speed = 0;
	275	}
	276
	277	static void dw_mci_exynos_set_ios(struct dw_mci host, struct mmc_ios ios)
	278	{
	279	struct dw_mci_exynos_priv_data *priv = host->priv;
	280	unsigned int wanted = ios->clock;
	281	u32 timing = ios->timing, clksel;
	282
	283	switch (timing) {
	284	case MMC_TIMING_MMC_HS400:
	285	/* Update tuned sample timing */
	286	clksel = SDMMC_CLKSEL_UP_SAMPLE(
	287	priv->hs400_timing, priv->tuned_sample);
	288	wanted <<= 1;
	289	break;
	290	case MMC_TIMING_MMC_DDR52:
	291	clksel = priv->ddr_timing;
	292	/* Should be double rate for DDR mode */
	293	if (ios->bus_width == MMC_BUS_WIDTH_8)
	294	wanted <<= 1;
	295	break;
	296	default:
	297	clksel = priv->sdr_timing;
c6d9deda	298	}
80113132 SJ	299
	300	/* Set clock timing for the requested speed mode*/
	301	dw_mci_exynos_set_clksel_timing(host, clksel);
	302
	303	/* Configure setting for HS400 */
	304	dw_mci_exynos_config_hs400(host, timing);
	305
	306	/* Configure clock rate */
	307	dw_mci_exynos_adjust_clock(host, wanted);
c3665006 TA	308	}
	309
	310	static int dw_mci_exynos_parse_dt(struct dw_mci *host)
	311	{
e6c784ed	312	struct dw_mci_exynos_priv_data *priv;
c3665006 TA	313	struct device_node *np = host->dev->of_node;
	314	u32 timing[2];
	315	u32 div = 0;
e6c784ed	316	int idx;
c3665006 TA	317	int ret;
c3665006 TA	318
e6c784ed	319	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
bf3707ea	320	if (!priv)
e6c784ed	321	return -ENOMEM;
e6c784ed YK	322
	323	for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
	324	if (of_device_is_compatible(np, exynos_compat[idx].compatible))
	325	priv->ctrl_type = exynos_compat[idx].ctrl_type;
	326	}
	327
c6d9deda SJ	328	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
	329	priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
	330	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
	331	priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
	332	else {
	333	of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
	334	priv->ciu_div = div;
	335	}
c3665006 TA	336
	337	ret = of_property_read_u32_array(np,
	338	"samsung,dw-mshc-sdr-timing", timing, 2);
	339	if (ret)
	340	return ret;
	341
2d9f0bd1 YK	342	priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
2d9f0bd1 YK	343
c3665006 TA	344	ret = of_property_read_u32_array(np,
	345	"samsung,dw-mshc-ddr-timing", timing, 2);
	346	if (ret)
	347	return ret;
	348
	349	priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
80113132 SJ	350
	351	ret = of_property_read_u32_array(np,
	352	"samsung,dw-mshc-hs400-timing", timing, 2);
	353	if (!ret && of_property_read_u32(np,
	354	"samsung,read-strobe-delay", &priv->dqs_delay))
	355	dev_dbg(host->dev,
	356	"read-strobe-delay is not found, assuming usage of default value\n");
	357
	358	priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
	359	HS400_FIXED_CIU_CLK_DIV);
e6c784ed	360	host->priv = priv;
c3665006 TA	361	return 0;
	362	}
	363
c537a1c5 SJ	364	static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
c537a1c5 SJ	365	{
89ad2be7 AK	366	struct dw_mci_exynos_priv_data *priv = host->priv;
	367
	368	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	369	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	370	return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
	371	else
	372	return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
c537a1c5 SJ	373	}
	374
	375	static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
	376	{
	377	u32 clksel;
89ad2be7 AK	378	struct dw_mci_exynos_priv_data *priv = host->priv;
	379
	380	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	381	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	382	clksel = mci_readl(host, CLKSEL64);
	383	else
	384	clksel = mci_readl(host, CLKSEL);
80113132	385	clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
89ad2be7 AK	386	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	387	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	388	mci_writel(host, CLKSEL64, clksel);
	389	else
	390	mci_writel(host, CLKSEL, clksel);
c537a1c5 SJ	391	}
	392
	393	static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
	394	{
89ad2be7	395	struct dw_mci_exynos_priv_data *priv = host->priv;
c537a1c5 SJ	396	u32 clksel;
	397	u8 sample;
	398
89ad2be7 AK	399	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	400	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	401	clksel = mci_readl(host, CLKSEL64);
	402	else
	403	clksel = mci_readl(host, CLKSEL);
80113132	404
c537a1c5	405	sample = (clksel + 1) & 0x7;
80113132 SJ	406	clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
80113132 SJ	407
89ad2be7 AK	408	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 \|\|
	409	priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
	410	mci_writel(host, CLKSEL64, clksel);
	411	else
	412	mci_writel(host, CLKSEL, clksel);
80113132	413
c537a1c5 SJ	414	return sample;
	415	}
	416
	417	static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
	418	{
	419	const u8 iter = 8;
	420	u8 __c;
	421	s8 i, loc = -1;
	422
	423	for (i = 0; i < iter; i++) {
	424	__c = ror8(candiates, i);
	425	if ((__c & 0xc7) == 0xc7) {
	426	loc = i;
	427	goto out;
	428	}
	429	}
	430
	431	for (i = 0; i < iter; i++) {
	432	__c = ror8(candiates, i);
	433	if ((__c & 0x83) == 0x83) {
	434	loc = i;
	435	goto out;
	436	}
	437	}
	438
	439	out:
	440	return loc;
	441	}
	442
9979dbe5	443	static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
c537a1c5 SJ	444	{
c537a1c5 SJ	445	struct dw_mci *host = slot->host;
80113132	446	struct dw_mci_exynos_priv_data *priv = host->priv;
c537a1c5	447	struct mmc_host *mmc = slot->mmc;
c537a1c5 SJ	448	u8 start_smpl, smpl, candiates = 0;
	449	s8 found = -1;
	450	int ret = 0;
	451
c537a1c5 SJ	452	start_smpl = dw_mci_exynos_get_clksmpl(host);
	453
	454	do {
c537a1c5 SJ	455	mci_writel(host, TMOUT, ~0);
	456	smpl = dw_mci_exynos_move_next_clksmpl(host);
	457
9979dbe5	458	if (!mmc_send_tuning(mmc, opcode, NULL))
6c2c6506	459	candiates \|= (1 << smpl);
c537a1c5	460
c537a1c5 SJ	461	} while (start_smpl != smpl);
	462
	463	found = dw_mci_exynos_get_best_clksmpl(candiates);
80113132	464	if (found >= 0) {
c537a1c5	465	dw_mci_exynos_set_clksmpl(host, found);
80113132 SJ	466	priv->tuned_sample = found;
80113132 SJ	467	} else {
c537a1c5	468	ret = -EIO;
80113132	469	}
c537a1c5	470
c537a1c5 SJ	471	return ret;
	472	}
	473
c22f5e1b	474	static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
80113132 SJ	475	struct mmc_ios *ios)
	476	{
	477	struct dw_mci_exynos_priv_data *priv = host->priv;
	478
	479	dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing);
	480	dw_mci_exynos_adjust_clock(host, (ios->clock) << 1);
	481
	482	return 0;
	483	}
	484
0f6e73d0 DK	485	/* Common capabilities of Exynos4/Exynos5 SoC */
0f6e73d0 DK	486	static unsigned long exynos_dwmmc_caps[4] = {
cab3a802	487	MMC_CAP_1_8V_DDR \| MMC_CAP_8_BIT_DATA \| MMC_CAP_CMD23,
c3665006 TA	488	MMC_CAP_CMD23,
	489	MMC_CAP_CMD23,
	490	MMC_CAP_CMD23,
	491	};
	492
0f6e73d0 DK	493	static const struct dw_mci_drv_data exynos_drv_data = {
0f6e73d0 DK	494	.caps = exynos_dwmmc_caps,
c3665006	495	.init = dw_mci_exynos_priv_init,
c3665006 TA	496	.set_ios = dw_mci_exynos_set_ios,
c3665006 TA	497	.parse_dt = dw_mci_exynos_parse_dt,
c537a1c5	498	.execute_tuning = dw_mci_exynos_execute_tuning,
80113132	499	.prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning,
c3665006 TA	500	};
	501
	502	static const struct of_device_id dw_mci_exynos_match[] = {
0f6e73d0 DK	503	{ .compatible = "samsung,exynos4412-dw-mshc",
0f6e73d0 DK	504	.data = &exynos_drv_data, },
c3665006	505	{ .compatible = "samsung,exynos5250-dw-mshc",
0f6e73d0	506	.data = &exynos_drv_data, },
00fd041b YK	507	{ .compatible = "samsung,exynos5420-dw-mshc",
00fd041b YK	508	.data = &exynos_drv_data, },
6bce431c YK	509	{ .compatible = "samsung,exynos5420-dw-mshc-smu",
6bce431c YK	510	.data = &exynos_drv_data, },
89ad2be7 AK	511	{ .compatible = "samsung,exynos7-dw-mshc",
	512	.data = &exynos_drv_data, },
	513	{ .compatible = "samsung,exynos7-dw-mshc-smu",
	514	.data = &exynos_drv_data, },
c3665006 TA	515	{},
c3665006 TA	516	};
517cb9f1	517	MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
c3665006	518
9665f7f2	519	static int dw_mci_exynos_probe(struct platform_device *pdev)
c3665006	520	{
8e2b36ea	521	const struct dw_mci_drv_data *drv_data;
c3665006 TA	522	const struct of_device_id *match;
	523
	524	match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
	525	drv_data = match->data;
	526	return dw_mci_pltfm_register(pdev, drv_data);
	527	}
	528
15a2e2ab	529	static const struct dev_pm_ops dw_mci_exynos_pmops = {
e2c63599 DA	530	SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
	531	.resume_noirq = dw_mci_exynos_resume_noirq,
	532	.thaw_noirq = dw_mci_exynos_resume_noirq,
	533	.restore_noirq = dw_mci_exynos_resume_noirq,
	534	};
	535
c3665006 TA	536	static struct platform_driver dw_mci_exynos_pltfm_driver = {
c3665006 TA	537	.probe = dw_mci_exynos_probe,
7d589edc	538	.remove = dw_mci_pltfm_remove,
c3665006 TA	539	.driver = {
c3665006 TA	540	.name = "dwmmc_exynos",
20183d50	541	.of_match_table = dw_mci_exynos_match,
e2c63599	542	.pm = &dw_mci_exynos_pmops,
c3665006 TA	543	},
	544	};
	545
	546	module_platform_driver(dw_mci_exynos_pltfm_driver);
	547
	548	MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
	549	MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
	550	MODULE_LICENSE("GPL v2");
2fc546fd	551	MODULE_ALIAS("platform:dwmmc_exynos");