[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / dw_mmc-k3.c

/*
 * Copyright (c) 2013 Linaro Ltd.
 * Copyright (c) 2013 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/mmc/host.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>

#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"

/*
 * hi6220 sd only support io voltage 1.8v and 3v
 * Also need config AO_SCTRL_SEL18 accordingly
 */
#define AO_SCTRL_SEL18		BIT(10)
#define AO_SCTRL_CTRL3		0x40C

struct k3_priv {
	struct regmap	*reg;
};

static unsigned long dw_mci_hi6220_caps[] = {
	MMC_CAP_CMD23,
	MMC_CAP_CMD23,
	0
};

static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
{
	int ret;

	ret = clk_set_rate(host->ciu_clk, ios->clock);
	if (ret)
		dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);

	host->bus_hz = clk_get_rate(host->ciu_clk);
}

static const struct dw_mci_drv_data k3_drv_data = {
	.set_ios		= dw_mci_k3_set_ios,
};

static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
{
	struct k3_priv *priv;

	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->reg = syscon_regmap_lookup_by_phandle(host->dev->of_node,
					 "hisilicon,peripheral-syscon");
	if (IS_ERR(priv->reg))
		priv->reg = NULL;

	host->priv = priv;
	return 0;
}

static int dw_mci_hi6220_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct dw_mci_slot *slot = mmc_priv(mmc);
	struct k3_priv *priv;
	struct dw_mci *host;
	int min_uv, max_uv;
	int ret;

	host = slot->host;
	priv = host->priv;

	if (!priv || !priv->reg)
		return 0;

	if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
		ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
					 AO_SCTRL_SEL18, 0);
		min_uv = 3000000;
		max_uv = 3000000;
	} else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
		ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
					 AO_SCTRL_SEL18, AO_SCTRL_SEL18);
		min_uv = 1800000;
		max_uv = 1800000;
	} else {
		dev_dbg(host->dev, "voltage not supported\n");
		return -EINVAL;
	}

	if (ret) {
		dev_dbg(host->dev, "switch voltage failed\n");
		return ret;
	}

	if (IS_ERR_OR_NULL(mmc->supply.vqmmc))
		return 0;

	ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
	if (ret) {
		dev_dbg(host->dev, "Regulator set error %d: %d - %d\n",
				 ret, min_uv, max_uv);
		return ret;
	}

	return 0;
}

static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios)
{
	int ret;
	unsigned int clock;

	clock = (ios->clock <= 25000000) ? 25000000 : ios->clock;

	ret = clk_set_rate(host->biu_clk, clock);
	if (ret)
		dev_warn(host->dev, "failed to set rate %uHz\n", clock);

	host->bus_hz = clk_get_rate(host->biu_clk);
}

static int dw_mci_hi6220_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
{
	return 0;
}

static const struct dw_mci_drv_data hi6220_data = {
	.caps			= dw_mci_hi6220_caps,
	.switch_voltage		= dw_mci_hi6220_switch_voltage,
	.set_ios		= dw_mci_hi6220_set_ios,
	.parse_dt		= dw_mci_hi6220_parse_dt,
	.execute_tuning		= dw_mci_hi6220_execute_tuning,
};

static const struct of_device_id dw_mci_k3_match[] = {
	{ .compatible = "hisilicon,hi4511-dw-mshc", .data = &k3_drv_data, },
	{ .compatible = "hisilicon,hi6220-dw-mshc", .data = &hi6220_data, },
	{},
};
MODULE_DEVICE_TABLE(of, dw_mci_k3_match);

static int dw_mci_k3_probe(struct platform_device *pdev)
{
	const struct dw_mci_drv_data *drv_data;
	const struct of_device_id *match;

	match = of_match_node(dw_mci_k3_match, pdev->dev.of_node);
	drv_data = match->data;

	return dw_mci_pltfm_register(pdev, drv_data);
}

static const struct dev_pm_ops dw_mci_k3_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				pm_runtime_force_resume)
	SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
			   dw_mci_runtime_resume,
			   NULL)
};

static struct platform_driver dw_mci_k3_pltfm_driver = {
	.probe		= dw_mci_k3_probe,
	.remove		= dw_mci_pltfm_remove,
	.driver		= {
		.name		= "dwmmc_k3",
		.of_match_table	= dw_mci_k3_match,
		.pm		= &dw_mci_k3_dev_pm_ops,
	},
};

module_platform_driver(dw_mci_k3_pltfm_driver);

MODULE_DESCRIPTION("K3 Specific DW-MSHC Driver Extension");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:dwmmc_k3");
Commit	Line	Data
036f29d5 ZG	1	/*
	2	* Copyright (c) 2013 Linaro Ltd.
	3	* Copyright (c) 2013 Hisilicon Limited.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*/
	10
036f29d5	11	#include <linux/clk.h>
0293efdd	12	#include <linux/mfd/syscon.h>
036f29d5	13	#include <linux/mmc/host.h>
0293efdd	14	#include <linux/module.h>
036f29d5	15	#include <linux/of_address.h>
0293efdd	16	#include <linux/platform_device.h>
2c8ae20e	17	#include <linux/pm_runtime.h>
0293efdd ZG	18	#include <linux/regmap.h>
0293efdd ZG	19	#include <linux/regulator/consumer.h>
036f29d5 ZG	20
	21	#include "dw_mmc.h"
	22	#include "dw_mmc-pltfm.h"
	23
0293efdd ZG	24	/*
	25	* hi6220 sd only support io voltage 1.8v and 3v
	26	* Also need config AO_SCTRL_SEL18 accordingly
	27	*/
	28	#define AO_SCTRL_SEL18 BIT(10)
	29	#define AO_SCTRL_CTRL3 0x40C
	30
	31	struct k3_priv {
	32	struct regmap *reg;
	33	};
	34
af637629 JF	35	static unsigned long dw_mci_hi6220_caps[] = {
	36	MMC_CAP_CMD23,
	37	MMC_CAP_CMD23,
	38	0
	39	};
	40
036f29d5 ZG	41	static void dw_mci_k3_set_ios(struct dw_mci host, struct mmc_ios ios)
036f29d5 ZG	42	{
036f29d5 ZG	43	int ret;
036f29d5 ZG	44
0e662440	45	ret = clk_set_rate(host->ciu_clk, ios->clock);
036f29d5	46	if (ret)
0e662440	47	dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
036f29d5 ZG	48
	49	host->bus_hz = clk_get_rate(host->ciu_clk);
	50	}
	51
036f29d5 ZG	52	static const struct dw_mci_drv_data k3_drv_data = {
036f29d5 ZG	53	.set_ios = dw_mci_k3_set_ios,
036f29d5 ZG	54	};
036f29d5 ZG	55
0293efdd ZG	56	static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
	57	{
	58	struct k3_priv *priv;
	59
	60	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
	61	if (!priv)
	62	return -ENOMEM;
	63
	64	priv->reg = syscon_regmap_lookup_by_phandle(host->dev->of_node,
	65	"hisilicon,peripheral-syscon");
	66	if (IS_ERR(priv->reg))
	67	priv->reg = NULL;
	68
	69	host->priv = priv;
	70	return 0;
	71	}
	72
	73	static int dw_mci_hi6220_switch_voltage(struct mmc_host mmc, struct mmc_ios ios)
	74	{
	75	struct dw_mci_slot *slot = mmc_priv(mmc);
	76	struct k3_priv *priv;
	77	struct dw_mci *host;
	78	int min_uv, max_uv;
	79	int ret;
	80
	81	host = slot->host;
	82	priv = host->priv;
	83
	84	if (!priv \|\| !priv->reg)
	85	return 0;
	86
	87	if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
	88	ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
	89	AO_SCTRL_SEL18, 0);
	90	min_uv = 3000000;
	91	max_uv = 3000000;
	92	} else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
	93	ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
	94	AO_SCTRL_SEL18, AO_SCTRL_SEL18);
	95	min_uv = 1800000;
	96	max_uv = 1800000;
	97	} else {
	98	dev_dbg(host->dev, "voltage not supported\n");
	99	return -EINVAL;
	100	}
	101
	102	if (ret) {
	103	dev_dbg(host->dev, "switch voltage failed\n");
	104	return ret;
	105	}
	106
	107	if (IS_ERR_OR_NULL(mmc->supply.vqmmc))
	108	return 0;
	109
	110	ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
	111	if (ret) {
	112	dev_dbg(host->dev, "Regulator set error %d: %d - %d\n",
	113	ret, min_uv, max_uv);
	114	return ret;
	115	}
	116
	117	return 0;
	118	}
	119
120	static void dw_mci_hi6220_set_ios(struct dw_mci host, struct mmc_ios ios)
121	{
122	int ret;
123	unsigned int clock;
124
125	clock = (ios->clock <= 25000000) ? 25000000 : ios->clock;
126
127	ret = clk_set_rate(host->biu_clk, clock);
128	if (ret)
129	dev_warn(host->dev, "failed to set rate %uHz\n", clock);
130
131	host->bus_hz = clk_get_rate(host->biu_clk);
132	}
133
3203a827 JG	134	static int dw_mci_hi6220_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
	135	{
	136	return 0;
	137	}
	138
0293efdd	139	static const struct dw_mci_drv_data hi6220_data = {
af637629	140	.caps = dw_mci_hi6220_caps,
0293efdd ZG	141	.switch_voltage = dw_mci_hi6220_switch_voltage,
	142	.set_ios = dw_mci_hi6220_set_ios,
	143	.parse_dt = dw_mci_hi6220_parse_dt,
3203a827	144	.execute_tuning = dw_mci_hi6220_execute_tuning,
0293efdd ZG	145	};
0293efdd ZG	146
036f29d5 ZG	147	static const struct of_device_id dw_mci_k3_match[] = {
036f29d5 ZG	148	{ .compatible = "hisilicon,hi4511-dw-mshc", .data = &k3_drv_data, },
0293efdd	149	{ .compatible = "hisilicon,hi6220-dw-mshc", .data = &hi6220_data, },
036f29d5 ZG	150	{},
	151	};
	152	MODULE_DEVICE_TABLE(of, dw_mci_k3_match);
	153
	154	static int dw_mci_k3_probe(struct platform_device *pdev)
	155	{
	156	const struct dw_mci_drv_data *drv_data;
	157	const struct of_device_id *match;
	158
	159	match = of_match_node(dw_mci_k3_match, pdev->dev.of_node);
	160	drv_data = match->data;
	161
	162	return dw_mci_pltfm_register(pdev, drv_data);
	163	}
	164
2c8ae20e SL	165	static const struct dev_pm_ops dw_mci_k3_dev_pm_ops = {
	166	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	167	pm_runtime_force_resume)
	168	SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
	169	dw_mci_runtime_resume,
	170	NULL)
	171	};
036f29d5 ZG	172
	173	static struct platform_driver dw_mci_k3_pltfm_driver = {
	174	.probe = dw_mci_k3_probe,
	175	.remove = dw_mci_pltfm_remove,
	176	.driver = {
	177	.name = "dwmmc_k3",
	178	.of_match_table = dw_mci_k3_match,
2c8ae20e	179	.pm = &dw_mci_k3_dev_pm_ops,
036f29d5 ZG	180	},
	181	};
	182
	183	module_platform_driver(dw_mci_k3_pltfm_driver);
	184
	185	MODULE_DESCRIPTION("K3 Specific DW-MSHC Driver Extension");
	186	MODULE_LICENSE("GPL v2");
7026fd66	187	MODULE_ALIAS("platform:dwmmc_k3");