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a8c643ad JN |
1 | /* |
2 | * ZX Specific Extensions for Synopsys DW Multimedia Card Interface driver | |
3 | * | |
4 | * Copyright (C) 2016, Linaro Ltd. | |
5 | * Copyright (C) 2016, ZTE Corp. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/mfd/syscon.h> | |
15 | #include <linux/mmc/host.h> | |
16 | #include <linux/mmc/mmc.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/pm_runtime.h> | |
21 | #include <linux/regmap.h> | |
22 | #include <linux/slab.h> | |
23 | ||
24 | #include "dw_mmc.h" | |
25 | #include "dw_mmc-pltfm.h" | |
26 | #include "dw_mmc-zx.h" | |
27 | ||
28 | struct dw_mci_zx_priv_data { | |
29 | struct regmap *sysc_base; | |
30 | }; | |
31 | ||
32 | enum delay_type { | |
33 | DELAY_TYPE_READ, /* read dqs delay */ | |
34 | DELAY_TYPE_CLK, /* clk sample delay */ | |
35 | }; | |
36 | ||
37 | static int dw_mci_zx_emmc_set_delay(struct dw_mci *host, unsigned int delay, | |
38 | enum delay_type dflag) | |
39 | { | |
40 | struct dw_mci_zx_priv_data *priv = host->priv; | |
41 | struct regmap *sysc_base = priv->sysc_base; | |
42 | unsigned int clksel; | |
43 | unsigned int loop = 1000; | |
44 | int ret; | |
45 | ||
46 | if (!sysc_base) | |
47 | return -EINVAL; | |
48 | ||
49 | ret = regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0, | |
50 | PARA_HALF_CLK_MODE | PARA_DLL_BYPASS_MODE | | |
51 | PARA_PHASE_DET_SEL_MASK | | |
52 | PARA_DLL_LOCK_NUM_MASK | | |
53 | DLL_REG_SET | PARA_DLL_START_MASK, | |
54 | PARA_DLL_START(4) | PARA_DLL_LOCK_NUM(4)); | |
55 | if (ret) | |
56 | return ret; | |
57 | ||
58 | ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG1, &clksel); | |
59 | if (ret) | |
60 | return ret; | |
61 | ||
62 | if (dflag == DELAY_TYPE_CLK) { | |
63 | clksel &= ~CLK_SAMP_DELAY_MASK; | |
64 | clksel |= CLK_SAMP_DELAY(delay); | |
65 | } else { | |
66 | clksel &= ~READ_DQS_DELAY_MASK; | |
67 | clksel |= READ_DQS_DELAY(delay); | |
68 | } | |
69 | ||
70 | regmap_write(sysc_base, LB_AON_EMMC_CFG_REG1, clksel); | |
71 | regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0, | |
72 | PARA_DLL_START_MASK | PARA_DLL_LOCK_NUM_MASK | | |
73 | DLL_REG_SET, | |
74 | PARA_DLL_START(4) | PARA_DLL_LOCK_NUM(4) | | |
75 | DLL_REG_SET); | |
76 | ||
77 | do { | |
78 | ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG2, &clksel); | |
79 | if (ret) | |
80 | return ret; | |
81 | ||
82 | } while (--loop && !(clksel & ZX_DLL_LOCKED)); | |
83 | ||
84 | if (!loop) { | |
85 | dev_err(host->dev, "Error: %s dll lock fail\n", __func__); | |
86 | return -EIO; | |
87 | } | |
88 | ||
89 | return 0; | |
90 | } | |
91 | ||
92 | static int dw_mci_zx_emmc_execute_tuning(struct dw_mci_slot *slot, u32 opcode) | |
93 | { | |
94 | struct dw_mci *host = slot->host; | |
95 | struct mmc_host *mmc = slot->mmc; | |
96 | int ret, len = 0, start = 0, end = 0, delay, best = 0; | |
97 | ||
98 | for (delay = 1; delay < 128; delay++) { | |
99 | ret = dw_mci_zx_emmc_set_delay(host, delay, DELAY_TYPE_CLK); | |
100 | if (!ret && mmc_send_tuning(mmc, opcode, NULL)) { | |
101 | if (start >= 0) { | |
102 | end = delay - 1; | |
103 | /* check and update longest good range */ | |
104 | if ((end - start) > len) { | |
105 | best = (start + end) >> 1; | |
106 | len = end - start; | |
107 | } | |
108 | } | |
109 | start = -1; | |
110 | end = 0; | |
111 | continue; | |
112 | } | |
113 | if (start < 0) | |
114 | start = delay; | |
115 | } | |
116 | ||
117 | if (start >= 0) { | |
118 | end = delay - 1; | |
119 | if ((end - start) > len) { | |
120 | best = (start + end) >> 1; | |
121 | len = end - start; | |
122 | } | |
123 | } | |
124 | if (best < 0) | |
125 | return -EIO; | |
126 | ||
127 | dev_info(host->dev, "%s best range: start %d end %d\n", __func__, | |
128 | start, end); | |
129 | return dw_mci_zx_emmc_set_delay(host, best, DELAY_TYPE_CLK); | |
130 | } | |
131 | ||
132 | static int dw_mci_zx_prepare_hs400_tuning(struct dw_mci *host, | |
133 | struct mmc_ios *ios) | |
134 | { | |
135 | int ret; | |
136 | ||
137 | /* config phase shift as 90 degree */ | |
138 | ret = dw_mci_zx_emmc_set_delay(host, 32, DELAY_TYPE_READ); | |
139 | if (ret < 0) | |
140 | return -EIO; | |
141 | ||
142 | return 0; | |
143 | } | |
144 | ||
145 | static int dw_mci_zx_execute_tuning(struct dw_mci_slot *slot, u32 opcode) | |
146 | { | |
147 | struct dw_mci *host = slot->host; | |
148 | ||
149 | if (host->verid == 0x290a) /* only for emmc */ | |
150 | return dw_mci_zx_emmc_execute_tuning(slot, opcode); | |
151 | /* TODO: Add 0x210a dedicated tuning for sd/sdio */ | |
152 | ||
153 | return 0; | |
154 | } | |
155 | ||
156 | static int dw_mci_zx_parse_dt(struct dw_mci *host) | |
157 | { | |
158 | struct device_node *np = host->dev->of_node; | |
159 | struct device_node *node; | |
160 | struct dw_mci_zx_priv_data *priv; | |
161 | struct regmap *sysc_base; | |
162 | int ret; | |
163 | ||
164 | /* syscon is needed only by emmc */ | |
165 | node = of_parse_phandle(np, "zte,aon-syscon", 0); | |
166 | if (node) { | |
167 | sysc_base = syscon_node_to_regmap(node); | |
168 | of_node_put(node); | |
169 | ||
170 | if (IS_ERR(sysc_base)) { | |
171 | ret = PTR_ERR(sysc_base); | |
172 | if (ret != -EPROBE_DEFER) | |
173 | dev_err(host->dev, "Can't get syscon: %d\n", | |
174 | ret); | |
175 | return ret; | |
176 | } | |
177 | } else { | |
178 | return 0; | |
179 | } | |
180 | ||
181 | priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); | |
182 | if (!priv) | |
183 | return -ENOMEM; | |
184 | priv->sysc_base = sysc_base; | |
185 | host->priv = priv; | |
186 | ||
187 | return 0; | |
188 | } | |
189 | ||
190 | static unsigned long zx_dwmmc_caps[3] = { | |
191 | MMC_CAP_CMD23, | |
192 | MMC_CAP_CMD23, | |
193 | MMC_CAP_CMD23, | |
194 | }; | |
195 | ||
196 | static const struct dw_mci_drv_data zx_drv_data = { | |
197 | .caps = zx_dwmmc_caps, | |
198 | .execute_tuning = dw_mci_zx_execute_tuning, | |
199 | .prepare_hs400_tuning = dw_mci_zx_prepare_hs400_tuning, | |
200 | .parse_dt = dw_mci_zx_parse_dt, | |
201 | }; | |
202 | ||
203 | static const struct of_device_id dw_mci_zx_match[] = { | |
204 | { .compatible = "zte,zx296718-dw-mshc", .data = &zx_drv_data}, | |
205 | {}, | |
206 | }; | |
207 | MODULE_DEVICE_TABLE(of, dw_mci_zx_match); | |
208 | ||
209 | static int dw_mci_zx_probe(struct platform_device *pdev) | |
210 | { | |
211 | const struct dw_mci_drv_data *drv_data; | |
212 | const struct of_device_id *match; | |
213 | ||
214 | match = of_match_node(dw_mci_zx_match, pdev->dev.of_node); | |
215 | drv_data = match->data; | |
216 | ||
217 | return dw_mci_pltfm_register(pdev, drv_data); | |
218 | } | |
219 | ||
220 | static const struct dev_pm_ops dw_mci_zx_dev_pm_ops = { | |
221 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
222 | pm_runtime_force_resume) | |
223 | SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend, | |
224 | dw_mci_runtime_resume, | |
225 | NULL) | |
226 | }; | |
227 | ||
228 | static struct platform_driver dw_mci_zx_pltfm_driver = { | |
229 | .probe = dw_mci_zx_probe, | |
230 | .remove = dw_mci_pltfm_remove, | |
231 | .driver = { | |
232 | .name = "dwmmc_zx", | |
233 | .of_match_table = dw_mci_zx_match, | |
234 | .pm = &dw_mci_zx_dev_pm_ops, | |
235 | }, | |
236 | }; | |
237 | ||
238 | module_platform_driver(dw_mci_zx_pltfm_driver); | |
239 | ||
240 | MODULE_DESCRIPTION("ZTE emmc/sd driver"); | |
241 | MODULE_LICENSE("GPL v2"); |